OptiMOS -T Power-Transistor Product Summary V DS 55 V R DS(on),max 5) 35 mω Features Dual N-channel Logic Level - Enhancement mode AEC Q11 qualified I D 2 A PG-TDSON-8-4 MSL1 up to 26 C peak reflow 175 C operating temperature Green Product (RoHS compliant) 1% Avalanche tested Type Package Marking IPG2N6S3L-35 PG-TDSON-8-4 3N6L35 Maximum ratings, at T j =25 C, unless otherwise specified Parameter Symbol Conditions Value Unit Continuous drain current I D T C =25 C, V GS =1 V 1) 2 A T C =1 C, V GS =1 V 2) 15.5 Pulsed drain current 2) I D,pulse - 8 Avalanche energy, single pulse 2, 5) E AS I D =1A 55 mj Avalanche current, single pulse 5) I AS - 2 A Gate source voltage 4) V GS - ±16 V Power dissipation P tot T C =25 C 3 W Operating and storage temperature T j, T stg - -55... +175 C IEC climatic category; DIN IEC 68-1 - - 55/175/56 Rev. 1. page 1 28-9-23
Parameter Symbol Conditions Values Unit min. typ. max. Thermal characteristics 2) Thermal resistance, junction - case R thjc - - - 5 K/W SMD version, device on PCB R thja minimal footprint - 1-6 cm 2 cooling area 3) - 6 - Electrical characteristics, at T j =25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS = V, I D = 1 ma 55 - - V Gate threshold voltage V GS(th) V DS =V GS, I D =15 µa 1.2 1.7 2.2 Zero gate voltage drain current 5) I DSS V DS =55 V, V GS = V, T j =25 C -.1 1 µa V DS =55 V, V GS = V, T j =125 C 2) - 1 1 Gate-source leakage current 5) I GSS V GS =16 V, V DS = V - 1 1 na Drain-source on-state resistance 5) R DS(on) V GS =5 V, I D =7A - 53 62 mω V GS =1 V, I D =11A - 3 35 Rev. 1. page 2 28-9-23
Parameter Symbol Conditions Values Unit min. typ. max. Dynamic characteristics 2) Input capacitance 5) C iss - 133 173 pf Output capacitance 5) C oss V GS = V, V DS =25 V, f =1 MHz - 17 22 Reverse transfer capacitance 5) C rss - 16 24 Turn-on delay time t d(on) - 3 - ns Rise time t r V DD =27.5 V, V GS =1 V, I D =2 A, - 5 - Turn-off delay time t d(off) R G =25 Ω - 8 - Fall time t f - 9-2, 5) Gate Charge Characteristics Gate to source charge Q gs - 7 9 nc Gate to drain charge Q gd V DD =11 V, I D =2 A, - 3 4.5 Gate charge total Q g V GS = to 1 V - 18 23 Gate plateau voltage V plateau - 5.1 - V Reverse Diode Diode continous forward current 2) Diode pulse current 2) I S - - 2 A T C =25 C I S,pulse - - 8 Diode forward voltage V SD V GS = V, I F =2 A, T j =25 C Reverse recovery time 2) t rr V R =27.5 V, I F =I S, di F /dt =1 A/µs - 1. 1.3 V - 1 - ns Reverse recovery charge 2, 5) Q rr - 1 - nc 1) Current is limited by bondwire; with an R thjc =5 K/W the chip is able to carry 22A at 25 C. 2) Specified by design. Not subject to production test. 3) Device on 4 mm x 4 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 7 µm thick) copper area for drain connection. PCB is vertical in still air. 4) Qualified at -5V and +16V. 5) Per channel Rev. 1. page 3 28-9-23
1 Power dissipation 2 Drain current P tot = f(t C ); V GS 6 V; I D = f(t C ); V GS 6 V; 35 25 3 2 25 P tot [W] 2 15 15 1 1 5 5 5 1 15 2 5 1 15 2 T C [ C] T C [ C] 3 Safe operating area 4 Max. transient thermal impedance I D =f(v DS ); T C =25 C; D =; Z thjc = f(t p ) parameter: t p parameter: D =t p /T 1 1 µs 1 1 1 µs.5 1 µs 1 1 1 ms Z thjc [K/W].1.5 1-1.1 single pulse 1.1 1 1 1 1-2 1-6 1-5 1-4 1-3 1-2 1-1 1 V DS [V] t p [s] Rev. 1. page 4 28-9-23
5 Typ. output characteristics 5) 6 Typ. drain-source on-state resistance 5) I D = f(v DS ); T j = 25 C R DS(on) = f(i D ); T j = 25 C parameter: V GS parameter: V GS 8 1 V 1 3.5 V 4.5 V 5 V 6 V 6 8 4 6 V R DS(on) [mω] 6 5.5 V 2 5 V 4 4.5 V 4 V 1 V 3.5 V 2 4 6 8 V DS [V] 2 2 4 6 8 7 Typ. transfer characteristics 5) 8 Typ. drain-source on-state resistance 5) I D = f(v GS ); V DS = 6V R DS(on) = f(t j ); I D = 11 A; V GS = 1 V parameter: T j 8 6 6-55 C 5 4 25 C R DS(on) [mω] 4 175 C 2 3 1 2 3 4 5 6 7 V GS [V] 2-6 -2 2 6 1 14 18 T j [ C] Rev. 1. page 5 28-9-23
9 Typ. gate threshold voltage 1 Typ. Capacitances 5) V GS(th) = f(t j ); V GS = V DS C = f(v DS ); V GS = V; f = 1 MHz parameter: I D 2.5 1 4 2 V GS(th) [V] 1.5 1 15µA 15µA C [pf] 1 3 Coss Ciss.5 Crss -6-2 2 6 1 14 18 T j [ C] 1 2 5 1 15 2 25 3 V DS [V] 11 Typical forward diode characteristicis 5) 12 Avalanche characteristics 5) IF = f(v SD ) I A S = f(t AV ) parameter: T j 1 2 parameter: T j(start) 1 1 25 C 15 C 1 C I F [A] 1 1 I AV [A] 175 C 25 C 1 1.2.4.6.8 1 1.2 1.4 V SD [V].1 1 1 1 1 t AV [µs] Rev. 1. page 6 28-9-23
13 Avalanche energy 5) 14 Drain-source breakdown voltage E AS = f(t j ) V BR(DSS) = f(t j ); I D = 1 ma parameter: I D 125 65 1 5A 6 E AS [mj] 75 5 1A V BR(DSS) [V] 55 5 25 2A 25 5 75 1 125 15 175 T j [ C] 45-6 -2 2 6 1 14 18 T j [ C] 15 Typ. gate charge 5) 16 Gate charge waveforms V GS = f(q gate ); I D = 2 A pulsed parameter: V DD 12 V GS 1 11 V 44 V Q g 8 V GS [V] 6 4 V gs(th) 2 Q g(th) Q sw Q gate 5 1 15 2 25 Q gate [nc] Q gs Q gd Rev. 1. page 7 28-9-23
Published by Infineon Technologies AG 81726 Munich, Germany Infineon Technologies AG 28 All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1. page 8 28-9-23
Revision History Version Date Changes Revision 1. 22.9.28 Initial Final Data Sheet Rev. 1. page 9 28-9-23