Design for Testability - PDF Free Download

Design for Testability Outline Ad Hoc Design for Testability Techniques Method of test points Multiplexing and demultiplexing of test points Time sharing of I/O for normal working and testing modes Partitioning of registers and large combinational circuits Scan-Path Design Scan-path design concept Controllability and observability by means of scan-path Full and partial serial scan-paths Non-serial scan design Classical scan designs

Ad Hoc Design for Testability Techniques Method of Test Points: Block Block 2 Improving controllability and observability: Block Block 2 CP OP Block Block 2 CP OP Block is not observable, Block 2 is not controllable - controllability: CP = - normal working mode CP = - controlling Block 2 with signal - controllability: CP = - normal working mode CP = - controlling Block 2 with signal

Ad Hoc Design for Testability Techniques Method of Test Points: Block Block 2 Block is not observable, Block 2 is not controllable Improving controllability: Block CP CP2 Block Block 2 CP CP2 MUX Block 2 Normal working mode: CP =, CP2 = Controlling Block 2 with : CP =, CP2 = Controlling Block 2 with : CP2 = Normal working mode: CP2 = Controlling Block 2 with : CP =, CP2 = Controlling Block 2 with : CP =, CP2 =

Ad Hoc Design for Testability Techniques Multiplexing monitor points: To reduce the number of output pins for observing monitor points, multiplexer can be used: 2 n observation points are replaced by a single output and n inputs to address a selected observation point Disadvantage: Only one observation point can be observed at a time x x 2 x n MUX 2 n - MUX OUT Number of additional pins: (n + ) Number of observable points: [2 n ] Advantage: (n + ) << 2 n

Ad Hoc Design for Testability Techniques Multiplexing monitor points: To reduce the number of output pins for observing monitor points, multiplexer can be used: To reduce the number of inputs, a counter (or a shift register) can be used to drive the address lines of the multiplexer Disadvantage: Only one observation point can be observed at a time c 2 n - MUX Counter Number of additional pins: 2 Nmber of observable points: [2 n ] Advantage: 2 < n << 2 n OUT

Ad Hoc Design for Testability Techniques Demultiplexer for implementing control points: x DMUX CP CP2 To reduce the number of input pins for controlling testpoints, demultiplexer and a latch register can be used. 2 n - CPN Disadvantage: x x 2 x n N clock times are required between test vectors to set up the proper control values Number of additional pins: (n + ) Number of control points: 2 n- N 2 n Advantage: (n + ) << N

Ad Hoc Design for Testability Techniques Demultiplexer for implementing control points: x DMUX CP CP2 To reduce the number of input pins for controlling testpoints, demultiplexer and a latch register can be used. c 2 n - Counter CPN To reduce the number of inputs for addressing, a counter (or a shift register) can be used to drive the address lines of the demultiplexer Number of additional pins: 2 Number of control points: N Advantage: 2 << N Disadvantage: N clock times are required between test vectors to set up the proper control values

Time-sharing of outputs for monitoring To reduce the number of output pins for observing monitor points, timesharing of working outputs can be introduced: no additional outputs are needed MUX To reduce the number of inputs, again counter or shift register can be used if needed Original circuit Number of additional pins: Number of control points: N Advantage: << N

Time-sharing of inputs for controlling Normal input lines DMUX N CP CP2 CPN To reduce the number of input pins for controlling test points, time-sharing of working inputs can be introduced. To reduce the number of inputs for driving the address lines of demultiplexer, counter or shift register can be used if needed Number of additional pins: Number of control points: N Advantage: << N

Example: DFT with MUX-s and DMUX-s Given a circuit: - CP and CP2 are not controllable - CP3 and CP4 are not observable DFT task: Improve the testability by using a single control input, no additional inputs/outputs allowed 2 3 4 CP CP2 CP3 CP4 2 3 4

Example: DFT with MUX-s and DMUX-s Given a circuit: CP3 and CP4 are not observable Improving the observability Coding: T Mode Norm. Test MUX T 2 3 4 CP CP2 CP3 CP4 2 3 4 MUX MUX Result: A single pin T is needed

Example: DFT with MUX-s and DMUX-s Given a circuit: CP and CP2 are not controllable Improving the controllability T Counter Decoder Result: A single pin T is needed Q DMUX DMUX 2 3 4 FF FF Coding: CP MUX MUX Q CP2 CP3 CP4 Mode Norm. Contr Test 2 3 4 DMUX MUX x

Example: DFT with MUX-s and DMUX-s T Counter Decoder x z z x 2 2 F F z 3 3 x y 3 Q F 2 z 4 F 4 Q Mode DMUX MUX MUX 2 Norm Contr x x Test Obs Obs 2 Obs 3 DMUX DMUX FF FF CP MUX Result: A single pin T is needed 2 3 4 CP 2 CP 3 MUX 2 2 2 MUX 2 3 3 4 3 CP4

Ad Hoc Design for Testability Techniques Examples of good candidates for control points: control, address, and data bus lines on bus-structured designs enable/hold inputs of microprocessors enable and read/write inputs to memory devices clock and preset/clear inputs to memory devices (flip-flops, counters,...) data select inputs to multiplexers and demultiplexers control lines on tristate devices Examples of good candidates for observation points: stem lines associated with signals having high fanout global feedback paths redundant signal lines outputs of logic devices having many inputs (multiplexers, parity generators) outputs from state devices (flip-flops, counters, shift registers) address, control and data busses

Fault redundancy and testability x x 2 x 4 x 3 y ) ( 2 4 3 4 2 x y x x x x x x y Faults at x 2 not testable x x 2 x 4 x 3 y 3 4 4 3 4 x x x x x x x y Redundant gates are removed: Fault at x 2 not testable x 2 x Remaining gate

Ad Hoc Design for Testability Techniques Logical redundancy: Redundancy should be avoided: If a redundant fault occurs, it may invalidate some test for nonredundant faults Redundant faults cause difficulty in calculating fault coverage Much test generation time can be spent in trying to generate a test for a redundant fault Redundancy intentionally added: To eliminate hazards in combinational circuits To achieve high reliability (using error detecting circuits) T Hazard control circuitry: Redundant AND-gate Fault not testable Additional control input added: T = - normal working mode T = - testing mode

Ad Hoc Design for Testability Techniques Fault redundancy: Error control circuitry: Decoder Testable error control circuitry: Decoder No error T Error detected E = if decoder is fault-free Fault not testable Additional control input added: T - normal working mode T = - testing mode

Ad Hoc Design for Testability Techniques Partitioning of registers (counters): IN OUT IN OUT C REG REG 2 CL CL 6 bit counter divided into two 8-bit counters: Instead of 2 6 = 65536 clocks, 2x2 8 = 52 clocks needed If tested in parallel, only 256 clocks needed CP: Data Inhibit C CP: Tester Data IN CL CP: Tester Data CP: Data Inhibit OUT REG REG 2 IN CL OUT CP: Clock Inhibit OP CP: Tester Clock

Ad Hoc Design for Testability Techniques Partitioning of large combinational circuits: C C2 DMUX MUX DMUX2 C C2 How many additional inputs are needed? MUX3 MUX2 MUX4 The time complexity of test generation and fault simulation grows faster than a linear function of circuit size Partioning of large circuits reduces these costs I/O sharing of normal and testing modes is used Three modes can be chosen: - normal mode - testing C - testing C2 (bolded lines)

Scan-Path Design IN Scan-IN Combinational circuit OUT The complexity of testing is a function of the number of feedback loops and their length The longer a feedback loop, the more clock cycles are needed to initialize and sensitize patterns q R q Scan-register is a aregister with both shift and parallel-load capability T = - normal working mode Scan-OUT T = - scan mode q Scan-IN T D C T q Scan-OUT Normal mode : flip-flops are connected to the combinational circuit Test mode: flip-flops are disconnected from the combinational circuit and connected to each other to form a shift register

Scan-Path Design and Testability Two possibilities for improving controllability/observability SCAN OUT MUX OUT IN DMUX SCAN IN

Parallel Scan-Path IN Combinational circuit OUT Scan-IN Scan-OUT Scan-IN 2 R R2 In parallel scan path flip-flops can be organized in more than one scan chain Advantage: time Disadvantage: # pins Scan-OUT 2

Partial Scan-Path IN Scan-IN Scan-OUT Combinational circuit R OUT In partial scan instead of full-scan, it may be advantageous to scan only some of the flip-flops R2 Example: counter even bits joined in the scan-register

Partial Scan Path Scan-In Hierarhical test generation with Scan-Path: Control Part R 2 y 4 # R IN y y 2 y 3 y 4 M M 2 a b + * c d e M 3 R 2 Data Part Scan-Out Bus R 2 2 y 3 y R + R 2 IN 2 3 R y 2 IN + R 2 R * R 2 IN* R 2

Testing with Minimal DFT Hierarhical test generation with Scan-Path: Control Part R 2 y 4 # R IN y y 2 y 3 y 4 M M 2 a b + * c d Scan-In e M 3 R 2 Data Part Scan-Out Bus R 2 2 y 3 y R + R 2 IN 2 3 R y 2 IN + R 2 R * R 2 IN* R 2

Random Access Scan IN Scan-IN Scan-CL X-Address DC Combinational circuit q R q Scan-OUT OUT In random access scan each flip-flop in a logic network is selected individually by an address for control and observation of its state Example: Delay fault testing Y-Address DC

Selection of Test Points Test point selection approaches Improving testability for any set of pseudo-random patterns (Pseudorandom BIST) Testability measures are used to characterize the controllability and observability of the circuit (independently of the test applied) Improving testability for a given sequence of vectors (Functional BIST) Fault simulation is used for measuring the fault coverage Methods that are used: logic simulation, fault simulation, evaluation (measuring) of controllability and observability

Random BIST vs Functional BIST Random BIST Test generator Traditional functional testing Functional BIST HW overhead UUT Signature Normal operation UUT Result UUT Result Signature Reference Go/NoGo Reference Go/NoGo HW overhead Reference Go/NoGo Random test set Deterministic functional test set

Improving Testability by Inserting CPs Test sequence Circuit Fault Simulation Not detected faults Fault coverage % Circuit modification Selection of CPs

Functional BIST

Selection of Test Points Method: Simulation of given test patterns Identification of the faults that are detected The remaining faults are classified as A: Faults that were not excited B: Faults at gate inputs that were excited but not propagated to the gate output C: Faults that were excited but not propagated to circuit output The faults A and B require control points for their detection The faults C may be detected by either by observation points or by control points Control points selection should be carried out before observation points selection

Classification of Not-Detected Faults Classes A and B need controllability x x 2 x 3 x 4 x 5 Always Class A: Fault x 3 is not activated Class C: Faults at x are not propagated to the output Class B: y Faults at x 5 are not propagated through the gate Class C needs either controllability or observability

Selection of Test Points Classification of faults Given test: No Test patterns Inputs Intern. points Fault table Inputs Intern. points 2 3 4 5 a b c 2 3 4 5 a b c - - 2 - - - - - 3 - - - - x / x 2 / x 3 / a / b / x a x 2 x 3 x 4 x 5 Not detected faults: Class Faults b c Missing signals A x /: x = is missing A b /: b = is missing B x 3 /: x 3 a = is missing B a /: x 3 a = is missing C x 2 /: x x 2 = OK y

Selection of Test Points Classification of faults Given test: No Test patterns Inputs Intern. points Fault table Inputs Intern. points 2 3 4 5 a b c 2 3 4 5 a b c - - 2 - - - - - 3 - - - - x / x 2 / x 3 / a / b / x a x 2 x 3 x 4 x 5 Not detected faults: Class Faults Missing signals A x /: x = is missing A b /: b = is missing B x 3 /: x 3 a = is missing b c B a /: x 3 a = is missing C x 2 /: x x 2 = OK, but y path activation is missing

Selection of Test Points: Procedure. Selection of control points: Once control point candidates are identified for the faults A and B, a minimum number of control points (CP) can be identified This can be formulated as a minimum coverage problem where a minimum CPs are selected such that at least one CP candidate is included for each fault in A and B Control point candidates F F2 F3 F4 F5 F6 F7 F8 F9 CP CP2 CP3 CP4 CP5 Faults, not detected Selected control points

Selection of Test Points: Procedure. Selection of control points: CP CP2 F F2 CP3 F3 CP F F2 F3 Control point candidates F F2 F3 F4 F5 F6 F7 F8 F9 CP CP2 CP3 CP4 CP5 Faults, not detected Selected control points

Selection of Test Points: Procedure 2. Selection of observation points Control Test Once the CPs are selected, the given test patterns are augmented to accommodate the additional inputs assotiated with the CPs and fault simulation is performed The fault class C is updated For each fault, in C the circuit lines to which the effect of the fault propagates, are identified as a potential observation point candidates A minimum covering problem is formulated and solved to find the observation points to be added New fault simulation DMUX CP CP2 CPN Fault class C updated Minimization of control points F F2 F3 F4 F5 F6 F7 F8 F9 CP CP2 CP3 CP4 CP5

Selection of Test Points: Procedure. Selection of observation points: F F2 CP2 F3 CP3 F F2 F3 CP3 CP Control point candidates F F2 F3 F4 F5 F6 F7 F8 F9 CP CP2 CP3 CP4 CP5 Faults, not detected Selected control points

Selection of Test Points Minimization of test points: Not detected faults: Class A: x /, b / Class B: x 3 /, a /, Test point coverage: To be selected Potential control points Not detected faults x / x 3 / a / b / x = + + + + x 3 = + + + a = + + + b = + x x 2 x 3 x / x 3 / No x4 x 5 a a / c b b / Test patterns Inputs Intern. points 2 3 4 5 a b c 2 3 y

Insertion of Test Points Test point for x / All faults detected: Class A: x /, b / Class B: x 3 /, a /, x x 2 x 3 x / x 3 / x4 x 5 a a / b b / c y T = This pattern is to be repeated with T = No Test patterns Inputs Intern. points 2 3 4 5 a b c 2 3 Corrected circuit: x x 2 x 3 x / T = x 3 / a a / x4 x 5 c b b / y

Insertion of Test Points Two test points: Selected test points: Class A: x / x = (control point) Class C: x 2 / (observable point) x x 2 x 3 x / x 2 / x 3 / x4 x 5 a a / b b / c y T = This pattern is to be repeated with T = No Test patterns Inputs Intern. points 2 3 4 5 a b c 2 3 To be observed Corrected circuit: x T = T 2 x 2 x 3 x / x 2 / a x4 x 5 c b T 2 y

Selection of Test Points Minimization of monitoring points: To reduce the number of output pins for observing monitor points, exor gates can be used: Space and time compaction Additional outputs With EXOR Not accurate Space Without MUX With MUX Time MUX 2 n - OUT OUT c Counter

Selection of Test Points Minimization of monitoring points: To reduce the number of output pins for observing monitor points, signature analyzers can be used: Space and time compaction Space With SA - Accurate Additional outputs With EXOR Not accurate With MUX Time MUX 2 n - OUT SA SCAN OUT c Counter SCAN IN

Boundary Scan Standard

Boundary Scan Architecture internal logic T TDO A P TDI TMS TCK TDO internal logic T A P internal logic T A P T A P TDI TMS TCK TDI Data_in BSC TDO internal logic T A P internal logic TDO Data_out TDI Test Data IN TMS Test Mode Select TCK Test Clock TDO Test Data OUT TAP Test Acess Port

Boundary Boundary Scan Architecture Scan Internal logic Registers Data Registers TDI Device ID. Register Bypass Register TDO Instruction Register (IR)

Boundary Scan Cell To next cell From system pin To system logic From last cell Shift DR D SET CLR Q Q Clock DR For SHIFT D SET CLR Q Q Update DR For HOLD Test/Normal Used at the input or output pins

Boundary Scan Working Modes SAMPLE mode: Get snapshot of normal chip output signals (monitoring mode)

Boundary Scan Working Modes PRELOAD mode: Put data on boundary scan chain before next instruction

Boundary Scan Working Modes Extest instruction: Test off-chip circuits and board-level interconnections

Boundary Scan Working Modes INTEST instruction Feeds external test patterns in and shifts responses out

Boundary Scan Working Modes Bypass instruction: Bypasses the corresponding chip using -bit register From TDI Shift DR Clock DR D SET CLR Q Q To TDO

Boundary Scan Working Modes IDCODE instruction: Connects the component device identification register serially between TDI and TDO in the Shift-DR TAP controller state Allows board-level test controller or external tester to read out component ID Required whenever a JEDEC identification register is included in the design TDI Version Part Number Manufacturer ID TDO 4-bits Any format 6-bits Any format -bits Coded form of JEDEC

Fault Detection with Boundary Scan Short Assume wired AND Open Assume stuck-at-

Any Bridge Detection with Boundary Scan Short Assume wired AND Open Assume stuck-at- Kautz showed in 974 that a sufficient condition to detect any pair of short circuited nets was that the horizontal codes must be unique for all nets. Therefore the test length is ]log 2 (N)[

Any Fault Detection with Boundary Scan Short Suspected Wired AND short Assume wired AND Ambiguiety Open Suspected open fault SAF/ Assume stuck-at- All -s and all -s are forbidden codes because of stuck-at faults Therefore the final test length is ]log 2 (N+2)[

Fault Diagnosis with Boundary Scan Short Suspected Wired AND short Assume wired AND Ambiguiety solved Open Suspected open fault SAF/ Assume stuck-at- To improve the diagnostic resolution we have to add one bit more

Synthesis of Testable Circuits y x x3 xx2 Test generation: x x 3 x 2 y y x x3 xx2 x x 2 x 3 y 4 test patterns are needed

Synthesis of Testable Circuits Two implementations for the same circuit: x x 3 y x x3 xx2 y x x 2 x 3 y x 2 First assignment Here: 4 test patterns are needed Here: Only 3 test patterns are needed

y c Synthesis of Testable Circuits y x x3 xx2 cx 3 c2x2 c3x2x3 c4x c5x x3 c6x x2 c7x x2x3 Given: Calculation of constants: f i x x 2 x 3 y New: y x x x x x x f C = f f C = f f f 2 C 2 = f f 2 f 3 C 3 = f f f 2 f 3 f 4 C 4 = f f 4 f 5 C 5 = f f f 4 f 5 f 6 C 6 = f f 2 f 4 f 6 f 7 C 3 = f f f 2 f 3 f 4 f 5 f 6 f 7 3 3 2

Synthesis of Testable Circuits Test generation method: y x x x x x x 3 3 2 Roles of test patterns: x x 2 x 3 x x 2 x 3 y

Amusing testability: Testability as a trade-off Theorem: You can test an arbitrary digital system by only 3 test patterns if you design it approprietly Proof:? Solution: System FSM Scan-Path CC NAND