- Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight
Today s lecture MOS capacitances Inverter propagation delay Power consumption MOS Capacitances Dynamic Behavior
Dynamic Behavior of MOS Transistor G C GS C GD S D C SB C GB C DB B The Gate Capacitance
Gate Capacitance G G G S C GC C GC C GC D S D S D Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off Gate Capacitance WLC ox C GC WLC ox C GC WLC ox 2 C GC B C GCS = C GCD WLC ox 2 C GCS C GCD 2WLC ox 3 V GS 0 V DS /(V GS -V T ) 1 Capacitance as a function of VGS (with VDS = 0) Capacitance as a function of the degree of saturation
Diffusion Capacitance Junction Capacitance
Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest Capacitances in 0.25 µm CMOS process
.MODEL Parameters MOS1.MODEL Modname NMOS/PMOS <VTO=VTO...> Computing the Capacitances V DD V DD V in C gd12 M2 C db2 V out C g4 M4 V out2 M1 C db1 C w Interconnect C g3 M3 Fanout Simplified Model V in V out C L
The Miller Effect V C gd1 V out V out V V in V 2C gd1 M1 V V in M1 A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value. Computing the Capacitances
CMOS Inverters V DD Propagation Delay
CMOS Inverter Propagation Delay Approach 1 V DD t phl = C L V swing /2 I av V out ~ C L I av C L k n V DD V in = V DD CMOS Inverter Propagation Delay Approach 2 V DD t phl = f(r on.c L ) = 0.69 R on C L V out V out ln(0.5) R on C L 1 V DD 0.5 0.36 V in = V DD R on C L t
3 2.5? Transient Response V out (V) 2 1.5 1 t plh t phl t p = 0.69 C L (R eqn +R eqp )/2 0.5 0-0.5 0 0.5 1 1.5 2 2.5 t (sec) x 10-10 Design for Performance Keep capacitances small Increase transistor sizes» watch out for self-loading! Increase V DD (?)
Delay as a function of V DD 5.5 5 4.5 4 t p (normalized) 3.5 3 2.5 2 1.5 1 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 V (V) DD Device Sizing 3.8 x 10-11 3.6 (for fixed load) t p (sec) 3.4 3.2 3 2.8 2.6 2.4 2.2 Self-loading effect: Intrinsic capacitances dominate 2 2 4 6 8 10 12 14 S
NMOS/PMOS ratio 5 x 10-11 tplh tphl 4.5 t p (sec) 4 tp β = W p /W n 3.5 3 1 1.5 2 2.5 3 3.5 4 4.5 5 β Impact of Rise Time on Delay 0.35 0.3 t phl (nsec) 0.25 0.2 0.15 0 0.2 0.4 0.6 t rise (nsec) 0.8 1 t p = t step(i) + ηt step(i-1)
The Sub-Micron MOS Transistor Threshold Variations Subthreshold Conduction Parasitic Resistances Threshold Variations V T V T Long-channel threshold Low V DS threshold Threshold as a function of the length (for low V DS ) L V DS Drain-induced barrier lowering (for low L)
Sub-Threshold Conduction I D (A) 10-2 10-4 10-6 10-8 Quadratic Linear The Slope Factor I D ~ I 0 e qvgs nkt, C n =1+ C S is V GS for I D2 /I D1 =10 D ox 10-10 Exponential 10-12 V T 0 0.5 1 1.5 2 2.5 V GS (V) Typical values for S: 60.. 100 mv/decade Sub-Threshold I D vs V GS qvgs nkt I D I0e 1 e qvds = kt V DS from 0 to 0.5V
Sub-Threshold I D vs V DS I D qvgs qvds = nkt kt I e 0 1 e ( 1+ λ V ) DS V GS from 0 to 0.3V Power Dissipation
Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors Dynamic Power Dissipation Vdd Vin Vout C L Energy/transition = C L * V dd 2 Power = Energy/transition * f = C L * V dd 2 * f Not a function of transistor sizes! Need to reduce C L, V dd, and f to reduce power.
Modification for Circuits with Reduced Swing V dd V dd V dd -V t C L E 0 1 = C L V dd ( V dd V t ) Can exploit reduced swing to lower power (e.g., reduced bit-line swing in memory) Adiabatic Charging 2 2 2
Adiabatic Charging Node Transition Activity and Power Consider switching a CMOS gate for N clock cycles E = C V N L 2 nn dd ( ) E N : the energy consumed for N clock cycles n(n): the number of 0->1 transition in N clock cycles P = lim avg N E N ------- f N clk = nn ( ) lim ------------ C N N L V 2 fclk dd α 0 1 = nn ( ) lim ------------ N N P avg = α 0 1 C L V 2 fclk dd
Short Circuit Currents Vd d Vin Vout C L 0.15 I VDD (ma) 0.10 0.05 0.0 1.0 2.0 3.0 V in (V) 4.0 5.0 How to keep Short-Circuit Currents Down? Short circuit current goes to zero if t fall >> t rise, but can t do this for cascade logic, so...
Minimizing Short-Circuit Power 8 7 6 Vdd =3.3 rm P no 5 4 3 Vdd =2.5 2 1 Vdd =1.5 0 0 1 2 3 4 5 t sin /t sout Leakage Vdd Vout Drain Junction Leakage Sub-Threshold Current Sub-threshold current one of most compelling issues in low-energy circuit design!
Reverse-Biased Diode Leakage GATE p + p+ N Reverse Leakage Current + - V dd I DL = J S A JS = 10-100 pa/µm2 at 25 deg C for 0.25µm CMOS JS doubles for every 9 deg C! Subthreshold Leakage Component
Static Power Consumption Vdd I stat V out V in =5V C L P stat = P (In=1).V dd. I stat Wasted energy Should be avoided in most cases, but could help reducing energy in others (e.g. sense amps) Principles for Power Reduction Prime choice: Reduce voltage!» Recent years have seen an acceleration in supply voltage reduction» Design at very low voltages still open question (0.6 0.9 V by 2010!) Reduce switching activity Reduce physical capacitance» Device Sizing: for F=20 f opt (energy)=3.53, f opt (performance)=4.47