Designing ombinational Logic ircuits dapted from hapter 6 of Digital Integrated ircuits Design Perspective Jan M. Rabaey et al. opyright 2003 Prentice Hall/Pearson 1 ombinational vs. Sequential Logic In ombinational Logic ircuit In ombinational Logic ircuit State ombinational Sequential put = f(in) put = f(in, Previous In) 2
Static MOS ircuit t every point in time (except during the switching transients) each gate output is connected to either or V ss via a low-resistive path. The outputs of the gates assume at all times the value of the oolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. 3 Static omplementary MOS In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only F(In1,In2, InN) PUN and PDN are dual logic networks 4
NMOS Transistors in Series/Parallel onnection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high X Y Y = X if and X Y Y = X if OR NMOS Transistors pass a strong 0 but a weak 1 5 PMOS Transistors in Series/Parallel onnection PMOS switch closes when switch control input is low X Y Y = X if ND = + X Y Y = X if OR = PMOS Transistors pass a strong 1 but a weak 0 6
Threshold Drops PUN S D D 0 V GS S 0 -V Tn L L PDN D L 0 V GS S L V Tp S D 7 omplementary MOS Logic Style 8
Example Gate: NND 9 Example Gate: NOR 10
omplex MOS Gate D D OUT = D + ( + ) 11 onstructing a omplex Gate D F SN1 D F SN4 SN2 SN3 D F (a) pull-down network (b) Deriving the pull-up network hierarchically by identifying sub-nets D (c) complete gate 12
ell Design Standard ells General purpose logic an be synthesized Same height, varying width Datapath ells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width 13 Standard ell Layout Methodology 1980s Routing channel signals GND 14
Standard ell Layout Methodology 1990s Mirrored ell No Routing channels M2 M3 GND Mirrored ell GND 15 Standard ells N Well ell height 12 metal tracks Metal track is approx. 3λ + 3λ Pitch = repetitive distance between objects ell height is 12 pitch 2λ In ell boundary GND Rails ~10λ 16
Standard ells With minimal diffusion routing With silicided diffusion In M 2 In In M 1 GND GND 17 Standard ells 2-input NND gate GND 18
Stick Diagrams ontains no dimensions Represents relative positions of transistors Inverter NND2 GND In GND 19 Stick Diagrams j Logic Graph X PUN X = ( + ) X i i j GND PDN 20
Two Versions of ( + ) X X GND GND 21 onsistent Euler Path X X i j GND 22
OI22 Logic Graph X PUN D D X = (+) (+D) X D D GND PDN 23 Example: x = ab+cd x x b c b c x x a d a d GND GND (a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d} x GND a b c d (c) stick diagram for ordering {a b c d} 24
Multi-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance 25 Properties of omplementary MOS Gates Snapshot High noise margins: V OH and V OL are at and GND, respectively. No static power consumption: There never exists a direct path between and V SS (GND) in steady-state mode. omparable rise and fall times: (under appropriate sizing conditions) 26
MOS Properties Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratioless lways a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path steady state between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistors 27 Switch Delay Model R eq R p R p R p R p R n L R n L R p int R n NND2 int INV R n R n L NOR2 28
Input Pattern Effects on Delay R p R n R n R p L int Delay is dependent on the pattern of inputs Low to high transition both inputs go low delay is 0.69 R p /2 L one input goes low delay is 0.69 R p L High to low transition both inputs go high delay is 0.69 2R n L 29 Delay Dependence on Input Patterns Voltage [V] 3 2.5 2 1.5 1 0.5 ==1 0 =1, =1 0 =1 0, =1 0 0-0.5 100 200 300 400 time [ps] Input Data Pattern ==0 1 =1, =0 1 = 0 1, =1 ==1 0 =1, =1 0 = 1 0, =1 Delay (psec) 30 67 64 61 45 80 81 NMOS = 0.5µm/0.25 µm PMOS = 0.75µm/0.25 µm L = 100 ff
Transistor Sizing R p R p 2 2 4 R p 2 R n L 4 R p int 2 R n int 1 R n R n 1 L 31 Transistor Sizing a omplex MOS Gate 4 3 8 6 8 6 D 4 6 D 1 2 2 2 OUT = D + ( + ) 32
Fan-In onsiderations D D 3 2 1 L Distributed R model (Elmore delay) t phl = 0.69 R eqn ( 1 +2 2 +3 3 +4 L ) Propagation delay deteriorates rapidly as a function of fan-in quadratically in the worst case. 33 t p as a Function of Fan-In t p (psec) 1250 1000 750 500 250 t phl t plh linear 0 2 4 6 8 10 12 14 16 fan-in t p quadratic Gates with a fan-in greater than 4 should be avoided. 34
t p as a Function of Fan- t p (psec) t p NOR2 t p NND2 t p INV 2 4 6 8 10 12 14 16 eff. fan-out ll gates have the same drive current. Slope is a function of driving strength 35 t p as a Function of Fan-In and Fan- Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to L t p = a 1 FI + a 2 FI 2 + a 3 FO 36
Fast omplex Gates: Design Technique 1 Transistor sizing as long as fan-out capacitance dominates Progressive sizing In N MN L Distributed R line In 3 M3 3 M1 > M2 > M3 > > MN (the fet closest to the output is the smallest) In 2 In 1 M2 M1 2 1 an reduce delay by more than 20%; decreasing gains as technology shrinks 37 Fast omplex Gates: Design Technique 2 Transistor ordering critical path critical path In 3 1 In 2 1 In 1 0 1 M3 0 1 charged L In 1 M3 charged L M2 2 charged In 2 1 M2 2 discharged In M1 charged 3 1 M1 discharged 1 1 delay determined by time to discharge L, 1 and 2 delay determined by time to discharge L 38
Fast omplex Gates: Design Technique 3 lternative logic structures F = DEFGH 39 Fast omplex Gates: Design Technique 4 Isolating fan-in from fan-out using buffer insertion L L 40
Fast omplex Gates: Design Technique 5 Reducing the voltage swing t phl = 0.69 (3/4 ( L )/ I DSTn ) = 0.69 (3/4 ( L V swing )/ I DSTn ) linear reduction in delay also reduces power consumption ut the following gate is much slower! Or requires use of sense amplifiers on the receiving end to restore the signal level (memory design) 41 Ratioed Logic 42
Ratioed Logic Resistive Load R L F Depletion Load V T < 0 F PMOS Load V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudo-nmos Goal: to reduce the number of devices over complementary MOS 43 Ratioed Logic Resistive Load R L N transistors + Load V OH = F V OL = R PN R PN + R L In 1 In 2 In 3 PDN ssymetrical response Static power consumption V SS t pl = 0.69 R L L 44
ctive Loads Depletion Load V T < 0 PMOS Load F V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS depletion load NMOS pseudo-nmos 45 Pseudo-NMOS D F L V OH = (similar to complementary MOS) V2 k n ( V OL k DD V Tn )V p OL ------------- = ------ ( V 2 2 DD V Tp ) 2 V OL ( V DD V T ) 1 1 k p = ------ (assuming that V k T = V Tn = V Tp ) n SMLLER RE & LOD UT STTI POWER DISSIPTION!!! 46
Pseudo-NMOS VT 3.0 2.5 2.0 W/L p = 4 V out [V] 1.5 1.0 W/L p = 2 0.5 W/L p = 0.5 W/L p = 0.25 W/L p = 1 0.0 0.0 0.5 1.0 1.5 2.0 2.5 V in [V] 47 Improved Loads Enable M1 M2 M1 >> M2 F D L daptive Load 48
Improved Loads (2) M1 M2 PDN1 PDN2 V SS V SS Differential ascode Voltage Switch Logic (DVSL) 49 DVSL Example XOR-NXOR gate 50
DVSL Transient Response 2.5 V ol ta ge [V] 1.5 0.5,, -0.5 0 0.2 0.4 0.6 0.8 1.0 Time [ns] 51 Pass-Transistor Logic 52
Pass-Transistor Logic Inputs Switch Network N transistors No static consumption 53 Example: ND Gate 0 F = 54
NMOS-Only Only Logic In x 0.5µm/0.25µm 1.5µm/ 0.25µm 0.5µm/ 0.25µm Voltage [V] 3.0 2.0 1.0 x In 0.0 0 0.5 1 1.5 2 Time [ns] 55 NMOS-only Switch = 2.5V = 2.5 V = 2.5 V = 2.5 V M n M 2 L M 1 V does not pull up to 2.5V, but 2.5V -V TN Threshold voltage loss causes static power consumption NMOS has higher threshold than PMOS (body effect) 56
NMOS Only Logic: Level Restoring Transistor Level Restorer M n M r X M 2 M 1 dvantage: Full Swing Restorer adds capacitance, takes away pull down current at X Ratio problem 57 Restorer Sizing Voltage [V] 3.0 2.0 1.0 W/L r =1.75/0.25 W/L r =1.50/0.25 W/L r =1.0/0.25 W/L r =1.25/0.25 Upper limit on restorer size Pass-transistor pull-down can have several transistors in stack 0.0 0 100 200 300 400 500 Time [ps] 58
Solution 2: Single Transistor Pass Gate with V T =0 0V 2.5V 0V 2.5V WTH OUT FOR LEKGE URRENTS 59 omplementary Pass Transistor Logic Pass-Transistor Network F (a) Inverse Pass-Transistor Network F F= F=+ F= ΒÝ (b) F= F=+ F= ΒÝ ND/NND OR/NOR EXOR/NEXOR 60
Solution 3: Transmission Gate = 2.5 V = 2.5 V L = 0 V 61 Resistance of Transmission Gate 30 R n 2.5 V Rn Resistance, ohms 20 10 R p R n R p 2.5 V 0 V R p V ou t 0 0.0 1.0 2.0 V ou t, V 62
Pass-Transistor ased Multiplexer S S S M 2 S F M 1 S GND In 1 S S In 2 63 Transmission Gate XOR M2 M1 F M3/M4 64
Delay in Transmission Gate Networks 2.5 2.5 2.5 2.5 In V 1 V i-1 V i V i+1 V n-1 V n 0 0 0 0 (a) In R eq R V eq R eq R 1 V i V i+1 V eq n-1 V n m (b) R eq R eq R eq R eq R eq R eq In (c) 65 Delay Optimization 66
Transmission Gate Full dder P P i i P S Sum Generation P P P o arry Generation i i Setup i P Similar delays for sum and carry 67 Dynamic Logic 68
Dynamic MOS In static circuits at every point in time (except when switching) the output is connected to either GND or via a low resistance path. fan-in of n requires 2n (n N-type + n P-type) devices Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. requires on n + 2 (n+1 N-type + 1 P-type) transistors 69 Dynamic Gate In 1 In 2 In 3 PDN M e L M e Two phase operation Precharge (LK = 0) Evaluate (LK = 1) 70
Dynamic Gate In 1 In 2 In 3 PDN M e L Two phase operation Precharge ( = 0) Evaluate ( = 1) M e off on off on 1 (()+) 71 onditions on put Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. Inputs to the gate can make at most one transition during evaluation. put can be in the high impedance state during and after evaluation (PDN off), state is stored on L 72
Properties of Dynamic Gates Logic function is implemented by the PDN only number of transistors is N + 2 (versus 2N for static complementary MOS) Full swing outputs (V OL = GND and V OH = ) Non-ratioed - sizing of the devices does not affect the logic levels Faster switching speeds reduced load capacitance due to lower input capacitance ( in ) reduced load capacitance due to smaller output loading (out) no I sc, so all the current provided by PDN goes into discharging L 73 Properties of Dynamic Gates Overall power dissipation usually higher than static MOS no static current path ever exists between and GND (including P sc ) no glitching higher transition probabilities extra load on PDN starts to work as soon as the input signals exceed V Tn, so V M, V IH and V IL equal to V Tn low noise margin (NM L ) Needs a precharge/evaluate clock 74
Issues in Dynamic Design 1: harge Leakage LK M e L V Evaluate Precharge Leakage sources Dominant component is subthreshold current 75 Solution to harge Leakage Keeper M kp L M e Same approach as level restorer for pass-transistor logic 76
Issues in Dynamic Design 2: harge Sharing L harge stored originally on L is redistributed (shared) over L and leading to reduced robustness =0 M e 77 harge Sharing Example L =50fF a =15fF! b =15fF c =15fF d =10fF 78
harge Sharing case 1) if V out < V Tn L = L V out ( t) + a ( V Tn ( V X )) M a X L V out or = V out ( t) = a -------V ( DD V Tn ( V X )) L = 0 M b a case 2) if V out > V Tn M e b a V out = -------------------- a + L 79 Solution to harge Redistribution M kp M e Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power) 80
Issues in Dynamic Design 3: ackgate oupling =0 L1 1 =1 2 =0 L2 In =0 M e Dynamic NND Static NND 81 ackgate oupling Effect 3 Voltage 2 1 1 0 In 2-1 0 2 Time, ns 4 6 82
Voltage Issues in Dynamic Design 4: lock Feedthrough M e L oupling between and input of the precharge device due to the gate to drain capacitance. So voltage of can rise above. The fast rising (and falling edges) of the clock couple to. 83 lock Feedthrough 2.5 lock feedthrough In 1 In 2 1.5 In 3 In 4 0.5 In & -0.5 0 0.5 Time, ns 1 lock feedthrough 84
Other Effects apacitive coupling Substrate coupling Minority charge injection Supply noise (ground bounce) 85 ascading Dynamic Gates V In 1 2 In M e M e 1 V Tn 2 V t Only 0 1 transitions allowed at inputs! 86
Domino Logic In 1 In 2 1 1 1 0 PDN 1 0 0 0 1 In 4 M kp PDN 2 In 3 In 5 M e M e 87 Why Domino? In i In j PDN In i PDN In i PDN In i PDN In j In j In j Like falling dominos! 88
Properties of Domino Logic Only non-inverting logic can be implemented Very high speed static inverter can be skewed, only L-H transition Input capacitance reduced smaller logical effort 89 Designing with Domino Logic 1 M r 2 In 1 In 2 PDN In 4 PDN In 3 an be eliminated! M e M e Inputs = 0 during precharge 90
Footless Domino 1 2 n 0 1 0 1 0 1 In 1 1 0 In 2 1 0 In 3 In n 1 0 1 0 The first gate in the chain needs a foot switch Precharge is rippling short-circuit current solution is to delay the clock for each stage 91 Differential (Dual Rail) Domino = off on M kp M kp 1 0 1 0!! = M e Solves the problem of non-inverting logic 92
np-mos In 1 In 2 In 3 PDN M e 1 1 1 0 1 In 4 In 5 M e PUN 0 0 0 1 2 (to PDN) Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN 93 NOR Logic In 1 In 2 In 3 PDN M e 1 1 1 0 1 In 4 In 5 M e PUN 0 0 0 1 2 (to PDN) to other PDN s to other PUN s WRNING: Very sensitive to noise! 94