Technology Development for InGaAs/InP-channel MOSFETs

MRS Spring Symposium, Tutorial: Advanced CMOS Substrates, Devices, Reliability, and Characterization, April 13, 2009, San Francisco Technology Development for InGaAs/InP-channel MOSFETs Mark Rodwell University of California, Santa Barbara rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax

Scope of Presentation Topic of discussion is channel materials for CMOS...the potential use of III-V materials...and their advantages and limitations To understand this, we must examine in some detail MOSFET scaling limits

Zero th -Order MOSFET Operation

Bipolar Transistor ~ MOSFET Below Threshold Vbe Vce I c Because emitter energy distribution is I exp( qv c be / kt ) thermal (exponential) Almost all electrons reaching base pass through it I c varies little with collector voltage

Field-Effect Transistor Operation source gate drain Positive Gate Voltage reduced energy barrier increased drain current

FETs: Computing Their Characteristics C gs ~ εa/ D C d ch I d = Q / τ where τ = Lg / velectron δq = C gs δv gs + C d ch δv ds δi d = g m δv gs + G ds δv ds where g m = C gs / τ and G gd = C d ch / τ

FET Characteristics I D increasing V GS C gs ~ εa/ / D C d chh V DS δ I d = g m δ V gs + G ds δ V ds g = C / τ G = C / τ τ = L / v m gs / gd d ch g electron

FET Subthreshold Characteristics δv gate = δv ox + δv channel = δ ( qns ) δ ( qn + C qn ox s s ) kt q Strong gate drive : channel charge varies linearly with V Weak gate drive : channel charge varies exponentially withv gs gs

Classical Long-Channel MOSFET Theory Assumptions : 1) Moderate lateral field E in channel. 2) Transport modeled by drift/diffusion J = qμ n( x) E n + qd n n ( x ) x 3) Exit tveoctyat velocity end edof pinched - off channel ca : v = v = kt / m exit thermal *

Classic Long-Channel MOSFET Theory I D Ohmic constant-current t t I d mobility-limited increasing V GS velocity-limited V DS mobility limited current V th For drain voltages larger than saturation : 2 I ( V ) / 2L D, μ = μcoxwg Vgs velocity limited current I = c W v ( V th V D, v ox g exit gs th ) g V gs Generalized Expression 2 I D + I I D, v I D D, μ = 1

Classic Long-Channel FET : Far Above Threshold I d ΔV V th V gs I D c where ox W v g exit ΔV V = v exit L ( Vgs Vth ΔV ) for ( Vgs Vth) / g / μ ΔV >> 1

Exponential, Square-Law, Linear FET Characteristics

Relevance of DC Parameters Digital circuit speed largely controlled by on-state current Standby power consumption controlled by off-state current Dynamic power consumption controlled by supply Voltage Examine VLSI Power & Delay Relationships

Zero th -Order VLSI Performance Analysis

CMOS Power Dissipation & Gate Delay V dd I on C wire C C PFET Gate delay τ gate C total V dd / 2I on = ( C wire + C NFET wiring capacitance usually dominates + C PFET ) V dd / 2I on C NFET Dynamic dower dissipation : P dynamic C V 2 2 = total dd frequency (switching probability) Off state current I off / I on > exp( qv / nkt ) th I off V dd Static Dissipation P static > I off V dd Tradeoff between static and dynamic dissipation : P dynamic ~ C wire V 2 dd f p P static ~ V dd I on e qv th / kt

Why Large Current Density is Needed FET with n = 6 fingers, each of widthw g total width = nw g W g G S D S D S D S G To drive C wire requires current at delay τ, I = C d wire V dd / 2τ. V dd C PFET I on C wire If I d /Wg is small, large FETs are needed. Large FETs long wires large Cwire. C NFET

Device Requirements High on-state current per unit gate width Low off-state current subthreshold slope Low device capacitance; but only to point where wires dominate Low supply voltage: probably 0.5 to 0.7 V

What Are Our Goals? Low off-state current (10 na/μm) for low static dissipation good subthreshold slope minimum L g / T ox low gate tunneling, low band-band tunneling Low delay C FET ΔV/I d in gates where transistor capacitances dominate. ~1 ff/μm parasitic capacitances low C gs is desirable, but high I d is imperative Low delay C wire ΔV/I d in gates where wiring capacitances dominate. large FET footprint long wires between gates need high I d / W g ; target ~5 ma/μm @ ΔV= 0.7V target ~ 3 ma/μm @ ΔV= 0.5V

Improving FETs by Scaling

Simple FET Scaling Goal double transistor bandwidth when used in any circuit reduce 2:1 all capacitances and all transport delays keep constant all resistances, voltages, currents All lengths, widths, thicknesses reduced 2:1 S/D contact resistivity reduced 4:1 gs m C gd / W g / g ~ ε g / W ~ vε / T C / W ~ ε L / T C gs W gs, f / g g ~ ε g ox ox If T ox cannot scale with gate length, C parasitic / C gs increases, g m / W g does not increase hence C parasitic /g m does not scale C / W ~ ε L / T sb g c sub

FET scaling: Output Conductance & DIBL ( gs C expression neglects D.O.S. effects) Cgs ~ εwε Wg Lg / Tox C d ch ~ ε Wg I d = Q / τ where δ Q = C δ V + gs gs C d ch δ V ds transconductance output conductance Keep L g / T ox constant as we scale L g

FET Scaling Laws LG Changes required to double transistor bandwidth: ( ) gate width W G parameter change gate length decrease 2:1 gate dielectric capacitance density increase 2:1 gate dielectric equivalent thickness decrease 2:1 channel electron density increase 2:1 source & drain contact resistance decrease 4:1 current density (ma/μm) increase 2:1

nm Transistors: it's all about the interfaces Metal-semiconductor interfaces (Ohmic contacts): very low resistivity Dielectric-semiconductor interfaces (Gate dielectrics): very high capacitance density Transistor & IC thermal resistivity.

Why Consider MOSFETs with III-V Channels? If FETs cannot be further scaled, instead increase electron velocity: I d / W g = qn s v I d / Q transit = v / L g III-V materials lower m* higher velocity ( need > 1000 cm 2 /V-s mobility) Candidate materials (?) In x Ga 1-x As, InP, InAs ( InSb, GaAs) Difficulties: High-K dielectrics III-V growth on Si building MOSFETs low m* constrains vertical scaling, reduces drive current

III-V CMOS: The Benefit Is Low Mass, Not High Mobility Simple dif drift - diffusion i theory, nondegenerate, far above threshold h : I D c ox W v g injection ( V V ΔV ) gs th where vinjection ~ vthermal = ( kt / * m ) 1/2 I d V th ΔV = v injection L g / μ Ensure that ΔV V << ( V th ) gs V ~ 700 mv V gs low effective mass high currents mobilities above ~ 1000 cm 2 /V-s of little benefit at 22 nm Lg

III-V MOSFETs for VLSI What is it? MOSFET with an InGaAs channel Why do it? low electron effective mass higher electron velocity more current, less charge at a given insulator thickness & gate length very low access resistance What are the problems? low electron effective mass constraints on scaling! must grow high-k on InGaAs, must grow InGaAs on Si Device characteristics must be considered in more detail

III-V MOSFET Characteristics

Low Effective Mass Impairs Vertical Scaling Shallow electron distribution needed for high g m / G ds ratio, low drain-induced i d d barrier lowering. Energy of L th well state L 2 / * 2 m T well For thin wells, only 1st state can be populated. For very thin wells, 1st state approaches L-valley.. Only one vertical state in well. Minimum ~ 5 nm well thickness. Hard to scale below 22 nm L g.

Semiconductor (Wavefunction Depth) Capacitance Bound state energy E L / m 2 * 2 well T well. Semiconductor capacitance c semiconductor = ε /T semi Energy(eV V) 3 2 1 0-1 -2-3 -4 T semi 0 50 100 150 200 250 Y (Ang.)

Density-Of-States Capacitance E f Ewell = n s /( nm * / πh 2 ) (bidirectional motion) V V = ρ / f well s c dos where c dos = q 2 nm * / π h 2 and n is the # of band minima Two implications: - With N s >10 13 /cm 2, electrons populate satellite valleys Fischetti et al, IEDM2007 - Transconductance dominated by finite state density Solomon & Laux, IEDM2001

Current Including Density of States, Wavefunction Depth Simple dif drift - diffusion i theory, nondegenerate, far above threshold h : I D c eq W v g thermal ( V V ΔV ) gs th where1/c 1 eq = 1/cox + 1/csemiconduc tor + /cdos I d V gs V th...but with III-V materials, we must also consider degenerate carrier concentrations.

( Lundstrom, Current of Degenerate & Ballistic FET Natori, Laux, Solomon, Fischetti, Asbeck,...) Density of states : dn s / de f = n m * / 2πh 2 (unidirectional motion) Highly degenerate : electron density : Fermi velocity : v f * 2 ns = n ( m / 2πh )( E f Ec), * 1/ 2 = ( 2( E E ) / m ), Mean electron velocity : v = (4 / 3π ) v f c f. Current density : J = qn s v 5/ 2 * 2 q n ( m ) 1/ ( E E ) / q ) 3/ 2 2 f c q = 2 2 3π h ma m = n 84 m μ m * 0 1/ 2 E f E 1eV c 3/ 2 3/ 2

2D vs. 1D Field-Effect Transistors in Ballistic Limit Drain I d E W g gate gate 2D - FET; InGaAs channel ( m 1/ 2 / m 3/ 2 = 0.04) * ma m E f Ec ma E f E J 84 = 17 μm m 1eV μm 1eV for 0.3eV Fermi level shift in semiconductor. * 0 3/ 2 ma = 2.8 m 0 μ c L g Source Drains I d Array of 1D - FETs; 5 nm InGaAs wells @ 6 nm pitch E W g gate L g gate E well 2 2 h π = = 0.37 ev, g 2 m, well 2m * T well = 2q 78 μa E f Ec ma E f Ec J = = 13 6 nm 1eV μm 1eV for 0.3eV Fermi level shift in semiconductor 2 / h = 78μS ma = 3.9 μm Sources

2D FET vs. Carbon Nanotube FET Drain W g gate I d gate 2D - FET; InGaAs channel ( m * / m 3/ 2 = 0.04) ma E ma f E c J 17 = 2.8, μm 1eV μm for 0.3eV Fermi level shift in semiconductor. 0 L g Source Drains gate Array of g m, tube carbon nanotubes, = 2q 2 / h = 78μS 5 nm pitch W g L g 78 μ A E f Ec ma E f E J = = 15.5 5 nm 1eV μm 1eV for 0.3eV Fermi level shift in semiconductor c = ma 4.7 μm Sources

Ballistic/Degenerate Drive Current vs. Gate Voltage More careful analyses by Taur & Asbeck Groups, UCSD; Fischetti Group: U-Mass: IEDM2007

Drive Current in the Ballistic & Degenerate Limits J ma = K 84 μm 025 0.25 0.2 V gs V 1V th 3/ 2, where K = * 1/ 2 ( m mo ) * ( 1+ ( c / c ) n ( m / m )) 3/ 2 dos, o n 0.7 nm, n=6 0.4 nm, n=6 ox o Error bars on Si data points correct for (E f -E c )>> kt approximation K 0.15 0.1 00 0.05 0.8 nm, n=1 n = # band minima 1.0 nm, n=1 c dos,o = density of states capacitance for m*=m o & n=1 EOT includes wavefunction depth (0.5 nm for 3.5 nm InGaAs well) 0 0.01 0.1 1 m*/m o

High Drive Current Requires Low Access Resistance sidewall source contact metal gate gate dielectric drain contact N+ source N+ drain quantum well / channel barrier substrate For <10% impact on drive current, I D R S /( V V ) < DD th 0.1 Target I D / W g ~ 1.5 ma/ μm @ ( V DD V th ) = 0.3 V Target I D / W g ~ 3 ma/ μm @ ( V DD V th ) = 0.5 V R s W g < 15 20 Ω μm

Materials Selection; What channel material should we use?

Common III-V Semiconductors B. Brar 450 InSb 220 GaSb 770 1350 200 InAs AlSb 1550 AlAs 2170 200 GaAs 1420 500 450 InGaAs 760 InAlAs 1460 250 InP 1350 InGaP 1900 360 150 200 550 170 200 6.48 A lattice constant 6.48 A lattice constant 5.65 A lattice constant; grown on GaAs 5.87 A lattice constant; grown on InP

Semiconductor & Metal Band Alignments M. Wistey

Materials of Interest Source: Ioffe Institute http://www.ioffe.rssi.ru/sva/nsm/semicond rough #s only material Si Ge GaAs InP In 0.53 Ga 0.47 As InAs n 6 6 1 1 1 1 m*/m0 m/m0 0.98 m l 1.6 m l 0.063 0.08 0.04 0.023 0.19 m t 0.08 m t Γ-(L/X) ( ) separation, ev -- -- 0.29 ~0.5 0.5 0.73 bandgap, ev 1.12 0.66 1.42 1.34 0.74 0.35 mobility, cm 2 /V-s 1000 2000 5000 3000 10,000 25,000 high-field velocity 1E7 1E7 1-2E7 3.5E7 3.5E7???

Drive Current in the Ballistic & Degenerate Limits J ma = K 84 μm 025 0.25 0.2 V gs V 1V th 3/ 2, where K = * 1/ 2 ( m mo ) * ( 1+ ( c / c ) n ( m / m )) 3/ 2 dos, o n 0.7 nm, n=6 0.4 nm, n=6 ox o Error bars on Si data points correct for (E f -E c )>> kt approximation K 0.15 0.1 00 0.05 0.8 nm, n=1 n = # band minima Ge Si c dos,o = density of 1.0 nm, n=1 InGaAs InP, states capacitance for m*=m o & n=1 EOT includes wavefunction depth (0.5 nm for 3.5 nm InGaAs well) 0 0.01 0.1 1 m*/m o

Intervalley Separation Source: Ioffe Institute http://www.ioffe.rssi.ru/sva/nsm/semicond Intervalley separation sets: -high-field velocity through intervalley scattering -maximum electron density in channel without increased carrier effective mass

Choosing Channel Material: Other Considerations Ge: low bandgap GaAs: low intervalley separation InP: InGaAs InAs: good intervalley separation Good contacts only via InGaAs band offsets moderate mass better vertical scaling good intervalley separation bandgap too low? quantization low mass high h well energy poor vertical scaling good intervalley separation bandgap too low very low mass high well energy poor vertical scaling

Non-Parabolic Bands Bands are ~ parabolic only for k near zero. At high energies, bands become nearly hyperbolic. Asyptotic group velocity. Similar in most semiconductors. Parabolic - band FET expressions are generally ypessimistic.

Non-Parabolic Bands T. Ishibashi, IEEE Transactions on Electron Devices, 48,11, Nov. 2001,

MOSFET Design Assuming In Ga As Channel 0.5 0.5

Device Design / Fabrication Goals source contact metal gate sidewall gate dielectric drain contact N+ source N+ drain quantum well / channel barrier substrate Device gate overdrive 700 500 300 mv drive current 5 3 1.4 ma/μm N s 6*10 610 12 4*10 410 12 2.5*10 12 1/cm 2 Dielectric: EOT 0.6 nm target, ~1.5 nm short term Channel : 5 nm thick μ > 1000 cm 2 /V-s @ 5 nm, 6*10 12 /cm 2 S/D access resistance: 20 Ω-μm resistivity 0.5 Ω-μm 2 contacts, ~2*10 13 /cm 2, ~4*10 19 /cm 3, 5 nm depth

Target Device Parameters source contact metal gate sidewall gate dielectric drain contact N+ source N+ drain quantum well / channel barrier substrate well : 12 2 n ~ 5 10 / cm, 5 nm thick n s 19 3 13 5 10 / cm, 5 nm thick ns = 2. 5 10 / cm 2 2 ( 0. 25 Ω μm ) /( 25 nm wide contact) = 10 Ω μm

Device Structure & Process Flow

Device Fabrication: Goals & Challenges III-V HEMTs are built like this Source Gate Drain K Shinohara and most...and most III-V MOSFETs are built like this

Device Fabrication: Goals & Challenges Yet, we are developing, at great effort, a structure like this N+ source regrowth ε r TiW ε r InGaAs well InP well barrier N+ drain regrowth Why? Source Gate Drain K Shinohara

Why not just build HEMTs? Gate Barrier is Low! Gate barrier is low: ~0.6 ev Source Gate Drain K Shinohara Tunneling through barrier sets minimum thickness Emission over barrier limits 2D carrier density E c E F E c E F E well-γ E well-γ At N s = 10 13 / cm 2, ( E f E ) ~ 0.6 ev c

Why not just build HEMTs? Gate barrier also lies under source / drain contacts Source Gate Drain N+ layer widegap barrier layer K Shinohara low leakage: need high barrier under gate low resistance: need low barrier under contacts E c E c E F E F E well-γ N+ cap layer E well-γ

The Structure We Need -- is Much Like a Si MOSFET source contact metal gate sidewall gate dielectric drain contact N+ source N+ drain quantum well / channel barrier no gate barrier under S/D contacts substrate high-k gate barrier Overlap between gate and N+ source/drain How do we make this device?

S/D Regrowth Process Flow

Regrown S/D FETs: Versions Wistey et al 2008 MBE conference regrowth under sidewalls planar regrowth need thin sidewalls (now ~20-30 nm)..or doping under sidewalls

S/D Regrowth by Migration-Enhanced Epitaxy Wistey et al 2008 MBE conference MBE growth is line-of-sight gaps in regrowth near gate edges MEE provides surface migration during regrowth eliminates gaps SEM Cross Section SEM Side View (Oblique) Top of gate SiO2 dummy gate SiO2 dummy gate Side of gate InGaAs Regrowth Original Interface InGaAs Regrowth No gaps Smooth surfaces. SEM: Greg Burek SEM: Uttam Singisetti High Si activation (4x10 19 cm -3 ). Quasi-selective: no growth on sidewalls 6 0

Self-Aligned Planar III-V MOSFETs by Regrowth Mo contact metal N+ InGaAs regrowth, Mo contact metal Wistey Singisetti Burek Lee gate

Self-Aligned Planar III-V MOSFETs by Regrowth Wistey Singisetti Burek Lee

Regrown S/D FETs: Images

III-V MOS

InGaAs / InP MOSFETs: Why and Why Not low m*/m 0 high v carrier more current low m*/m 0 low density of states less current ballistic / degenerate calculation Error bars on Si data points correct for (E f - E c )>> kt approximation n = # band minima c dos,o = density of states capacitance for m*=m o & n=1 K 0.25 0.2 0.15 0.1 0.05 0.7 nm, n=6 0.4 nm, n=6 0.8 nm, n=1 1.0 nm, n=1 3/ 2 ma Vgs Vth J = K 84, μm 1V * n ( m m ) 1/ 2 o where K = * c dos, o m 1 + n cox mo 3/ 2 0 EOT includes wavefunction depth (0.5 nm for 3.5 nm InGaAs well) 0.01 0.1 1 m*/m o Low m* impairs vertical (hence L g ) scaling ; InGaAs no good below 22-nm. InGaAs allows very low access resistance Si wins if high-k scales below 0.6 nm EOT; otherwise, III-V has a chance

InGaAs/InP Channel MOSFETs for VLSI Low-m* materials are beneficial only if EOT cannot scale below ~1/2 nm Devices cannot scale much below 22 nm Lg limits IC density Little CV/I benefit in gate lengths below 22 nm Lg Need device structure with very low access resistance radical re-work of device structure & process flow Gate dielectrics, III-V growth on Si: also under intensive development