Modeling of Devices for Power Amplifier Applications

Modeling of Devices for Power Amplifier Applications David E. Root Masaya Iwamoto John Wood Contributions from Jonathan Scott Alex Cognata Agilent Worldwide Process and Technology Centers Santa Rosa, CA USA Agilent Technologies 2004

Presentation Outline Introduction Nonlinear Charge Modeling Electro-Thermal Modeling Advanced Measurements Mathematical CAD Techniques Summary & Conclusions Page 2

Power Amplifier Requirements and Modeling Implications Linearity: Harmonic and Intermodulation Distortion; ACPR; AM-AM; AM-PM Efficiency: PAE; Fundamental Output Power; Self-biasing Modeling Challenges from device physics (III-V transport), complex signals, multiple time-scale dynamics, and the wide variety of device designs in many material systems Accuracy over bias, frequency, and temperature; power Perspective for this talk: Modeling of III-V HBTs & HEMTs for circuit simulation Primarily from CAD perspective Page 3

Presentation Outline Introduction Nonlinear Charge Modeling Electro-Thermal Modeling Advanced Measurements Mathematical CAD Techniques Summary & Conclusions Page 4

Nonlinear Charge Modeling: MOTIVATION FET models with same I-V eq.s but different charge eq.s [2] IM3 [dbm] Model A = C j 0 1 V / φ Model C = "Agilent (HP) FET Model" (1991) = Model B = Modified Statz Model (1987) Contour C dv Charge model is critical for distortion simulation Page 5

Charge Modeling Problem for Circuit Simulation Specify two (e.g. Gate and Drain) charge functions, Q i,,i=g,d such that: dqi( VGS( t), VDS( t)) Ii() t = Ii( VGS(), t VDS()) t + dt Can calculate charge function from physics (in theory) [6]. Inverse modeling alternative (not just table-based): Relate model functions to small-signal data and equivalent ckt. data Im( Yint ) ω QG QG Derivatives of VGS V model function DS = = QD QD VGS V DS CGS + CGD CGD C C C + C m GD DS GD C GS Cm Page 6 S G C DS C GD D

Measured Bias-Dependent FET Gate Capacitances 400fF C GS Vgs=+0.5 160fF C GD 0.0 0.0 V DS 5.0 0.25um PHEMT Vgs=-1.5 20fF The measured data cannot be modeled by two, two-terminal nonlinear capacitors A single Q G function must model both C GS and C GD 0.0 V DS 5.0 C GS S G C DS Cm Vgs=-1.5 Vgs=+0.5 C GD D Page 7

(1) A model Q G function consistent w. SS data exists if and only if ( C + C ) C = V V meas meas meas GS GD GD DS GS (D. Root 2001 ISCAS Short Course) This is a constraint on pairs of independently measured Y parameters (or S-parameters) pairs of measured device capacitances (attached to gate node) This is the modeling principle of Terminal Charge Conservation (2) The prescription for model charge calculation is, then: Q = [( C + C ) dv C dv ] model meas meas meas G GS DS contour GS GD GD Similar conditions to (1) and (2) can be written at the drain Measured FET data are very consistent with (1) at gate Somewhat less consistent at drain Page 8

Why not use independently measured capacitances? I () t = I ( V (), t V ()) t + G G GS DS meas dvgs () t meas dvgd () t C ( V (), ()) ( (), ()) GS GS t VDS t + C V GD GS t VDS t dt dt This model will fit bias-dependent capacitances perfectly BUT: It can be shown the capacitance terms yield a spectrum with a DC component! I G Root RAWCON98 Terminal Charge Conserving capacitances do not produce a DC component I G ω 2ω freq ω 2ω freq Enforcing Terminal Charge Conservation is a modeling trade-off. It is not physical charge cons. (KCL) Page 9

Example: EPHEMT Large-Signal Model [24] Analytic I-V, table-based charge and gate current, + self-heating PAE (thick) and Delivered Power (thin) Contours Measured Maximum PAE Measured Maximum Pout Maximum Power-Added Efficiency, % untitled4..s(3,3) untitled4..s(1,1) Pdel_contours_p PAE_contours_p Simulated Pout Contours m2 m1 77.26 Simulated PAE Contours Maximum Power Delivered, dbm 26.27 indep(pae_contours_p) (0.000 to 40.000) indep(pdel_contours_p) (0.000 to 50.000) freq (1.000GHz to 1.000GHz) Simulated EPHEMT Load-Pull contours for Pmax & PAE. m1 indep(m1)=2 PAE_contours_p=0.318 / 89.811 level=77.159945, number=1 impedance = Z0 * (0.818 + j0.579) Max PAE: 77.26% meas. 77.16% simulated. m2 indep(m2)=3 Pdel_contours_p=0.603 / 156.285 level=26.261844, number=1 impedance = Z0 * (0.258 + j0.197) Max Power: 26.26 dbm measured and simulated Page 10

Terminal Charge Conservation and III-V HBT Modeling [4] Intrinsic common-emitter HBT Y-parameters are of the form: QBB QBB QBB QBB QBB QBB + gm + gce Im( Yint ) VBE V CE VBC IC VBC I C C B + τb gm C B + τb g CE = = = ω QCC QCC QCC QCC QCC QCC C C τc gm CC τc gce gm g + + + + CE VBE V CE VBC IC VBC I C Where: Q Im( Y + Y ) CC 21 22 CC 21 C = = CC = = τ C gm IC ω ( gm + gce) VBC ω τ Q Im( Y ) Necessary and Sufficient Conditions For model Q CC consistent with ss data: τ C V BC = C I C C Q CC can then be constructed directly from data by: Q = [ C dv +τ di ] CC C BC C C contour Page 11

III-V HBT Base-Collector Delay / Capacitance model [4] Measured base-collector transit time Shape of delay (before Kirk effect) related to velocity-field curves τ C V BC = C I C C - Capacitance cancellation effect in III-V HBTs follows Q = C dv +τ di CC C BC C C ( Q τ ( V, I) I) Device data, model equations, and physics consistent dif Page 12

GaAs HBT power cell ( 2x20 quad-emitter device): (4x2x20) f T & C BC vs. I C 40 Measurements Simulations [25] 5E-13 V CE =0.5 to 3V w/0.5v per step 35 30 4E-13 ft (GHz) 25 20 15 Cbc (Farads) 3E-13 2E-13 10 1E-13 5 0 0 10 20 30 40 50 60 Ic (ma) Accurate charge model necessary to fit both f T and C BC, simultaneously over wide range of bias. 0 0 10 20 30 40 50 60 Ic (ma) Si-based models do not fit this behavior well, generally Page 13

GaAs HBT power cell ( 2x20 quad-emitter device): S-parameters: 0.5-25.05 GHz S 21 /25 S11 & S22 S 11 S 22 S21 & S12 S 12 10 freq (500.0MHz to 25.05GHz) Measurements Simulations freq (500.0MHz to 25.05GHz) V CE =1,2,3V J C =0.05mA/µm 2 Page 14

Nonlinear Charge Modeling: Bias-Dependent IM3 of III-V HBTs [4] Measured f T Simulated f T V CE f T related to τ τ modeled by Q V CE Power (dbm) 0-10 -20-30 -40-50 -60-70 P out IM3-80 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 Measured Pout, IM3 Simulated Pout, IM3 P out IM3 V CE =2 to 4.5V 0.000 0.0010.002 0.003 0.0040.0050.006 0.007 0.0080.009 Ic (A) Ic (A) Charge model is critical for distortion simulation Page 15

6x(2x14)µm 2 InGaP/GaAs HBT cell: AM-AM and AM-PM distortions 16 14 96 95 Symbols: Measurement Solid lines: Simulation Gain (dbm) 12 10 8 6 4 94 93 92 91 90 Phase (degrees) V CE =3.5V J C =0.12mA/µm 2 Frequency=5GHz R L =50Ω 2 89 0 88-35 -30-25 -20-15 -10-5 0 5 10 Input Power (dbm) Good collector charge model critical for accurate AM-AM and AM-PM Page 16

Presentation Outline Introduction Nonlinear Charge Modeling Electro-Thermal Modeling Advanced Measurements Mathematical CAD Techniques Summary & Conclusions Page 17

Dynamic electro-thermal (self-heating) model Algebraic perspective T(t) is a dynamical variable I () t = I ( V () t, V ( t), Tt ()) c c be ce Q () t = Q ( V (), t I ( V, V, T() t ), T()) t tc tc bc c be ce Charge due to transit delay is a function of temperature Temperature evolution equation based on dissipated power dt τ + T = RTH ICVCE simplified dt T(t) calculated by the simulator self-consistently Page 18

Dynamic electro-thermal (self-heating) model [25] Currents, Voltages, and T(t) calculated by the simulator self-consistently using coupled electrical and thermal equivalent circuits Tdev = Tamb + deltat T dev =device junction temperature T amb =device ambient (backside) temperature 2-pole thermal circuit used. Collapsible to single node. Page 19

Self-heating model (static case) 0.6 1.4 0.5 JC (ma/µm 2 ) 0.4 0.3 0.2 0.1 VBE (Volts) 1.3 1.2 0.0-0.1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 V CE (Volts) 1.1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 V CE (Volts) Measurement Self-heating model [25] Isothermal model Page 20

Thermal Coupling: Current Collapse Instability Simulated with III-V HBT Model [25] Icct V_DC SRC1 Vdc=VCE I_Probe Icct I_DC SRC2 Idc=IBB HBT1 th delt1 R Rth_shnt1 I_Probe Icc1 AgilentHBT_NPN_Th HBT1 SelfTmod=1 R Rthx Thermal node allows interactions between devices. Temp limited for convergence (but see [11]) Realistic thermal constitutive relations required [10] delt2 thermal network HBT2 th R Rth_shnt2 I_Probe Icc2 AgilentHBT_NPN_Th HBT2 SelfTmod=1 Icct, Icc1, Icc2 (ma) deltat (Kelvin) 400 300 200 100 0 500 400 300 200 100 0 HBT1 HBT2 0 1 2 3 4 5 6 7 8 9 10 Vce (Volts) HBT1 HBT2 0 1 2 3 4 5 6 7 8 9 10 Vce (Volts) Page 21

Dynamic electro-thermal III-V HBT Model Low Freq. S-parameters and Pulse Response Measured/Simulated S21 (db) 28 27 26 25 24 Comparison of different thermal equivalent circuits in Linear (s-parameter) and Transient (time-domain) cases Extrapolation of measured Mag(S 21 ) vs. Frequency 1-pole Measured 2-poles I C (ma) 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 Pulsed I C vs. time 2-poles Measured No thermal 1-pole 23 1E3 No thermal 0.0 1E4 1E5 1E6 1E7 1E8 Frequency (Hz) 1E9 0.0 0.2 0.4 0.6 0.8 1.0 1.2 time (msec) Two poles are more accurate than one [8]. Compromise between speed and accuracy (SPICE). Distributed models can be used for HB analysis [7]. Page 22

6x(2x14)µm 2 InGaP/GaAs HBT cell: Electro-thermal Model Simulates PAE & I DC Accurately 50.0 60.0 40.0 50.0 V CE =3.5V PAE (%) 30.0 20.0 40.0 30.0 IDC (ma) J C =0.12mA/µm 2 Frequency=5GHz R L =50Ω 10.0 20.0 Simulation: 1-tone HB 0.0-15.0-10.0-5.0 0.0 5.0 10.0 15.0 20.0 Output Power (dbm) Symbols: Measurement Solid lines: Simulation 10.0 Page 23

6x(2x14)µm 2 InGaP/GaAs HBT cell: ACPR & PAE vs. Output Power -30.0 100.0 V CE =3.5V -40.0 80.0 J C =0.12mA/µm 2 ACPR (dbc) -50.0-60.0 60.0 40.0 PAE (%) Frequency=1.9GHz R L =50Ω -70.0 20.0 Modulation: IS-95 Rev. Link Simulation: Envelope -80.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 Output Channel Power (dbm) Symbols: Measurement Solid lines: Simulation 0.0 Page 24

Presentation Outline Introduction Nonlinear Charge Modeling Electro-Thermal Modeling Advanced Measurements Mathematical CAD Techniques Summary & Conclusions Page 25

Advanced Measurements Essential for Model Development Model Validation Device characterization for technology development Can not always infer dynamic large-signal behavior from only static (DC) or linear (S-parameter) data Preferred for characterizing limiting behavior (e.g. breakdown) Page 26

GaN Devices 1 mm 10 fingers GaN on Si f T ~ 30GHz Pulse width 2us Pulsed measurements provide much more data than can be measured under static (DC) conditions Page 27

Pulsed data on III-V HBT Current dependence of breakdown [15] 5x2x14 CE GaAs HBT f T ~ 60GHz Pulse width 1us Can observe and extract breakdown parameters Page 28

Pulsed Bias Measurements Same 0.25um PHEMT device Soak time ~20 ms Pulse width ~200 ns Iso-dynamic Can use to separate thermal and trapping effects Page 29

Vector Nonlinear Network Analyzer (VNNA) Measurements: Breakdown Current Biased well below pinch-off Time (ns) Measure device under conditions of actual use. Examine reliability under these conditions. Page 30

Vector Nonlinear Network Analyzer (VNNA) Measurements: Forward Gate Current Biased less negatively than before Time (ns) Measure device under conditions of actual use. Forward gate current in phemts is complicated. Page 31

Vector Nonlinear Network Analyzer (VNNA) Measurements: Phase of device intermodulation versus bias measured Simulated AgilentHBT Page 32

Presentation Outline Introduction Nonlinear Charge Modeling Electro-Thermal Modeling Advanced Measurements Mathematical CAD Techniques Summary & Conclusions Page 33

Table-Based Model Limitation Naive simulator interpolation -> poor distortion -0.6-1.0 Vgs P=-10dBm 0.2V Vds 2-tones @ 100MHz (+1MHz) Si NJFET Table Model (a) Vg=-1V Power=-10dBm IP3 (dbm) -1.4-0.6-1.0-1.4 Vgs P=-20dBm Voltage Swing 0.06VVds (b) Vg=-1V Power=-20dBm IP3 (dbm) Null in third derivative of spline w.r.t. Vgs (2 nd axis) with symmetrical data points Interpolation model is better when signal size ~ data spacing Vd Vd Page 34

Artificial Neural Networks A NN is a parallel processor made up of simple, interconnected processing units, called neurons, with weighted connections. sigmoid weights biases x 1... F( x I K,..., xk = vis wkixk + ai + b i= 1 k = 1 1 ) x k Universal Approximation Theorem: Fit any nonlinear function of any # of variables Infinitely differentiable: good for distortion. Easy to train (fit) using standard third-party tools (MATLAB) Page 35

Artificial Neural Networks: Excellent, smooth fit. Better than simple table-based models + Measured data Blue Lines ANN fit Page 36

Adjoint Neural Network [21] Constructing FET gate charge, Q g, given ( meas meas Im Y ) 11, ImY12 Experimental validation of terminal charge conservation at the gate for GaAs phemt Q V g gs ImY 11 C ( V, V ) gg gs ds Q V g ds ImY ω ω 12 Cgd ( Vgs, Vds) V ds X measured modeled V ds Page 37

Summary and Conclusions Charge Modeling shown to be critical for simulating PA FoMs Terminal Charge Conservation modeling principle discussed in detail. Two-dimensional FET capacitances Voltage & Current dependent transit time and capacitance in III-V HBTs Electro-Thermal Effects shown to be important for PA simulation Static and dynamic self-heating necessary to fit device characteristics Technical issues with thermal equivalent circuit, thermal coupling, and thermal constitutive relations summarized Advanced Measurements shown to reveal rich device behavior Advanced CAD shown promising for better PA simulation models Page 38