EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
Announcements Lab 1 this week, report due next week Bring your breadboards to lab! HW 1 due this Friday at 4 PM in box, Kemper 2131 Instructor office hours this week: Wednesday 11 AM -12 PM TA Office Hours: Thursdays 3:30-5 PM, Kemper 2157/2161 Amirtharajah/Parkhurst, EEC 118 Spring 2010 2
Outline Finish Lecture 1 Slides Switch Example MOSFET Structure MOSFET Regimes of Operation Scaling Parasitic Capacitances Amirtharajah/Parkhurst, EEC 118 Spring 2010 3
MOS Transistor Types Rabaey Ch. 3 (Kang & Leblebici Ch. 3) Two transistor types (analogous to bipolar NPN, PNP) NMOS: p-type substrate, n + source/drain, electrons are charge carriers PMOS: n-type substrate, p + source/drain, holes are charge carriers gate gate N + N + source drain P + P + source drain P-substrate N-substrate bulk (substrate) bulk (substrate) NMOS PMOS Amirtharajah/Parkhurst, EEC 118 Spring 2010 4
MOS Transistor Symbols NMOS D PMOS D G B G B S D S D G B G B S D S D G B G B S Amirtharajah/Parkhurst, EEC 118 Spring 2010 5 S
Note on MOS Transistor Symbols All symbols appear in literature Symbols with arrows are conventional in analog papers PMOS with a bubble on the gate is conventional in digital circuits papers Sometimes bulk terminal is ignored implicitly connected to supply: NMOS PMOS Unlike physical bipolar devices, source and drain are usually symmetric Amirtharajah/Parkhurst, EEC 118 Spring 2010 6
MOS Transistor Structure Important transistor physical characteristics Channel length L = L D 2x d (K&L L = Lgate 2L D ) Channel width W Thickness of oxide t ox W t ox L x d Amirtharajah/Parkhurst, EEC 118 Spring 2010 7
NMOS Transistor I- Characteristics I I- curve vaguely resembles bipolar transistor curves Quantitatively very different Turn-on voltage called Threshold oltage T Amirtharajah/Parkhurst, EEC 118 Spring 2010 8
NMOS Transistor I- Characteristics II Drain current varies quadratically with gate-source voltage GS (in Saturation) Amirtharajah/Parkhurst, EEC 118 Spring 2010 9
MOS Transistor Operation: Cutoff Simple case: D = S = B = 0 Operates as MOS capacitor (Cg = gate to channel) Transistor in cutoff region When GS < T0, depletion region forms No carriers in channel to connect S and D (Cutoff) s = 0 source g < T0 drain d = 0 depletion region B = 0 P-substrate Amirtharajah/Parkhurst, EEC 118 Spring 2010 10
MOS Transistor Operation: Inversion When GS > T0, inversion layer forms Source and drain connected by conducting n- type layer (for NMOS) Conducting p-type layer in PMOS s = 0 source g > T0 d = 0 drain P-substrate depletion region inversion layer B = 0 Amirtharajah/Parkhurst, EEC 118 Spring 2010 11
Threshold oltage Components Four physical components of the threshold voltage 1. Work function difference between gate and channel (depends on metal or polysilicon gate): Φ GC 2. Gate voltage to invert surface potential: -2Φ F 3. Gate voltage to offset depletion region charge: Q B /C ox 4. Gate voltage to offset fixed charges in the gate oxide and oxide-channel interface: Q ox /C ox C ox ε t ox = : gate oxide capacitance per unit area ox Amirtharajah/Parkhurst, EEC 118 Spring 2010 12
Threshold oltage Summary If SB = 0 (no substrate bias): T Q B0 = ΦGC F Cox 0 2φ Q C ox ox (K&L 3.20) If SB 0 (non-zero substrate bias) T = ( ) 2φ + φ T 0 + F SB γ 2 F (3.19) Body effect (substrate-bias) coefficient: γ = 2qN ε C ox A Si (K&L 3.24) Threshold voltage increases as SB increases! Amirtharajah/Parkhurst, EEC 118 Spring 2010 13
Threshold oltage (NMOS vs. PMOS) NMOS PMOS Substrate Fermi potential Depletion charge density Substrate bias coefficient φ F < 0 φ F > 0 Q B < 0 Q B > 0 γ > 0 γ < 0 Substrate bias voltage SB > 0 SB < 0 Amirtharajah/Parkhurst, EEC 118 Spring 2010 14
Body Effect Body effect: Source-bulk voltage SB affects threshold voltage of transistor Body normally connected to ground for NMOS, dd (cc) for PMOS Raising source voltage increases T of transistor Implications on circuit design: series stacks of devices A B x If x > 0, SB (A) > 0, T (A) > TO T0 Amirtharajah/Parkhurst, EEC 118 Spring 2010 15
MOS Transistor Regions of Operation Three main regions of operation Cutoff: GS < T No inversion layer formed, drain and source are isolated by depleted channel. I DS 0 Linear (Triode, Ohmic): GS > T, DS < GS - T Inversion layer connects drain and source. Current is almost linear with DS (like a resistor) Saturation: GS > T, DS GS - T Channel is pinched-off. Current saturates (becomes independent of DS, to first order). Amirtharajah/Parkhurst, EEC 118 Spring 2010 16
MOSFET Drain Current Overview Saturation: I D μc 2 W L ( ) 2 ( + λ ) ox = GS T 1 DS Linear (Triode, Ohmic): I = μc D Cutoff: I D 0 ox W L ( ) DS 2 GS T DS 2 Classical MOSFET model, will discuss deep submicron modifications as necessary (Rabaey, Eqs. 3.25, 3.29) Amirtharajah/Parkhurst, EEC 118 Spring 2010 17
Cutoff Region S G D source drain substrate depletion region For NMOS: GS < TN B For PMOS: GS > TP Depletion region no inversion Current between drain and source is 0 Actually there is always some leakage (subthreshold) current Amirtharajah/Parkhurst, EEC 118 Spring 2010 18
Linear Region When GS > T, an inversion layer forms between drain and source Current I DS flows from drain to source (electrons travel from source to drain) Depth of channel depends on between gate and channel Drain end narrower due to larger drain voltage Drain end depth reduces as DS is increased Channel (inversion layer) s =0 source g > T0 B = 0 drain d < GS - T0 P-substrate depletion region (larger at drain end) Amirtharajah/Parkhurst, EEC 118 Spring 2010 19
Linear Region I/ Equation Derivation Gradual Channel Approximation: Assume dominant electric field in y-direction Current is constant along channel Integrate differential voltage drop d c = I D dr along y Amirtharajah/Parkhurst, EEC 118 Spring 2010 20
Linear Region I/ Equation alid for continuous channel from Source to Drain I D = μ C n ox W L [( ) ] 1 2 GS Device transconductance: Process transconductance: I D = k ' n W L T k k DS n = μ n ' n 2 C n ox = μ C ox DS W L [( ) ] 1 2 GS T DS 2 DS Amirtharajah/Parkhurst, EEC 118 Spring 2010 21
Saturation Region When DS = GS - T : No longer voltage drop of T from gate to substrate at drain Channel is pinched off If DS is further increased, no increase in current I DS As DS increased, pinch-off point moves closer to source Channel between that point and drain is depleted High electric field in depleted region accelerates electrons towards drain g > T0 s =0 d > - GS T0 depletion source drain region pinch-off point B = 0 Amirtharajah/Parkhurst, EEC 118 Spring 2010 22
Saturation I/ Equation As drain voltage increases, channel remains pinched off Channel voltage remains constant Current saturates (no increase with increasing DS ) To get saturation current, use linear equation with I D DS = GS - T ( ) 2 = μ C 1 2 n ox W L GS TN Amirtharajah/Parkhurst, EEC 118 Spring 2010 23
MOS I/ Characteristics I/ curve for ideal MOS device GS3 > GS2 > GS1 GS3 Drain current I DS Linear GS2 GS1 Saturation Drain voltage DS Amirtharajah/Parkhurst, EEC 118 Spring 2010 24
Channel Length Modulation In saturation, pinch-off point moves As DS is increased, pinch-off point moves closer to source Effective channel length becomes shorter Current increases due to shorter channel ' L I D = = L ΔL 1 2 W μ ncox GS TN + λ L ( ) 2 ( 1 ) λ = channel length modulation coefficient DS Amirtharajah/Parkhurst, EEC 118 Spring 2010 25
MOS I/ Curve Summary I/ curve for non-ideal NMOS device: DS = GS - T Drain current I DS Linear GS3 GS2 GS1 Saturation with channellength modulation without channellength modulation (λ=0) Drain voltage DS Amirtharajah/Parkhurst, EEC 118 Spring 2010 26
Cutoff MOS I/ Equations Summary GS GS < > TN TP I D = 0 Linear GS GS TN TP,, Saturation GS GS DS DS < > GS GS TN TP I D = μc ox W L [( ) ] 1 2 TN, DS GS TN 1 W 2 ID = 2 Cox GS T TP, DS GS TP L GS T DS 2 DS ( ) ( 1 ) μ +λ DS Note: if SB 0, need to recalculate T from T0 Amirtharajah/Parkhurst, EEC 118 Spring 2010 27
A Fourth Region: Subthreshold Subthreshold: GS nkt q I = D I Se 1 e DS kt q Sometimes called weak inversion region When GS near T, drain current has an exponential dependence on gate to source voltage Similar to a bipolar device Not typically used in digital circuits Sometimes used in very low power digital applications Often used in low power analog circuits, e.g. quartz watches Amirtharajah/Parkhurst, EEC 118 Spring 2010 28
MOSFET Scaling Effects Rabaey Section 3.5 (Kang & Leblebici Section 3.5) Scaling provides enormous advantages Scale linear dimension (channel length) by factor S > 1 Better area density, yield, performance Two types of scaling Constant field scaling (full scaling) A = A/S 2 ; L = L/S; W = W/S; I D = I D /S; P = P/S 2 ; dd = dd /S Power Density P /A = stays the same Change these two Constant voltage scaling A = A/S 2 ; L = L/S; W = W/S; I D = I D *S; P = P*S; dd = dd Power Density P /A = S 3 *P (Reliability issue) This changed as well Amirtharajah/Parkhurst, EEC 118 Spring 2010 29
Short Channel Effects As geometries are scaled down T (effective) goes lower Effective channel length decreases Sub-threshold Ids occurs Current goes from drain to source while gs < t Tox is scaled which can cause reliability problems Can t handle large g without hot electron effects Changes the t when carriers imbed themselves in the oxide Interconnects scale Electromigration and ESD become issues Amirtharajah/Parkhurst, EEC 118 Spring 2010 30
MOSFET Capacitances Rabaey Section 3.3 (Kang & Leblebici Section 3.6) Oxide Capacitance Gate to Source overlap Gate to Drain overlap Gate to Channel Junction Capacitance Source to Bulk junction Drain to Bulk junction Amirtharajah/Parkhurst, EEC 118 Spring 2010 31
Oxide Capacitances: Overlap source L drawn drain x d Overlap capacitances Gate electrode overlaps source and drain regions x d is overlap length on each side of channel L eff = L drawn 2x d (effective channel length) Overlap capacitance: C = C = C Wx Assume x d equal on both sides GSO GDO ox d Amirtharajah/Parkhurst, EEC 118 Spring 2010 32
Total Oxide Capacitance Total capacitance consists of 2 components Overlap capacitance Channel capacitance Cutoff: C gs source C gb C gd drain No channel connecting to source or drain C GS = C GD = C ox Wx d C GB = C ox WL eff Total Gate Capacitance = C G = C ox WL Amirtharajah/Parkhurst, EEC 118 Spring 2010 33
Oxide Capacitances: Channel Linear mode Channel spans from source to drain Channel Capacitance split equally between S and D C GS 1 2 C 1 C 2 WL = CoxWLeff GD ox eff Total Gate capacitance C G = C ox WL Saturation regime Channel is pinched off: Channel Capacitance -- C = WL GD D C ox GS ox Amirtharajah/Parkhurst, EEC 118 Spring 2010 34 = 2 C = C WL + 3 Total Gate capacitance: C G = 2/3 C ox WL eff + 2x d WC OX eff C OX Wx C GB d = 0 C GB = 0
Oxide Capacitances: Channel C g,total (no overlap, x d = 0) Amirtharajah/Parkhurst, EEC 118 Spring 2010 35
Junction Capacitance Reverse-biased P-N junctions! Capacitance depends on reverse-bias voltage. Amirtharajah/Parkhurst, EEC 118 Spring 2010 36
Amirtharajah/Parkhurst, EEC 118 Spring 2010 37 Junction Capacitance a d a d j N N N N q A C + = 0 2 2 ε For a P-N junction: a d a d Si j N N N N q C + = 0 0 2 ε If =0, cap/area = m j j AC C = 0 0 1 General form: m = grading coefficient (0.5 for abrupt junctions) (0.3 for graded junctions)
Junction Capacitance Junction with substrate Bottom area = W * L S (length of drain/source) Total cap = C j Junction with sidewalls Channel-stop implant Perimeter = 2L S + W Area = P * X j Total cap = C jsw Total junction cap C = C j + C jsw Amirtharajah/Parkhurst, EEC 118 Spring 2010 38
Junction Capacitance oltage Equivalence Factor Creates an average capacitance value for a voltage transition, defined as ΔQ/Δ AC 1 m 1 m j0 0 2 1 C eq = 1 1 = 2 1 0 0 AK ( )( ) eq j0 1 m C K eq 2 = (abrupt junction only) 0 ( ) ( ) 0 2 0 1 2 1 C = AK C + db eq PX K C j0 j eqsw jsw0 Amirtharajah/Parkhurst, EEC 118 Spring 2010 39
Example: Junction Cap Consider the following NMOS device Substrate doping: N A = 10 15 cm -3 Source/drain doping: N D = 2 x 10 20 cm -3 Channel-stop doping: 10X substrate doping Drain length L D = 1um Transistor W = 10um Junction depth Xj = 0.5um, abrupt junction Find capacitance of drain-bulk junction when drain voltage = 3 Amirtharajah/Parkhurst, EEC 118 Spring 2010 40
Inverter Characteristics Next Topic: Inverters Transfer functions, noise margins, resistive and nonlinear loads CMOS Inverters Amirtharajah/Parkhurst, EEC 118 Spring 2010 41