MC74HC38A -of-8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The MC74HC38A is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC38A decodes a three bit Address to one of eight active low outputs. This device features three Chip Select inputs, two active low and one active high to facilitate the demultiplexing, cascading, and chip selecting functio. The demultiplexing function is accomplished by using the Address inputs to select the desired device output; one of the Chip Selects is used as a data input while the other Chip Selects are held in their active states. 6 PDIP 6 N SUFFIX CASE 648 6 MARKING DIAGRAMS MC74HC38AN AWLYYWWG Features Output Drive Capability: 0 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating oltage Range: to Low Input Current:.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 00 FETs or 29 Equivalent Gates Pb Free Packages are Available* 6 6 SOIC 6 D SUFFIX CASE 75B TSSOP 6 DT SUFFIX CASE 948F 6 HC38AG AWLYWW 6 HC 38A ALYW 6 SOEIAJ 6 F SUFFIX CASE 966 6 74HC38A ALYWG A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb Free Package = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet. *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2009 December, 2009 Rev. 0 Publication Order Number: MC74HC38A/D
MC74HC38A A0 A A2 2 3 6 5 4 CC Y0 Y CS2 4 3 Y2 CS3 5 2 Y3 CS Y7 6 7 0 Y4 Y5 GND 8 9 Y6 Figure. Pin Assignment ADDRESS INPUTS A0 A A2 6 CS CHIP- 4 SELECT CS2 INPUTS 5 CS3 2 3 5 4 3 2 0 Y0 Y Y2 Y3 Y4 Y5 9 7 Y6 Y7 PIN 6 = CC PIN 8 = GND Figure 2. Logic Diagram ACTIE-LOW OUTPUTS FUNCTION TABLE Inputs Outputs CSCS2 CS3 A2 A A0 Y0 Y Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X H H H H H H H H X H X X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L H = high level (steady state); L = low level (steady state); X = don t care ORDERING INFORMATION MC74HC38ANG Device Package Shipping PDIP 6 (Pb Free) 500 Units / Rail MC74HC38ADG SOIC 6 (Pb Free) 48 Units / Rail MC74HC38ADR2 SOIC 6 2500 Tape & Reel MC74HC38ADR2G SOIC 6 (Pb Free) 2500 Tape & Reel MC74HC38ADTR2 TSSOP 6* 2500 Tape & Reel MC74HC38ADTR2G TSSOP 6* 2500 Tape & Reel MC74HC38AFG SOEIAJ 6 (Pb Free) 50 Units / Rail For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. *This package is inherently Pb Free. 2
MC74HC38A MAXIMUM RATINGS Symbol Parameter alue Unit CC DC Supply oltage (Referenced to GND) 0.5 to + 7.0 in DC Input oltage (Referenced to GND) 0.5 to CC + 0.5 out DC Output oltage (Referenced to GND) 0.5 to CC + 0.5 I in DC Input Current, per Pin ± 20 ma I out DC Output Current, per Pin ± 25 ma I CC DC Supply Current, CC and GND Pi ± 50 ma P D Power Dissipation in Still Air, Plastic DIP SOIC Package TSSOP Package 750 500 450 T stg Storage Temperature 65 to + 50 C T L Lead Temperature, mm from Case for 0 Seconds (Plastic DIP, SOIC or TSSOP Package) 260 mw C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be cotrained to the range GND ( in or out ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditio is not implied. Extended exposure to stresses above the Recommended Operating Conditio may affect device reliability. Derating Plastic DIP: 0 mw/ C from 65 to 25 C SOIC Package: 7 mw/ C from 65 to 25 C TSSOP Package: 6..W/ C from 65 to 25 C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to GND) in, out DC Input oltage, Output oltage (Referenced to GND) 0 CC T A Operating Temperature, All Package Types 55 + 25 C t r, t f Input Rise and Fall Time CC = (Figure 2) CC = CC = 0 0 0 000 500 400 3
MC74HC38A DC ELECTRICAL CHARACTERISTICS (oltages Referenced to GND) Symbol Parameter Test Conditio CC Guaranteed Limit 55 C to 25 C 85 C 25 C Unit IH Minimum High Level Input oltage out = 0. or CC 0. I out 20 A.5 2. 3.5 4.2.5 2. 3.5 4.2.5 2. 3.5 4.2 IL Maximum Low Level Input oltage out = 0. or CC 0. I out 20 A 0.5 0.9.35.8 0.5 0.9.35.8 0.5 0.9.35.8 OH Minimum High Level Output oltage in = IH or IL I out 20 A.9 4.4 5.9.9 4.4 5.9.9 4.4 5.9 in = IH or IL I out 2.4 ma I out 4.0 ma I out 5.2 ma 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 OL I in I CC Maximum Low Level Output oltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) in = IH or IL I out 20 A in = IH or IL I out 2.4 ma I out 4.0 ma I out 5.2 ma 0. 0. 0. 0.26 0.26 0.26 0. 0. 0. 0.33 0.33 0.33 0. 0. 0. 0.40 0.40 0.40 in = CC or GND ± 0. ±.0 ±.0 A in = CC or GND I out = 0 A 4 40 60 A AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Input t r = t f = ) Symbol t PLH, t PLH, t PLH, t TLH, t THL Parameter Maximum Propagation Delay, Input A to Output Y (Figures and 4) Maximum Propagation Delay, CS to Output Y (Figures 2 and 4) Maximum Propagation Delay, CS2 or CS3 to Output Y (Figures 3 and 4) Maximum Output Traition Time, Any Output (Figures 2 and 4) CC Guaranteed Limit 55 C to 25 C 85 C 25 C C in Maximum Input Capacitance 0 0 0 pf 35 90 27 23 0 85 22 9 20 90 24 20 75 30 5 3 70 25 34 29 40 00 28 24 50 20 30 26 95 40 9 6 205 65 4 35 65 25 33 28 80 50 36 3 0 55 22 9 Unit Typical @ 25 C, CC = 5.0 C PD Power Dissipation Capacitance (Per Package)* 55 * Used to determine the no load dynamic power coumption: P D = C PD 2 CC f + I CC CC. pf 4
MC74HC38A SWITCHING WAEFORMS ALID INPUT A 50% t PLH OUTPUT Y 50% ALID CC GND INPUT CS OUTPUT Y t r 90% 50% 0% 90% 50% 0% t f t PLH CC GND t THL t TLH Figure. Figure 2. TEST POINT INPUT CS2, CS3 OUTPUT Y 90% 50% 0% t f 90% 50% 0% t r t PLH CC GND DEICE UNDER TEST OUTPUT C L * t THL Figure 3. t TLH *Includes all probe and jig capacitance Figure 4. Test Circuit PIN DESCRIPTIONS ADDRESS INPUTS A0, A, A2 (Pi, 2, 3) Address inputs. These inputs, when the chip is selected, determine which of the eight outputs is active low. CONTROL INPUTS CS, CS2, CS3 (Pi 6, 4, 5) Chip select inputs. For CS at a high level and CS2, CS3 at a low level, the chip is selected and the outputs follow the Address inputs. For any other combination of CS, CS2, and CS3, the outputs are at a logic high. OUTPUTS Y0 Y7 (Pi 5, 4, 3, 2,, 0, 9, 7) Active low Decoded outputs. These outputs assume a low level when addressed and the chip is selected. These outputs remain high when not addressed or the chip is not selected. 5
MC74HC38A EXPANDED LOGIC DIAGRAM 5 Y0 4 Y A0 3 Y2 A 2 2 Y3 A2 3 Y4 CS3 CS2 5 4 0 9 Y5 Y6 7 Y7 CS 6 6
MC74HC38A PACKAGE DIMENSIONS PDIP 6 N SUFFIX CASE 648 08 ISSUE T 6 A 8 9 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, 982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. H G F D 6 PL S C K 0.25 (0.00) M T SEATING T PLANE A M J L M INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.740 0.770 8.80 9.55 B 0.250 0.270 6.35 6.85 C 0.45 0.75 3.69 4.44 D 0.05 0.02 0.39 0.53 F 0.040 0.70.02.77 G 0.00 BSC 2.54 BSC H 0.050 BSC.27 BSC J 0.008 0.05 0.2 0.38 K 0.0 0.30 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 0 0 0 S 0.020 0.040 0.5.0 SOIC 6 D SUFFIX CASE 75B 05 ISSUE J A 6 9 8 B P 8 PL 0.25 (0.00) M B S NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, 982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. T SEATING PLANE G K C D 6 PL 0.25 (0.00) M T B S A S M R X 45 J F MILLIMETERS INCHES DIM MIN MAX MIN MAX A 9.80 0.00 0.386 0.393 B 3.80 4.00 0.50 0.57 C.35.75 0.054 0.068 D 0.35 0.49 0.04 0.09 F 0.40.25 0.06 0.049 G.27 BSC 0.050 BSC J 0.9 0.25 0.008 0.009 K 0.0 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.00 0.09 7
MC74HC38A PACKAGE DIMENSIONS TSSOP 6 DT SUFFIX CASE 948F 0 ISSUE A 0.5 (0.006) T 0.5 (0.006) T 0.0 (0.004) T SEATING PLANE L U PIN IDENT. U D S S 2X L/2 C 6X K REF 0.0 (0.004) M T U S S 6 9 8 A G B U N H N J J F DETAIL E DETAIL E K K ÇÇÇ ÇÇÇ ÉÉ SECTION N N 0.25 (0.00) M W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, 982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.0 0.93 0.200 B 4.30 0 0.69 0.77 C.20 0.047 D 0.05 0.5 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.8 0.28 0.007 0.0 J 0.09 0.20 0.004 0.008 J 0.09 0.6 0.004 0.006 K 0.9 0.30 0.007 0.02 K 0.9 0.25 0.007 0.00 L 6.40 BSC 0.252 BSC M 0 8 0 8 8
MC74HC38A PACKAGE DIMENSIONS SOEIAJ 6 F SUFFIX CASE 966 0 ISSUE O e 6 9 Z b D A H E A 0.3 (0.005) M 0.0 (0.004) 8 E IEW P M L E Q L DETAIL P c NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, 982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.08). MILLIMETERS INCHES DIM MIN MAX MIN MAX A --- 5 --- 0.08 A 0.05 0.20 0.002 0.008 b 0.35 0.50 0.04 0.020 c 0.8 0.27 0.007 0.0 D 9.90 0.50 0.390 0.43 E 5.0 5.45 0.20 0.25 e.27 BSC 0.050 BSC H E 7.40 8.20 0.29 0.323 L 0.50 0.85 0.020 0.033 L E.0.50 0.043 0.059 M 0 0 0 0 Q 0.70 0.90 0.028 0.035 Z --- 0.78 --- 0.03 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: 303 675 275 or 800 344 3860 Toll Free USA/Canada Fax: 303 675 276 or 800 344 3867 Toll Free USA/Canada Email: orderlit@oemi.com N. American Technical Support: 800 282 9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 42 33 790 290 Japan Customer Focus Center Phone: 8 3 5773 3850 9 ON Semiconductor Website: www.oemi.com Order Literature: http://www.oemi.com/orderlit For additional information, please contact your local Sales Representative MC74HC38A/D