Dual RINC 9 Line Receiver www.fairchildsemi.com Features Two separate analog receiver channels Converts RINC 9 levels to serial data Built-in TTL compatible complete channel test inputs TTL and CMOS compatible outputs Low power dissipation Internal bandgap Short circuit protected MIL-STD-B screening available for ceramic packages vailable in 0-Lead ceramic DIP, 0-Terminal LCC, and 0-Lead SOIC Description The consists of two analog RINC 9 receivers which take differentially encoded RINC level data and convert it to serial TTL level data. The provides two complete analog RINC receivers and no external components are required. Input level shifting thin film resistors and bipolar technology allow RINC input voltage transients up to ±00V without damage to the. Each channel is identical, featuring symmetrical propagation delays for better high speed performance. Input common mode rejection is excellent and threshold voltage is stable, independent of supply voltage. Data outputs are TTL and CMOS compatible. Two TTL compatible test inputs used to test the RINC channels are available. They can be used to override the RINC input data and set the channel outputs to a known state. The Fairchild RM/RM line driver is the companion chip to the line receiver. Together they provide the analog functions needed for the RINC 9 interface. Digital data processing involving serial-to-parallel conversion and clock recovery can be accomplished using one of the RINC interface IC s available or by an equivalent gate array implementation. Block Diagram +V S +V L 9 In In B Cap Cap B 9 7 Bit Detection and Level Shifting Hysteresis Output Driver Out Out B Test Test B 0 Test Circuitry Bandgap Voltage Reference Threshold Generator Cap Cap B In In B 7 Bit Detection and Level Shifting Hysteresis Output Driver Out Out B -V S Gnd --0 Rev..0.0
PRODUCT SPECIFICTION Functional Description The contains two discrete RINC 9 receiver channels. Each channel contains three main sections: a resistor input network, a window comparator, and a logic output buffer stage. The first stage provides overvoltage protection and biases the signal using voltage dividers and current sources, providing excellent input common mode rejection. The test inputs are provided to set the outputs to a predetermined state for built-in channel test capability. If the test inputs are not used, they should be grounded. The window comparator section detects data from the resistor input network. Logic corresponds to RINC High state (OUT) and a Logic 0, to RINC Low state (OutB). n RINC Null state at the inputs forces both outputs to Logic 0. Threshold and hysteresis voltages are generated by a bandgap voltage reference to maintain stable switching characteristics over temperature and power supply variations. The output stage generates a TTL compatible logic output capable of driving m of load. Pin ssignments DIP and SOIC Top View LCC Top View -V S Test 0 9 TestB Cap CapB Test TestB -V S 0 Cap 9 CapB InB OutB In 7 In CapB InB Out InB OutB In Cap Out 7 7 In CapB InB Out GND Cap 7 GND Out +V L 9 NC OutB 9 0 NC +V L OutB +V S NC --0 NC 0 +V S --0 bsolute Maximum Ratings Parameter Min. Max. Units Supply Voltage (VCC to VEE) + V VLOGIC Voltage +7 V Logic Input Voltage -0. VLOGIC + 0. V Temperature Range Storage - +0 C Operating - + C Junction Temperature - +7 C Lead Soldering Temperature 0 sec., DIP, LCC +00 C 0 sec., SOIC +0 C
PRODUCT SPECIFICTION Thermal Characteristics (Still air, soldered on a PC board) Note:. MIL-STD-. Parameter LCC DIP SOIC Maximum Junction Temperature +7 C +7 C + C Thermal Resistance, qjc C/W 70 C/W C/W Thermal Resistance, qjc 0 C/W C/W 0 C/W DC Electrical Characteristics T = - C to + C, ±V VS ±V, VL = +V, unless otherwise noted. Symbol Parameter Conditlons Min. Typ. Max. Units ICC (+VS) Test inputs = 0V..0 m IEE (-VS) Test inputs = 0V 0..0 m IL (VL) Test inputs = V.0 7. m VTL V()-V(B) Low threshold.7.0. V VTH V()-V(B) High threshold.7.0. V VIN V()-V(B) Out and OutB = 0 -. 0. V VIC V() and V(B)-GND Maximum common mode ± V frequency = 0 khz RI Input resistance, Input to Input B 0 kw RH Input resistance, Input to Gnd 0 kw RG Input resistance, B to Gnd Filter caps disconnected 0 kw CI, Input capacitance, to B 0 pf CH, Input capacitance, to Gnd Filter caps disconnected 0 pf CG, Input capacitance, B to Gnd Filter caps disconnected 0 pf Test Inputs (Test, TestB) VIH Logic input voltage.7 V VIL Logic 0 input voltage 0 0. V IIH Logic input current VIH = V 0 00 m IIL Logic 0 input voltage VIL = 0.V 0 m Outputs VOH IOH = 00 m T = C.0. V IOH =. m Full temperature range..0 V VOL IOL = 00 m T = C 0.0 0. V IOL =.0 m Full temperature range 0 0. V Tr Rise Time CL = 0 pf, @ C 0 70 ns Tf Fall Time CL = 0 pf, @ C 0 70 ns TPLH Propagation delay CL = 0 pf, f = 00 khz 700 ns TPHL Output low to high Output high to low Filter caps = 9 pf T = C 700 ns Notes:. s stated in RINC9.. VT refers ot the threshold voltage at which the channels output switches from low to high or from high to low.. Common mode voltage present at both RINC inputs.. Guaranteed by design.. Test inputs should be connected to ground if not used.. Sample tested.
PRODUCT SPECIFICTION Typical Performance Characteristics TPHL, TPLH (ns) 900 00 700 00 00 00 00 00 00 0 - TP HL TP LH --0 Current (m) 0 0 0 - I L I EE I CC --0 Temperature ( C) Temperature ( C) Figure. Propagation Delay vs. Temperature CL = 0 pf, CFILTER = 9 pf Figure. Supply Current vs. Temperature VOL (Volts).00 0.7 0.0 + C + C 0. + C 0 0 0..0..0. --0.0 VOH (Volts). + C. + C..9 - C.7. 0 0..0..0. --07.0 I OL (m) I OH (m) Figure. Output Voltage Low vs. Output Current Figure. Output Voltage High vs. Output Current 70.0 Rise/Fall Time (ns) 0 0 0 0 0 0 0 - T F T R --0 Prop Delay (µs)..0..0 0. T = + C T PLH T PHL 0 0 0 00 0 00 0 00 0 00 --09 Temperature ( C) Filter Capacitance (pf) Figure. TR and TF vs. Temperature Figure. Propagation Delay vs. Filter Capacitance T = C
PRODUCT SPECIFICTION C Test Waveforms RINC In (Differential) +0V 0V Logic Out 90% 90% 0% 0% Logic Out ( Output) T PLH T R T F T PHL --0 -- Figure 7. Propagation Delay Figure. Rise/Fall Times Test Circuit +V -V +V In 0. mf 0.0 mf 0.0 mf In 9 0 pf Out Out B 0 pf Out V REF 9 7 7 0 pf 0 pf Out B 9pF 9pF 9pF 9pF Notes:. V IN = 00 khz square wave, -.V to +.V.. Set V REF = +. V to test V OUT and V OUT. Set V REF = -. V to test VOUT and VOUT.. 0 pf load capacitance includes probe and wiring capacitance. -- Figure 9. C Test Schematic Diagram
PRODUCT SPECIFICTION Truth Table RINC nputs V() - V(B) Test Inputs Outputs Output TEST TESTB OUT OUTB State Null 0 0 0 0 Null Low 0 0 0 Low High 0 0 0 High X 0 0 Low X 0 0 High X 0 0 Null pplications Discussion The standard connections for the are shown in Figure 0. Dual supplies from ± to ± VDC are recommended for the ±VS supplies. Decoupling of all supplies should be done near the IC to avoid propagation of noise spikes due to switching transients. The ground connection should be sturdy and isolated from large switching currents to provide as quiet a ground reference as possible. The noise filter capacitors are optional and are added to provide extra noise immunity by limiting bandwidth of the input signal before it reaches the window comparator stage. Two capacitors are required for each channel and they must all be the same value. The suggested capacitor value for a 00 khz operation is 9 pf. For lower data rates, larger values of capacitance may be used to yield better node performance. To get optimum performance, the following equation can be used to calculate capacitor value for a specific data rate:.9 0 C FILTER = --------------------------- F O Where CFILTER is the capacitor value in pf, and FO is the input frequency (0 khz FO 0 khz). The can be used with the Fairchild RM/ RM line driver to provide a complete analog RINC 9 interface. simple application which can be used for systems requiring a repeater-type circuit for long transmissions is given in Figure. More RM drivers may be added to test multiple RINC channels, as shown.
PRODUCT SPECIFICTION pplications +V +V 9 RINC 9 pf 9 In In B Cap B Data Out To Logic 7 Cap B RINC 9 pf 9 pf 7 In In B Cap B Data Out To Logic Cap B 9 pf Logic Test Inputs 0 Test Test B -V -- Figure 0. RINC Receiver Standard Connections RINC Test Input In Out In B B / Out Data () Data (B) OUT RM BOUT B Test Data () Data (B) RM OUT BOUT B Test To dditional s -- Figure. Repeater Circuit 7
PRODUCT SPECIFICTION pplications (continued) +V +V Inputs RINC 0 +V L In Out In B Out B H0 L0 VCC VSS Mode N V V Sync Clk +V R Data () I RM RM B S OUT OUT RINC Line Out RINC In Out In B Out B +V GND -V S S -V H L EF N0 Data (B) Gnd -V S PE C CB 7 pf 7 pf -V +V Reset RINC +V GND -V S S In Out In B Out B H L IRQ R/W Clock From Microprocessor RINC In Out In B Out B +V L To +V H L D0 - D 0 CS Microprocessor Data Bus From ddress Decoder -- Figure. Four- RINC Receiver Circuit -V 0 W / W +V 0K 0K 0K 0K 9 0K 0K +V 0 W / W +V 0 W / W -- Figure. Burn-In Circuit
PRODUCT SPECIFICTION Mechanical Dimensions 0-Lead SOIC Symbol Inches Millimeters Min. Max. Min. Max..09.0...00.0 0.0 0.0 B.0.00 0. 0. C.009.0 0. 0. D.9..0.00 E.9.99 7.0 7.0 e.00 BSC.7 BSC H.9.9 0.00 0. h.00.09 0. 0.7 L.0.00 0.0.7 N 0 0 a 0 0 ccc.00 0.0 Notes Notes:. Dimensioning and tolerancing per NSI Y.M-9.. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed.00 inch (0.mm).. "L" is the length of terminal for soldering to a substrate.. Terminal numbers are shown for reference only.. "C" dimension does not include solder finish thickness.. Symbol "N" is the maximum number of terminals. 0 E H 0 D h x C e B SETING PLNE C LED COPLNRITY a L ccc C 9
PRODUCT SPECIFICTION Mechanical Dimensions (continued) 0-Lead Ceramic DIP Symbol Inches Millimeters Min. Max. Min. Max..00.0 Notes b.0.0.. b.0.0.., c.00.0.0. D.00.9 E.0.0.9 7.7 e.00 BSC. BSC, 9 e.00 BSC 7. BSC 7 L..00..0 Q s a.0.00...00. 90 0 90 0 Notes:. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark.. The minimum limit for dimension "b" may be.0(.mm) for leads number, 0, and 0 only.. Dimension "Q" shall be measured from the seating plane to the base plane.. This dimension allows for off-center lid, meniscus and glass overrun.. The basic pin spacing is.00 (.mm) between centerlines. Each pin centerline shall be located within ±.00 (.mm) of its exact longitudinal position relative to pins and 0.. pplies to all four corner's (leads number, 0,, and 0). 7. "e" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90.. ll leads Increase maximum limit by.00(.0mm) measured at the center of the flat, when lead finish is applied. 9. Eighteen spaces. D Note E s e e Q L a c b b 0
PRODUCT SPECIFICTION Mechanical Dimensions (continued) 0-Terminal LCC Symbol Inches Millimeters Min. Max. Min. Max..00.00..,.00.0.7., B.0.0..7 B.00.0.. D/E...9 9.09 D/E D/E D/E e h j L L L ND/NE N.00 BSC.0 BSC.00 BSC. BSC. 9.09 Notes.00 BSC.7 BSC.00 REF.0 REF.00 REF. REF.0.0..0.07.09.9..00.0.0. 0 0, Notes:. The index feature for terminal identification, optical orientation or handling purposes, shall be within the shaded index areas shown on planes and. Plane, terminal identification may be an extension of the length of the metallized terminal which shall not be wider than the B dimension.. Unless otherwise specified, a minimum clearance of.0 inch (0.mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.).. Dimension "" controls the overall package thickness. The maximum "" dimension is the package height before being solder dipped.. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the drawing. The index corner shall be clearly unique.. Dimension "B" minimum and "L" minimum and the appropriately derived castellation length define an unobstructed three dimensional space traversing all of the ceramic layers in which a castellation was designed. Dimensions "B" and "L" maximum define the maximum width and depth of the castellation at any point on its surface. Measurement of these dimensions may be made prior to solder dripping.. Chip carriers shall be constructed of a minimum of two ceramic layers. E E LID PLNE PLNE D D (j) X (h) X PLCS INDEX CORNER e E E B D D L L L DETIL "" DETIL "" B
PRODUCT SPECIFICTION Ordering Information Part Number Package Operating Temperature Range RVM 0 Lead SOIC -0 C to + C D 0 Lead Ceramic DIP - C to + C L 0 Terminal Leadless Chip Carrier - C to + C LIFE SUPPORT POLICY FIRCHILD S PRODUCTS RE NOT UTHORIZED FOR USE S CRITICL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN PPROVL OF THE PRESIDENT OF FIRCHILD SEMICONDUCTOR CORPORTION. s used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.. critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com /0/9 0.0m 00 Stock# DS000 Ó 99 Fairchild Semiconductor Corporation