LH5P8128 FEATURES 131,072 8 bit organization Access times (MAX.): 60/80/100 ns Cycle times (MIN.): 100/130/160 ns Single +5 V power supply Power consumption: Operating: 572/385/275 mw (MAX.) Standby (CMOS level): 1.1 mw (MAX.) TTL compatible I/O Available for auto-refresh and self-refresh modes 512 refresh cycles/8 ms Compatible with standard 1M SRAM pinout Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 8 20 mm 2 TSOP (Type I) DESCRIPTION The LH5P8128 is a 1M bit Pseudo-Static RAM organized as 131,072 8 bits. It is fabricated using silicon-gate CMOS process technology. A PSRAM uses on-chip refresh circuitry with a DRAM memory cell for pseudo static operation which eliminates external clock inputs, while having the same pinout as industry standard SRAMs. Moreover, due to the functional similarities between PSRAMs and SRAMs, existing 128K 8 SRAM sockets can be filled with the LH5P8128 with little or no changes. The advantage is the cost savings realized with the lower cost PSRAM. The LH5P8128 PSRAM has the ability to fill the gap between DRAM and SRAM by offering low cost, low power standby and a simple interface. CMOS 1M (128K 8) Pseudo-Static RAM PIN CONNECTIONS 32-PIN DIP 32-PIN SOP 1 32 A 16 2 31 A 14 3 30 A 12 4 29 A 7 A 6 5 6 28 27 A 13 A 8 A 5 A 4 7 8 26 25 A9 A 11 A 3 A 2 9 10 24 23 A 10 A 1 A 0 11 12 22 21 I/O 7 I/O 0 I/O 1 I/O 2 13 14 15 20 19 18 I/O 6 I/O 5 I/O 4 GND 16 17 V CC A 15 I/O 3 Figure 1. Pin Connections for DIP and SOP Packages 32-PIN TSOP (Type I) A 11 A 9 A 8 A 13 A 15 V CC A 16 A 14 A 12 A 7 A 6 A 5 A 4 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 16 18 17 TOP VIEW 5P8128-1 A 10 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A 0 A 1 A 2 A 3 NOTE: Reverse bend available on request. 5P8128-1A Figure 2. Pin Connections for TSOP Package 1
LH5P8128 CMOS 1M (128K 8) Pseudo-Static RAM 16 GND 32 V CC A 0 12 A 1 11 A 2 10 A 3 9 A 4 8 A 5 7 A 6 6 A 7 5 A 8 27 A 9 26 A 10 23 A 11 25 A 12 4 A 13 28 A 14 3 A 15 31 A 16 2 COLUMN BUFFER ROW BUFFER REFRESH COUNTER EXT/INT MUX ROW DECODER COLUMN DECODER SENSE AMPS MEMORY ARRAY I/O SELECTOR V BB GENERATOR DATA IN BUFFER DATA OUT BUFFER 13 I/O 0 14 I/O 1 15 I/O 2 17 I/O 3 18 I/O 4 19 I/O 5 20 I/O 6 21 I/O 7 22 30 CLOCK GENERATOR REFRESH CONTROLLER REFRESH TIMER 1 24 29 NOTE: Pin numbers apply to the 32-pin DIP or SOP. 5P8128-2 Figure 3. LH5P8128 Block Diagram PIN DESCRIPTION SIGNAL PIN NAME SIGNAL PIN NAME A 0 - A 16 Address input Read/Write input Output Enable Input, Chip Enable input Refresh input Data input/output 2
CMOS 1M (128K 8) Pseudo-Static RAM LH5P8128 ABSOLUTE MAXIMUM RATINGS Operating current Standby current PARAMETER SYMBOL RATING UNIT NOTE Applied voltage on any pins V T -1.0 to +7.0 V 1 Output short circuit current I O 50 ma Power dissipation P D 600 mw Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +150 C NOTE: 1. The maximum applicable voltage on any pin with respect to GND. RECOMMENDED OPERATING CONDITIONS (T A = 0 to +70 C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage Input voltage Self-refresh average current V CC 4.5 5.0 5.5 V GND 0 0 0 V 2.4 V CC + 0.3 V -1.0 0.8 V CAPACITANCE (T A = 0 to +70 C, f = 1MHz, V CC = 5.0 V ±10%) PARAMETER CONDITIONS SYMBOL MIN. MAX. UNIT A 0 - A 16 C IN1 8 pf Input capacitance, C IN2 5 pf, C IN3 5 pf C IN4 5 pf Input/output capacitance C OUT1 10 pf DC CHARACTERISTICS (T A = 0 to +70 C, V CC = 5.0 V ±10%) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE LH5P8128-60 104 LH5P8128-80 I CC1 trc = t RC (MIN) 70 LH5P8128-10 50 ma 1, 2 TTL Input 1 1, 3 I CC2 ma CMOS Input 0.2 1, 4 TTL Input 1 1, 5 I CC3 ma CMOS Input 0.2 1, 6 Input leakage current I LI 0 V V IN 6.5 V 0 V except on test pins -10 10 µa Output in highimpedance -10 10 µa I/O leakage current I LO state 0 V V OUT V CC + 0.3 V Output HIGH voltage I OUT = -1 ma 2.4 V Output LOW voltage I OUT = 4 ma 0.4 V NOTES: 1. Specified values are with outputs open. 2. Depends on the cycle time. 3. =, = 4. = V CC - 0.2 V, = V CC - 0.2 V 5. =, = 6. = V CC - 0.2 V, = 0.2 V 3
LH5P8128 CMOS 1M (128K 8) Pseudo-Static RAM AC ELECTRICAL CHARACTERISTICS 1,2,3 (T A = 0 to +70 C, V CC = 5.0 V ±10%) PARAMETER SYMBOL LH5P8128-60 LH5P8128-80 LH5P8128-10 MIN. MAX. MIN. MAX. MIN. MAX. Random read, write cycle time t RC 100 130 160 ns Read modify write cycle time t RMW 165 195 235 ns CE pulse width t CE 60 10,000 80 10,000 100 10,000 ns CE precharge time t P 40 40 50 ns Address setup time t AS 0 0 0 ns 4 Address hold time t AH 15 20 25 ns 4 Read command setup time t RCS 0 0 0 ns Read command hold time t RCH 0 0 0 ns CE access time t CEA 60 80 100 ns 5 access time t A 25 30 35 ns 5 CE to output in Low-Z t CLZ 20 20 20 ns to output in Low-Z t OLZ 0 0 0 ns Output enable from end of write t WLZ 0 0 0 ns Chip disable to output in High-Z t CHZ 20 25 30 ns Output disable to output in High-Z t OHZ 20 25 30 ns Write enable to output in High-Z t WHZ 20 25 30 ns setup time t S 0 0 0 ns hold time t H 10 10 10 ns Write command pulse width t WP 30 30 30 ns Write command setup time t WCS 30 30 30 ns Write command hold time t WCH 40 50 60 ns Data setup time from write t DSW 25 30 35 ns 6 Data setup time from CE t DSC 25 30 35 ns 6 Data hold time from write t DHW 0 0 0 ns 6 Data hold time from CE t DHC 0 0 0 ns 6 Transition time (rise and fall) t T 3 35 3 35 3 35 ns Refresh time interval t REF 8 8 8 ms Refresh command hold time 15 15 15 ns Auto refresh cycle time t FC 100 130 160 ns Refresh delay time from CE 30 40 50 ns Refresh pulse width (Auto refresh) t FAP 30 8,000 30 8,000 30 8,000 ns Refresh precharge time (Auto refresh) t FP 30 30 30 ns Refresh pulse width (Self refresh) t FAS 8,000 8,000 8,000 ns CE delay time from refresh precharge (Self refresh) t FRS 140 160 190 ns UNIT NOTE NOTES: 1. In order to initialize the circuit, should be kept at or should be kept at for 100 µs after power-up, followed by at least 8 dummy cycles. 2. AC characteristics are measured at t T = 5 ns. 3. AC characteristics are measured at the following condition (see figure at right). 4. Address is latched at the negative edge of or at the positive edge of. 5. Measured with a load equivalent to 2TTL + 100 pf. 6. Data is latched at the positive edge of W/R or at the positive edge of or at the negative edge of. INPUT OUTPUT 2.4 V 0.8 V 2.2 V 0.8 V Figure 4. AC Characteristics 2.6 V 0.6 V 5P8128-3 4
CMOS 1M (128K 8) Pseudo-Static RAM LH5P8128 t RC t P t CE t AS t AH A 0 - A 16 INPUT t RCS t RCH t A t CEA t OHZ t OLZ t CLZ t CHZ VALID-DATA OUTPUT t FP t FRS NOTE: Operation possible using only ( ) by fixing to LOW ( to HIGH). 5P8128-4 Figure 5. Read Cycle 5
LH5P8128 CMOS 1M (128K 8) Pseudo-Static RAM t RC t P t CE t AS t AH A 0 - A 16 INPUT t S t H t WCS t WCH t WP t DSW t DHW t DSC t DHC DATA INPUT t FP t FRS NOTE: Operation possible using only ( ) by fixing to LOW ( to HIGH). 5P8128-5 Figure 6. Write Cycle 1 ( = HIGH) 6
CMOS 1M (128K 8) Pseudo-Static RAM LH5P8128 t RC t P t CE t AS t AH A 0 - A 16 INPUT t WCS t WCH t WP t DSW t DHW t DSC t DHC D IN VALID DATA INPUT t WHZ t OLZ t CLZ t OHZ t WLZ t CHZ D OUT t FP t FRS NOTE: Operation possible using only ( ) by fixing to LOW ( to HIGH). 5P8128-6 Figure 7. Write Cycle 2 ( Clock) 7
LH5P8128 CMOS 1M (128K 8) Pseudo-Static RAM t RC t P t CE t AS t AH A 0 - A 16 INPUT t WCS t WCH t WP t DSW t DHW t DSC t DHC D IN VALID DATA INPUT t WHZ t CHZ t CLZ t WLZ D OUT t FP t FRS NOTE: Operation possible using only ( ) by fixing to LOW ( to HIGH). 5P8128-7 Figure 8. Write Cycle 3 ( = LOW) 8
CMOS 1M (128K 8) Pseudo-Static RAM LH5P8128 t RMW t P t AS t AH A 0 - A 16 INPUT t RCS t WCS t WP t A t DSW t DHW t CEA t DSC t DHC D IN DATA INPUT t OLZ t WHZ t CHZ t CLZ t OHZ t WLZ D OUT DATA OUTPUT t FP t FRS NOTE: Operation possible using only ( ) by fixing to LOW ( to HIGH). 5P8128-8 Figure 9. Read-Modify-Write Cycle 9
LH5P8128 CMOS 1M (128K 8) Pseudo-Static RAM t RC t P t CE t AS t AH A 0 - A 8 INPUT t H t S t RCS t RCH t FP HIGH-Z t FRS NOTE: A 9 - A 16 = Don't Care. 5P8128-9 Figure 10. CE Only Refresh OR t FP t FAS t FRS HIGH-Z NOTE:,, A 0 - A 16 = Don't Care. 5P8128-10 Figure 11. Self Refresh Cycle 10
CMOS 1M (128K 8) Pseudo-Static RAM LH5P8128 OR t FC t FC t FP t FAP t FP t FAP t FP NOTE:,, A 0 - A 16 = Don't Care. HIGH-Z Figure 12. Auto Refresh Cycle 5P8128-11 11
LH5P8128 CMOS 1M (128K 8) Pseudo-Static RAM PACKAGE DIAGRAMS 32DIP (DIP032-P-0600) 32 17 DETAIL 13.45 [0.530] 12.95 [0.510] 1 16 41.30 [1.626] 40.70 [1.602] 0.30 [0.012] 0.20 [0.008] 0 TO 15 4.50 [0.177] 4.00 [0.157] 15.24 [0.600] TYP. 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] 5.20 [0.205] 5.00 [0.197] 3.50 [0.138] 3.00 [0.118] 0.51 [0.020] MIN. DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32DIP 32-pin, 600-mil DIP 32SOP (SOP032-P-0525) 0.50 [0.020] 0.30 [0.012] 1.27 [0.050] TYP. 1.40 [0.055] 32 17 11.50 [0.453] 11.10 [0.437] 14.50 [0.571] 13.70 [0.539] 12.50 [0.492] 1 20.80 [0.819] 20.40 [0.803] 16 1.40 [0.055] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.275 [0.050] 2.90 [0.114] 2.50 [0.098] 0.20 [0.008] 0.00 [0.000] 1.275 [0.050] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32-pin, 525-mil SOP 32SOP 12
CMOS 1M (128K 8) Pseudo-Static RAM LH5P8128 32TSOP (Type I) (TSOP032-P-0820) 32 0.30 [0.012] 0.10 [0.004] 0.50 [0.020] TYP. 17 18.60 [0.732] 18.20 [0.717] 20.30 [0.799] 19.70 [0.776] 19.00 [0.748] 1 16 8.20 [0.323] 7.80 [0.307] 0.15 [0.006] 1.10 [0.043] 0.90 [0.035] 0.20 [0.008] 0.10 [0.004] 1.20 [0.047] MAX. 0.425 [0.017] 0.20 [0.008] 0.00 [0.000] DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT MINIMUM LIMIT 32TSOP 32-pin, 8 20 mm 2 TSOP (Type I) ORDERING INFORMATION LH5P8128 Device Type X Package - ## Speed 60 60 80 80 10 100 Access Time (ns) Blank 32-pin, 600-mil DIP (DIP032-P-0600) N 32-pin, 525-mil SOP (SOP032-P-0525) T 32-pin, 8 x 20 mm 2 TSOP (Type I) (TSOP032-P-0820) TR 32-pin, 8 x 20 mm 2 TSOP (Type I) Reverse bend (TSOP032-P-0820) CMOS 1M (128K x 8) Pseudo-Static RAM Example: LH5P8128N-60 (CMOS 1M (128K x 8) Pseudo-Static RAM, 60 ns, 32-pin, 525-mil SOP) 5P8128-12 13
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