Lecture 04: Single Transistor Ampliers

Lecture 04: Single Transistor Ampliers Analog IC Design Dr. Ryan Robucci Department of Computer Science and Electrical Engineering, UMBC Spring 2015 Dr. Ryan Robucci Lecture IV 1 / 37

Single-Transistor Ampliers Common Source Common Drain Common Gate Dr. Ryan Robucci Lecture IV 2 / 37

Common Source Aplier (1) sat cutoff nonsat When leave sat? Approach: Use equation V D = V G V TH V OUT = V IN V TH Must nd unknown voltage V OUT in terms of input Assume Saturation V DD V out R D = k W L 2 V GS V }{{ T } V ov 2 V out = R D k W L 2 V GS V }{{ T V } DD V ov 2 Dr. Ryan Robucci Lecture IV 3 / 37

Common Source Aplier (2) V IN V TH = V out = R D k W L 2 V IN V }{{ TH } V ov 0 = R D k W L 2 V IN = 1± k = R W L D 2 V GS V }{{ T V } DD V ov V GS V }{{ T } V DD V ov 2 V GS V }{{ T } V IN V TH V }{{} DD V ov V ov 1+4R D k W L 2 R D k W L 2 2 = V in,sat (pos. answer is the obvouis choice) Dr. Ryan Robucci Lecture IV 4 / 37

Common Source Aplier (3) For V in > V in,sat k V out = V DD R W ( L D 2 2Vov V out Vout) 2 For linear region (V out 2V ov ): k V out V DD R W L D 2 (2V ov V out ) V out V DD R D k W L V ov V ( out V out 1 + RD k W L V ) ov VDD V out V DD (1+R D k W L V ov) = ( V DD ) 1 1+R D R ON Now let R ON = 1 V out V out V DD k W L V ov ( V DD ) 1 1+R D R ON R ON (R ON +R D ) (a simple voltage divider) Dr. Ryan Robucci Lecture IV 5 / 37

Common Source Aplier (4) However the highest gain is in the sat region: k d R W L D 2 V GS V }{{ T } Vov A V = dv out,sat dv in = dv in A V = g m R D Compare with Small Signal Approach: 0 v o R D v o vi = g m v i = g m R D (same as before) 2 V DD What happens when λ 0 v o vi = g m (R D r d ) What is the limit as R D is increased? Note (R D r d ) R D and (R D r d ) r d If R D r d, R out r d, A v g m r d If r d R D, R out R D, A v g m r d = R D k W L V ov Dr. Ryan Robucci Lecture IV 6 / 37

Ideal Current-Source Load (1) With R D replaced with in the small signal model, the gain is: A v = g m r ds To set these values in a design, we must choose the bias current. The value of the current source, I b, becomes the the transisor bias current, I bias, in the design. Choose I bias based on desired values for the input voltage bias, g m, power(current),etc.. Dr. Ryan Robucci Lecture IV 7 / 37

Ideal Current-Source Load (2): Design of the input bias point Note: In practice, high-gain circuits have a very limited input range Some intuative nessisity for for this is as follows: Output range is practically limited by the supply rails. Input range size is output range size A v Bias Point? Output Range Input Range Therefore, if output range size is <5 V and gain is A v = 100, the input range size is <50 mv For high gain circuits, we conceptually design an input bias point, V in,bias, rather than an input range dened by two values, V in,min and V in,max Typically start by assumming I bias I D,sat Then, V in,bias is dened by the decided bias current, I bias, 2I and the relation V ov = bias k W L Dr. Ryan Robucci Lecture IV 8 / 37

Ideal Current-Source Load (3): Output Range V out,max : The ideal current source presents no maximum on the output voltage, though if we are approximating a practical circuit we expect V out < V DD = V out,max V out,min : The transistor presents a lower bound on V out to maintain saturation V out > V in V th V out,min = V in,bias V TH = V ov What parameters aect V ov? V ov = 2I bias k W L Dr. Ryan Robucci Lecture IV 9 / 37

Ideal Current-Source load (4): Ex. Design Modication Take a situation in which after simulation you are satised with the gain but need to lower the input bias point to make it compatible with another circuit. How can you lower V out,min without sacracing gain ( g m r d )? A v = g m r d = 2I 1 V ov λi = 1 λv ov now, λ 1 L and V ov = 2I k WL 2I k W L so, A v input bias determined by V ov = 2IL k W You'll nd that to maintain A v and lower the input bias, more than one free design parameter must be changed. L and I may be decreased proportionally so that L I is constant The cost of this solution is more size and lower bandwidth W = more parasitics I = R = (RC out ) = B.W. Dr. Ryan Robucci Lecture IV 10 / 37

PFET (less-ideal) current source (1) To design for the PFET choose V bias such that I sat for PFET is the same as the desired I bias To approximate a current source, the L for the PFET can be made large so that R out is large Model for saturated PFET acting as current source is shown. (Optional in-class sidebar current and voltage sources) Dr. Ryan Robucci Lecture IV 11 / 37

PFET (less-ideal) current source (2) Gain Finding Gain: (done as example in-class) R out = r d,p r d,n G m = g m,n A v = g m,n ( rd,p r d,n ) Dr. Ryan Robucci Lecture IV 12 / 37

PFET (less-ideal) current source (3) Why not just use a resistor with value of r d,p? Take example: [ λ p = 1 100 V 1 ] for a 1-µm eective length device I bias = 1 [µa] r d,p = 1 = 100M 1 10 6 For a resistor of 100M, the voltage drop with 1 µa would be 100V! Furthermore, the PFET L eff can be modied to alter the relationship. Transistor loads allow exibility in terms of designing the small-signal resistance and bias point. λi bias = 100 Dr. Ryan Robucci Lecture IV 13 / 37

PFET (less-ideal) current source (4): Output range However, this active load limits output range as compared to an Ideal current source as V out > V bias + V Tp, PFET leaves saturation and rd,p is replaced with 1 β(v SG V Tp ) So V out,max = V dd V sd,sat Output Range: V ds,sat,n < V out < V dd V sd,sat,p V ov,n < V out < V dd V ov,p OUTPUT RANGE is a key concept in Analog Design Dr. Ryan Robucci Lecture IV 14 / 37

Source Follower (Common Drain, Level Shifter) (1) sat cutoff nonsat A grounded bulk implies V GB = V G and V SB = V S A xed bulk implies v gb = v g and v sb = v s for the small-signal model As V i increases when does the transistor leave saturation? Ans: V i > V DD + V TH As V i decreases, when is cut-o achieved? Dr. Ryan Robucci Lecture IV 15 / 37

Source Follower (Common Drain, Level Shifter) (2) g m v in = v o R s + g s v o + v o v o r ds 1 R v in = g m 1 Rs +g = g s r ds S + r 1 m ds if g s R s 1 and g s r ds 1 v o v in g m gs g m gs = 1 n = κ = c ox c ox +c dep = 1 1+η 1 in strong inversion g S r ds R S +R s +r ds Dr. Ryan Robucci Lecture IV 16 / 37

Source Degenerated Amplier (1) As V in increases I will increase as V out decreases V s increases (as in source follower) When V OUT < V G V TH FET LEAVES SAT At what rate does Vout drop in the high gain region? To answer, can use small signal analysis. Dr. Ryan Robucci Lecture IV 17 / 37

Source Degenerated Amplier (2) (R out ) R out = R up R down R up = R D R down : Set V i xed (0): R down : v s = i t R S v x = v s + (i t + g s v s )r ds v x = i t R s + (i t + g s R s )r ds v x it v x it = R s + (1 + g s R s )r ds = R s + r ds + g s r ds R s ****This result we will want to utilize often: resistance looking into drain*** R eq = R s + r ds + g s r ds R s g s R s 1 may ignore r ds g s r ds 1 may ignore R S If both assumptions apply : R eq g s r ds R s R out R D (g s r ds R s + R s + r ds ) Dr. Ryan Robucci Lecture IV 18 / 37

Source Degenerated Amplier (3) (G m ) Set ouput to 0V A G m = i o vi =? Dr. Ryan Robucci Lecture IV 19 / 37

Source Degenerated Amplier (4) (G m ) Solve for unknown v s ) (1a) g m v i = v s (g S + 1 r ds + 1 R s g (1b)v s = v m i g S + 1 r ds + 1 Rs (2a) note i o = i x = v s R s (or just proceed with standard brute-force KCL) i o = v i g m r ds using (1b) i o v i = g S r ds R S +R S +r ds g m r ds g S r ds R S +R S +r ds g m G m = ( g s + Rs 1 + r )R 1 s ds as before, if g s R s r ds R s,r ds G m g mr ds g S r ds = g m 1 gs R s above threshold κ 1 G m 1 R s Dr. Ryan Robucci Lecture IV 20 / 37

Source Degenerated Amplier (5) (A v = G m R out ) g A v = G m R out = ( m R s g s + 1 + 1 )(R D (g s r ds R s + R s + r ds )) }{{} R r ds R D s }{{} gs Under some assumptions: A v g m R D gs Rs R D Rs (make sense?) R out R D BW = 1 C out R out Dr. Ryan Robucci Lecture IV 21 / 37

Source Degenerated Amplier (6) (source node) Take source node as output instead: R out = R up R down R down = R s Dr. Ryan Robucci Lecture IV 22 / 37

Source Degenerated Amplier (7) (source node) Set v i = 0 R eq = v x it =? v d = i z R D = i t R D (simplest equation that is in terms of input) v y = v d + v ds = v d + i rds r ds = v d + (i t v y g s )r ds (KVL using resistors) v y = i t R D + (i t v y g s )r ds Looking into source equation R eq = v y i t = R D+r ds 1+r ds g s Dr. Ryan Robucci Lecture IV 23 / 37

Resistance Looking into Source R eq = R D+r ds 1+g s r ds You will sometimes see R eq = R D+r ds 1+g m r ds if g mb is ignored note the following approximations (assuming g s r ds 1) if then R D r ds R D r ds R D r ds R eq R D g s r ds R eq 2 g s R eq = 1 g s Dr. Ryan Robucci Lecture IV 24 / 37

Common Gate Amplier (Current Buer) As V in increases, current decreases and V o increases V DD V o sat ~g s R D V G -V TH FET Leaves SAT V G -V TH V G FET is "off" I is nearly 0 In sat region: G m = g s + 1 r ds g s R out = R D r ds R in (input resistance) is low (looking into source equation) V i Dr. Ryan Robucci Lecture IV 25 / 37

Common Gate Amplier Output Range Transistor saturation condition limits ouput: V out > V B V TH Bias point of input is tied to V B and current: V B = V in + V ov + V TH = V in + 2I + V k W TH L Dr. Ryan Robucci Lecture IV 26 / 37

Common Gate, AC-Coupled An issue with the previous circuits is that DC current is drawn from the input. This can be resolved with an AC-coupled input: DC operating point is independant of the input DC level DC current is not drawn from input, though AC current is drawn Input impedance still low at most frequencies (though DC input resistance is ) Output resistance is high (R D casaded resistance) Dr. Ryan Robucci Lecture IV 27 / 37

Common Gate Amplier (Current Buer) Pseudo Small-Signal Here we'll assume the capacitor can be treated as a short Pseudo-Small Signal Drawing: For this class is a small-signal drawing using a transistor symbol as a shorthand for the transistor's small signal equivalence. If we include a source resistance R S between the input voltage source and source terminal: R out = R D (g m r ds R s + R s + r ds ) R D }{{} 1 G m = ( 1 R s + ) g s + 1 r }{{ ds } 1/gs if gs r ds 1 g s R s g s +1 if (g m r ds R s +R s +r ds ) R D If 1 g s R s, G m 1 R s Dr. Ryan Robucci Lecture IV 28 / 37

Common Gate Current Buer The original circuit: Current-Output Device Transimpedance (I-to-V) Amplifier Current Buffer The common-gate transistor can preferably be thought of as a current buer. In the circuit shown: looking into the source, the equivelent resistance R SS is lower than the added output load resistance R D. Looking into the drain, the equvilent resistance R DD, is higher then R s. In the common-gate voltage amplier we use R D to generate an output voltage. Dr. Ryan Robucci Lecture IV 29 / 37

Common Gate Current Buer Example (1) Sensor-Circuit (Pseudo) Small-Signal Model Resistor Alone as I-to-V Transimpedance (I-to-V) Amplifier Using Common-Gate Transimpedance (I-to-V) Amplifier Current Buffer Transimpedance (I-to-V) Amplifier Current Buffer Assume a sensor with the following characteristics: 100 µa on top of 1 ma bias current with a x output voltage, and an output resistance of 100K Assume the sensor parasitic capacitance, c S, is 1pF Assume we want 1 V output modulation and bandwith 100 Mhz Dr. Ryan Robucci Lecture IV 30 / 37

Common Gate Current Buer Example (2) Ideally we want v o is = R D and we might choose R D to be 10k. However, the actual gain is less because the actual sensor current is sensitive to the voltage. In this case the output voltage swing, which we require, is seen by the sensor. v o is = R D r s = 10k 100k 10k+100k 9.09k. An alternative intuition from the small-signal model is that ( the ideal signal current i s is divided between r s and R D. i in = i rs s (OPTIONAL SIDEBAR ON CURRENT DIVIDER) r s +R D ) Dr. Ryan Robucci Lecture IV 31 / 37

Common Gate Current Buer Example (3) An alternative using the common-gate conguration is shown. We'll assume the transistor along with V G is designed to obtain V ov = 0.5V at 1mA and λ = 1 1000 In this circuit the sensor sees resistance of R eq 1 g s = V on 2I = 250Ω if R D r ds. The output resistance is R D (r ds g s R S + r ds + R S ) = 10k (4m 100k 100k + 100k + 100k) 10k But what about the current i y I s? 100k 100k+250 now vs 100k 100k+10k berfore The current split is much better. The sensor sees a lower resistance yet the output resistance generating the output voltage swing is still high. The current buer has shielded the sensor from the voltage swing. Dr. Ryan Robucci Lecture IV 32 / 37

Common Gate Current Buer Example (4) Good Current-Current buer characteristics: Small input resistance, R IN R SOURCE : Input voltage does not uxuate with current and all intended current uxuations at the node are drawn into the buer. Large output resistance, R OUT R LOAD : Output current delivered to the load does not strongly depend on the output voltage (which means it is not sensitive to the load resistance). The ideal intended current is delivered to the load. However, there is one more advantge, even more critical...bw Resistor Current Buer Sensor Node Resistance 9.09 kω 250 Ω Sensor Node Time Constant τ = 9.09ns τ = 250ps Sensor Node BW 110 Mrad/s 4 Grad/s Sensor Node BW 17.5 MHz 637 MHz Dr. Ryan Robucci Lecture IV 33 / 37

Common Gate Current Buer Example (5) The lower impedance that the capacitor sees in parallel to it prevents the capacitor from drawing as much current. Therefore, the sensing circuit draws a larger percentage of the current. The -3dB frequency tells us when the capacitor draws an equal current to the resistance path it parallels. Transimpedance (I-to-V) Amplifier Current Buffer Dr. Ryan Robucci Lecture IV 34 / 37

Finding Time Constant of a Capacitor (1) We can nd the time constant of a capacitor by 1 replacing capacitor with a current source i t 2 nding the voltage v y created 3 R eq = v y i t 4 τ = R eq C Transimpedance (I-to-V) Amplifier Current Buffer + - Dr. Ryan Robucci Lecture IV 35 / 37

Finding Time Constant of a Capacitor (2) At ω = ω 3dB : R = 1 and i R = i C jωc The time constant provides us the frequency ω 3dB = 1 τ. At this frequency, the capacitor draws an equal magnitude of sinusoidal current to the resistance in parallel with it, though at a dierent phase. @DC: 1 A 3dB = v x /i x = R = A DC @ω = ω 3dB v x /i x = ( R 2 + R 2 + (R) 2 = A 3dB ) 2 1 ω 3dB C = 2 A DC Note log 10 ( 1 2 i C i R ) 3 Half Power Frequency: Also note vx,(@ω=ω 3dB 2 ) = 1 2 vx,(@dc) 2 A 3dB 2 = 1 A 2 DC 2 Dr. Ryan Robucci Lecture IV 36 / 37

Reminder Some hints discussed in solving small signal circuits Identify variables to eliminate (node voltages or currents) and try to choose and expression simplilest, most directly related to the input or output At times if there is a resistor between a node you have an expression for and another, nding the voltage accross the resistor can create a simple expression for the unknown voltage in terms of the known voltage When λ = 0 don't both with r ds throughout your work When calculating G m and consider the short a t the output, it is typical that a branch of your circuit can be quickly ignored Dr. Ryan Robucci Lecture IV 37 / 37