Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

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Lecture 1 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini; Chapter 4, Sections 4.54.6 6.12 Spring 29 Lecture 1 1

Large Signal Model for NMOS Transistor Regimes of operation: ID linear VDSsat=VGSVT saturation I D V DS VGS V GS V BS VGS=VT Cutoff cutoff VDS I D = Linear / Triode: W I D = L μ nc ox V GS V DS V T 2 V DS Saturation I D = I Dsat = W 2L μ nc ox V GS V T Effect of back bias [ ] 2 [ 1 V DS ] V T (V BS ) = V To [ 2 p V BS 2 ] p 6.12 Spring 29 Lecture 1 2

Smallsignal device modeling In many applications, we are only interested in the response of the device to a smallsignal applied on top of a bias. I D v ds v gs V GS v bs V BS V DS Key Points: Smallsignal is small response of nonlinear components becomes linear Since response is linear, lots of linear circuit techniques such as superposition can be used to determine the circuit response. Notation: i D = I D Total = DC Small Signal 6.12 Spring 29 Lecture 1 3

Mathematically: i D (V GS, V DS, V BS ; v gs, v ds, v bs ) I D ( V GS, V DS,V BS ) (v gs, v ds, v bs ) With linear on smallsignal drives: Define: = g m v gs g o v ds g mb v bs g m transconductance [S] g o output or drain conductance [S] g mb backgate transconductance [S] Approach to computing g m, g o, and g mb. g m i D v GS Q g o i D v DS Q g mb i D v BS Q Q [v GS = V GS, v DS = V DS, v BS = V BS ] 6.12 Spring 29 Lecture 1 4

Transconductance In saturation regime: i D = W 2L μ nc ox [ v GS V T ] 2 [ 1 V DS ] Then (neglecting channel length modulation) the transconductance is: g m = i D W v GS Q L μ n C ox ( V GS V T) Rewrite in terms of I D : g m = 2 W L μ n C ox I D gm saturation ID 6.12 Spring 29 Lecture 1 5

Transconductance (contd.) Equivalent circuit model representation of g m : G D v gs gm v gs S B i D (μa) 4 I D 3 = g m v gs V GS v gs I D 2 Q V GS 1 V DS 1 2 3 4 5 v DS (V) 6.12 Spring 29 Lecture 1 6

Output conductance In saturation regime: W 2 i D = 2L μ n C ox [v GS V T ] [1 v DS ] Then: W 2 i g D o = = μ n C ox (V GS V T ) I 2L D v DS Q Output resistance is the inverse of output conductance: Remember also: Hence: 1 1 r o = = g o I D 1 L r L o 6.12 Spring 29 Lecture 1 7

Output conductance (contd.) Equivalent circuit model representation of g o : G D S v gs r o i D (μa) B 4 I D I D 3 2 = g o v ds V GS, V BS Q 1 V DS v ds V DS v ds 1 2 3 4 5 V DS (V) 6.12 Spring 29 Lecture 1 8

Backgate transconductance In saturation regime (neglect channel length modulation): Then: Since: g mb = i D W 2L μ nc ox [ v GS V T ] 2 i D = W v BS Q L μ n C ox ( V GS V T) V T v BS Q V T (v BS ) = V To [ 2 p v BS 2 ] p Then : V T v BS Q = 2 2 p V BS Hence: g mb = g m 2 2 p V BS 6.12 Spring 29 Lecture 1 9

Backgate transconductance (contd.) Equivalent circuit representation of g mb : G D v gs gmb v bs S i D (μa) 4 B v bs I D 3 = g mb v bs V GS, V BS v bs I D 2 Q V GS, V BS 1 V DS 1 2 3 4 5 V DS (V) 6.12 Spring 29 Lecture 1 1

V DS V GS Metal interconnect to gate n polysilicon gate V BS = n source y n drain Q N (y) X d (y) x ptype Metal interconnect to bulk Figure by MIT OpenCourseWare. 6.12 Spring 29 Lecture 1

6Highfrequency smallsignal equivalent circuit model Need to add capacitances. In saturation: fringe electric field lines \... gate source... =',b, n... 4k ~N(%s) 4k1% depletion] overlapl overlap LD region I Cgs = channel charge overlap capacitance, C,, Cg, =overlap capacitance, C,, CSb= sourcejunction depletion capacitance (sidewall) C, = drain junction depletion capacitance (sidewall) ONLY Channel Charge Capacitance is intrinsic to device operation. All others are parasitic. 6.12 Spring 29 Lecture 1

Inversion layer charge in saturation q N (v GS ) = W L Q N (y)dy = W Q N (v C ) dy dv C v GS V T dv C Note that q N is total inversion charge in the channel & v C (y) is the channel voltage. But: Then: dv C dy = i D W μ n Q N (v C ) V GS V T [ ] 2 q N (v GS ) = W 2 μ n Q N (v C ) i D dv C Remember: Q N (v C ) = C [ ox v GS v C (y) V ] T Then: v GS V T [ ] 2 q N (v GS ) = W 2 μ n C 2 ox v GS v C (y) V T i D dv C 6.12 Spring 29 Lecture 1 13

Inversion layer charge in saturation (contd.) Do integral, substitute i D in saturation and get: Gate charge: q N (v GS ) = 2 3 WLC ox ( v GS V T) q G (v GS ) = q N (v GS ) Q B,max Intrinsic gatetosource capacitance: C gs,i = dq G dv GS = 2 3 WLC ox Must add overlap capacitance: C gs = 2 3 WLC ox WC ov Gatetodrain capacitance only overlap capacitance: C gd = WC ov 6.12 Spring 29 Lecture 1 14

ther capacitances SourcetoBulk capacitance:... csb = WLdvf cj (2~di&f w)cjsw where C :Bottom Wall at Vm (F 1em2) Cjsw DraintoBulk capacitance: Side Wall at VSB(F1cm) Cdb = WLdiffj (2~dijfw)cjsw where Cj :Bottom Wall at VDB(FI cm2) Cjsw Side Wall at VDB(F1cm) GatetoBulk capacitance: 6.12 Spring 29 Lecture 1.W

What did we learn today? Summary of Key Concepts Highfrequency smallsignal equivalent circuit model of MOSFET G C gd D S B v gs Cgs C gb v bs g m v gs g mb v bs r o C sb C db In saturation: g m r o L I D W L I D C gs WLC ox 6.12 Spring 29 Lecture 1 16

MIT OpenCourseWare http://ocw.mit.edu 6.12 Microelectronic Devices and Circuits Spring 29 For information about citing these materials or our Terms of Use, visit: http://ocw.mit.edu/terms.

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