Digital Integrated Circuits The Wire * Fuyuzhuo *Thanks for Dr.Guoyong.SHI for his slides contributed for the talk Introduction
The Wire transmitters receivers schematics physical 2
Interconnect Impact on Chip 3
Wire Models All-inclusive model Capacitance-only 4
Impact of Interconnect Parasitics Interconnect parasitics(cap./r./inductive) reduce reliability/performance/power Inductive ignored condition resistance of the wire is substantial enough long metal wire with a small cross section,or if the rise and fall times of the applied signal are slow Wires are short,cross section of the wire is large,or the interconnection has a low resistivity Interwire capacitance ignored condition Separation between neighboring wires is 5
Source: Intel Nature of Interconnect Local Interconnect Pentium Pro (R) Pentium(R) II Pentium (MMX) Pentium (R) Pentium (R) II No of nets (Log Scale) S Local = S Technology Global Interconnect S Global = S Die 10 100 1,000 10,000 100,000 Length (u) 6
INTERCONNECT Capacitance Introduction 7
Capacitance of Wire Interconnect V DD V DD V in C gd12 M2 C db2 V out C g4 M4 V out2 M1 C db1 C w Interconnect C g3 M3 Fanout Simplified Model V in V out C L 8
Capacitance: The Parallel Plate Model Too simplistic when W/H ratio become small c int t εdi = kε 0 di di WL H t di L W Current flow Dielectric Electrical-field lines k = 3.9 for SiO 2 Processes are starting to use low-k dielectrics k 3 (or less) as dielectrics use air pockets Substrate S Cwire S S S L 1 S L 9
Permittivity 10
Fringing Capacitance Over the years, a steady reduction in the W/H ratio which has even dropped below 1 (a) H W - H/2 + (b) 11
Fringing versus Parallel Plate Including fringing cap. Gap (from [Bakoglu89]) 12
Interwire Capacitance fringing parallel 13
Impact of Interwire Capacitance Interwire capacitance starts to dominate when W becomes smaller than 1.75H (from [Bakoglu89]) 14
Wiring Capacitances (0.25 mm CMOS) Area cap. af/um2 Fringing cap. af/um 15
Example Wire Capacitance Example 4.1: a global clock wire for 1 to 2 cm die size can reach a length of 10 cm. if the wire width is 1um and uses AL1. the wire capacitance is calculated as follows: 16
MIMI and fringe capacitor Poly-insulator-poly(PIP) Metal-insulator-Metal(MIM) Fringe capacitor 17
INTERCONNECT Resisitance Introduction 18
Wire Resistance R = L H W H L Sheet Resistance R o W R 1 R 2 19
Two conductor with equal R 20
Interconnect Resistance 21
Example Wire Resistance Example 4.2: A 10 cm long and 1 μm wide aluminum wire is routed on the first aluminum layer. Assuming a sheet resistance for Al of 0.075 Ω/. The total wire resistance is calculated as follows: 22
Resistance Estimation 23
Example : Parasitic R&C (1/5) 24
Example : Parasitic R&C (2/5) 25
Example : Parasitic R&C (3/5) 26
Example : Parasitic R&C (4/5) 27
Example : Parasitic R&C (4/5) 28
Example : Parasitic C (1/5) 29
Example : Parasitic C (2/5) 30
Example : Parasitic C (3/5) 31
Example : Parasitic C (4/5) 32
Example : Parasitic C (5/5) 33
Interconnect Scaling Effect Assume W (wire width), H (wire thickness), t (oxide thickness) all scaled down by S (S > 1). Assume local wire length L scaled down by S ( S > 1) and global wire scaled up by Sg(Sg< 1). 34
Interconnect Design Selective Scaling Try not to scale the wire thickness (H) Better interconnect material Copper (Cu) or silicides (better conductivity) Low-k material (lower capacitance) Advanced interconnect topology more interconnect layers thin-denseat lower layers; fat-widely-spacedat higher layers 35
Sheet Resistance 36
Modern Interconnect 37
Resistor layout Meander structure Undoped high-resistivity polysilicon 300-1000ohm/square 38
Crosstalk Floating line Driven line Miller effect Shielding Routing Low-k interconnect Encoding 39
Capacitive Coupling to Floating Line 40
Capacitive Crosstalk 41
Coupling Disturbance 42
Capacitive Coupling to Driven Line A step voltage change on line-x results in a transient on line-y For a step VX= 0->2.5V, VY is first charged to ΔV k = Y τ = τ C Y aggressor victim CXY + C = XY R R 1 1+ k aggressor victim + C Then discharges via R Y to 0 with time const (C (C ΔV Y X X + C XY XY ) ) 43
ΔV k Capacitive Coupling to Driven Line A step voltage change on line-x results in a transient on line-y For a step VX= 0->2.5V, VY is first charged to = Y τ = τ C Y aggressor victim CXY + C = XY R R 1 1+ k aggressor victim (C (C ΔV Y X X + C + C XY XY ) ) 1.8 1.5 1.2 0.9 Aggressor Victim (undriven): 50% 0.6 0.3 Victim (half size driver): 16% Victim (equal size driver): 8% Victim (double size driver): 4% 0 0 200 400 600 800 1000 1200 1400 1800 2000 t (ps) 44
Design Tips for Crosstalk Avoid floating nodes Floating nodes vulnerable to crosstalk Do not run wires in parallel for too long Increase the rise and fall time if possible Use differential signaling Less sensitive to noise Using shielding wires or layers to isolate signal lines 45
Shielding 46
Miller Effect of Crosstalk Delay depends on activity in neighboring wires When aggressor & victim lines switch in opposite directions, there exists Miller effect. 47
Impact of Crosstalk on Delay 48
Avoid Crosstalk by Encoding Delay variation is reduced to 2%. Area & capacitance increase by 5%. 49
Interconnect Organization Dense Wire Fabric ([Kathri2001]) Wires on adjacent layers are routed orthogonally. Signals on the same layer are separated by VDD and GND shields(used in FPGAs) V = V DD, S = Signal, G = GND 50
Interconnect Modeling 51
The Lumped C Model V out Driver c wire C lumped dv dt out V R out V driver in 0 V out ( t) (1 e t ) V, R driver C lumped R driver V out t pd = RCln 2 = 0.69RC = R'C V in C lumped 52
Lumped RC Model 53
Elmore Delay of RC-Network 54
Delay Elmore Delay Another Solution 55
Elmore Delay of RC Chain 56
Distributed versus Lumped 57
Distributed RC Distributed RC-line 58
Distributed Wire Model 59
Step Step-response of Diffusion response of Diffusion Eqn 60
Lumped vs Distributed Models Table 4-7 Step Response of Lumped and Distributed RC Networks: Points of Interest 61
Lumped & Distributed Together 62
example 63
Delay 64
Example Consider a 5mm long, 0.32um wide metal2 wire in a 180nm process. The sheet resistance is 0.05ohm/sheet and the capacitance is 0.2fF/um. Construct a 3-segment π-model for the wire Solution:The wire is 5000um/0.32um=15625 squares in length. The total resistance is (0.05ohm/Π)(15625Π)=781ohm. The total capacitance is (0.2fF/um).5000um=1pF. Each π-segment has onethird of this resistance and capacitance. The π-model is shown 65
Example -elmore model RC tree Figure shows a gate driving wires to two destinations. The gate is represented as a voltage source with effective resistance R1. the two receivers are located at nodes 3 and 4. the wire to node 3 is long enough that it is represented with a pair of π-segments, while the wire to node 4 is represented with a single segment. Find the Elmore delay from input x to each receiver The Elmore delays are T D3 =R 1 C 1 +(R 1 +R 2 )C 2 +(R 1 +R 2 +R 3 )C 3 +R 1 C 4 T D4 =R 1 C 1 +R 1 C 2 +R 1 C 3 +(R 1 +R 4 )C 4 66
Design rules 67
A close solution Delay time is τ ( V Break chain and Insert buffer n ) n CR k 0 eq k CR eq n( n 1) 2 68
Transmission gate delay optimization Total delay time Assume all has n transmission gate,break chain every m switchs,buffer delay time is t buf t p 0.69[ 0.69CR n m eq m( m 1) CReq ] ( 2 n( m 1) n ( 1) t 2 m n m buf 1) t buf 69
Optimal number of switch m optimal m optimal t p m t p 0 m n ntbuf 0.69CReq 2 2 m tbuf 1. 7 1. 7 CR eq 0 It is independent with n 70
Samsung DDR-3 4Gb 71
homework 72