Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Wire July 30, 2002 1
The Wire transmitters receivers schematics physical 2
Interconnect Impact on Chip 3
Wire Models All-inclusive model Capacitance-only Every physical object has resistance, capacitance, inductance! 4
Impact of Interconnect Parasitics Interconnect parasitics reduce reliability Why? affect performance and power consumption Classes of parasitics Capacitive Which one is worst? Resistive Inductive 5
Nature of Interconnect Local Interconnect Pentium Pro (R) Pentium(R) II Pentium (MMX) Pentium (R) Pentium (R) II No of nets (Log Scale) S Local = S Technology Global Interconnect S Global = S Die Source: Intel 10 100 1,000 10,000 100,000 Length (u) 6
INTERCONNECT 7
Capacitance of Wire Interconnect V DD V DD V in C gd12 M2 C db2 V out C g4 M4 V out2 M1 C db1 C w Interconnect C g3 M3 Fanout Simplified Model V in V out C L 8
Capacitance: The Parallel Plate Model L Current flow W Electrical-field lines H t di Dielectric Substrate c int = ε t di WL Cwire di S SL SL 9 S = S = 1
Permittivity 10
Fringing Capacitance L W Height >= Width Fringing can not be neglected H (a) H W - H/2 + Approximations (b) 11
Fringing versus Parallel Plate (from [Bakoglu89]) 12
Interwire Capacitance More capacitive load per wire Inter-wire crosstalk! fringing parallel 13
Impact of Interwire Capacitance (from [Bakoglu89]) 14
Wiring Capacitances (0.25 μm m CMOS) 15
INTERCONNECT 16
Wire Resistance R = ρ L H W H L Sheet Resistance R o W R 1 R 2 Ohms per square 17
Interconnect Resistance 18
Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials reduce average wire-length e.g. copper, silicides More Interconnect Layers reduce average wire-length 19
Polycide Gate MOSFET Silicide PolySilicon SiO 2 n + n + p Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly 20
Sheet Resistance Pre-silicided polysilicon process never route in Poly Even for silicided diffusion never route in diffusion due to high active/substrate capacitance 21
Modern Interconnect 22
Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric 23
Skin Effects W 24
INTERCONNECT 25
It Matters Ringing, overshoot, reflections, coupling, and switching noise (power supply) For wires in lower levels, above 30GHz For thick wires in higher levels, above 10GHz For Die Bond wires, and other packaging, above 100MHz 26
Interconnect Modeling 27
The Lumped Model V out Driver c wi re R driver V out V in C lumped 28
The Lumped RC-Model The Elmore Delay All the capacitors Only the resistors on the shared path Td i = R 1 C 1 +R 1 C 2 +(R 1 +R 2 )C 3 +(R 1 +R 2 )C 4 +(R 1 +R 3 +R i )Ci 29
The Ellmore Delay RC Chain For linear: Td i = C 1 R 1 +..C n( R 1 +R 2 R n ) 30
Wire Model Assume: Wire modeled by N equal-length segments For large values of N: Note: Quadratic in length! ½ simple value 31
The Distributed RC-line 32
Step-response of RC wire as a function of time and space 2.5 2 x= L/10 voltage (V) 1.5 1 0.5 x = L/4 x = L/2 x= L 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 time (nsec) 33
RC-Models Note Definitions! 34
Driving an RC-line R s (r w,c w,l) V out V in 35
Design Rules of Thumb rc delays should only be considered when t prc >> t pgate of the driving gate Lcrit >> t pgate /0.38rc rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line t rise < RC When not met, the change in the signal is slower than the propagation delay of the wire! 36 Digital EE141 Integrated Circuits 2nd MJIrwin, PSU, 2000 Wires