ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February 4, 2016 MOS SPICE Models, MOS Parasitic Details

Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model! First Order Capacitor Summary! Capacitance Implications 2

Review: nmos IV Characteristics 2 4 4 4 4 4 I D = 3 4 4 4 4 4 5 I S! # " W L! # " $ &e % V GS V th nkt /q $ & %!! # " 1 e # " V DS $ & kt /q % $ & 1+ λv DS % ( ) V GS V Tn Subthreshold µ n C ox W ( 2 L 2 ( V GS V Tn (V SB ))V DS V 2 DS )(1+ λ V DS ) V GS > V Tn,V DS < V GS Linear µ n C ox W ( 2 L V V (V ) GS Tn SB ) 2 (1+ λ V DS ) V GS > V Tn,V DS V GS V Tn Saturation, v sat C OX W ( V GS V th ) V / dsat -. 2 0 1 E y > E cn (short channel) Velocity Saturation 3

Simplified Design Flow! Design a circuit to perform a function with specified minimum speed and optimized power (minimized with an upper bound) " Zero order model to design topology " First order model to meet speed spec " Rise/fall times, propogation delay, gate capacitance, output stage equivalent resistance " Transistor IV curves today " Iterative SPICE simulation tweak knobs to optimize for power (switching (dynamic), leakage (static), etc.) 4

MOSFET Parasitic Capacitance! Any two conductors separated by an insulator form a parallel-plate capacitor! Two types " Extrinsic Outside the box (e.g. junction, overlap) " Intrinsic Inside the box (e.g. gate-to-channel) 5

Capacitance Roundup! C GS =C GCS +C GSO! C GD =C GCD +C GDO! C GB =C GCB! C SB =C diff! C DB =C diff intrinsic extrinsic 6

Extrinsic Overlap Capacitance

Overlap! gate/source and gate/drain overlap 8

Overlap! Length of overlap L D = L M L eff 2 L M L D L eff 9

Overlap Capacitance L M L D C = ε r ε 0 A d L eff C o = ε ox WL D t ox 10

Overlap Capacitance L M L D C = ε r ε 0 A d L eff C OX = ε OX t OX C o = ε ox WL D t ox C o = C ox WL D 11

Overlap Capacitance L M L D C = ε r ε 0 A d L eff C OX = ε OX t OX C o = ε ox WL D t ox C o = C ox WL D = C GSO = C GDO 12

Overlap Capacitance! It turns out that fringing field lines add significantly to the total capacitance! Estimates of the fringing field capacitances based on measurements are normally used! The gate-to-drain overlap capacitances are generally given as measured parameters in the MOSFET model files! The values are per-width values 13

Overlap Capacitance Name LEVEL Model Parameters Model type (1, 2, or 3) Units CBD Bulk-drain zero-bias p-n cap (not used) F CBS Bulk-source zero-bias p-n cap (not used) F CJ Bulk p-n zero-bias bottom cap/area F/m**2 CJSW Bulk p-n zero-bias perimeter cap/length F/m MJ Bulk p-n bottom grading coefficient MJSW Bulk p-n sidewall grading coefficient FC Empirical bulk p-n forward-bias cap coefficient CGSO Gate-source overlap cap/channel width F/m CGDO Gate-drain overlap cap/channel width F/m CGBO Gate-bulk overlap cap/channel width F/m NSUB Substate doping density 1/cm**3 NSS NFS Surface-state density Fast surface-state density 1/cm**2 1/cm**2 TOX Oxide thickness m TPG Gate material type: + 1 = opposite of substrate, - 1 = same as substrate, 0 = aluminum XJ Metallurgical junction depth m Scales with Width (W) 14

Extrinsic Junction Capacitance

Diode Capacitance! When a reverse voltage is applied to a PN junction, a depletion region containing almost no charge carriers is generated and acts similarly to the dielectric of a capacitor.! The depletion region increases in width as the reverse voltage across it increases.! If we imagine that the diode capacitance can be likened to a parallel plate capacitor, then as the plate spacing (i.e. the depletion region width) increases, the capacitance should decrease.! Increasing the reverse bias voltage across the PN junction therefore decreases the diode capacitance.! Worst case is in zero-bias case 16

Junction Capacitance n + n + 17

Junction Capacitance! 1 * -4: Sidewall Junction Capacitance, C jsw! 5: (Bottom) Junction Capacitance, C j 18

(Bottom) Junction Capacitance n + n + N D + V = Ext Bias --> V SB, V DB 19

(Bottom) Junction Capacitance n + n + N D + V = Ext Bias --> V SB, V DB C j0 = ε si x d = ε si q 2 N A N D N A + N D 1 φ 0 Zero-bias capacitance (F/cm 2 ) 20

Sidewall Junction Capacitance C j0sw = ε si q 2 N A (sw) N D N A (sw)+ N D 1 φ 0 (F/cm 2 ) (F/cm) 21

Junction Capacitance 22

Junction Capacitance C diff = C j WY + C jsw ( 2Y +W ) 23

Junction Capacitance Name LEVEL Model Parameters Model type (1, 2, or 3) Units CBD Bulk-drain zero-bias p-n cap (not used) F CBS Bulk-source zero-bias p-n cap (not used) F CJ Bulk p-n zero-bias bottom cap/area F/m**2 CJSW Bulk p-n zero-bias perimeter cap/length F/m MJ Bulk p-n bottom grading coefficient MJSW Bulk p-n sidewall grading coefficient FC Empirical bulk p-n forward-bias cap coefficient CGSO Gate-source overlap cap/channel width F/m CGDO Gate-drain overlap cap/channel width F/m CGBO Gate-bulk overlap cap/channel width F/m NSUB Substate doping density 1/cm**3 NSS NFS Surface-state density Fast surface-state density 1/cm**2 1/cm**2 TOX Oxide thickness m TPG Gate material type: + 1 = opposite of substrate, - 1 = same as substrate, 0 = aluminum XJ Metallurgical junction depth m Scales with Junction area or width 24

Capacitance Roundup! C GS =C GCS +C GSO! C GD =C GCD +C GDO! C GB =C GCB! C SB =C diff! C DB =C diff intrinsic extrinsic 25

Intrinsic

Gate-to-Channel Capacitance! Looks like parallel plate capacitance! Two components: " What is C GC? " What is C GB? 27

Gate-to-Channel Capacitance! Looks like parallel plate capacitance! Two components: Case: Strong Inversion " C GC " C GB =0 C GC = C ox WL eff 28

Gate-to-Channel Capacitance! Looks like parallel plate capacitance! Two components: Case: Strong Inversion " C GC Split evenly between S and D " C GB =0 C GC = C ox WL eff C GCS = C GCD = 1 2 C ox WL eff 29

Gate-to-Source Capacitance! Channel + Overlap C GS = C GCS + C GSO C GS = C OX WL D + 1 2 C WL " OX eff = C OX W L L M eff $ # 2 % '+ 1 & 2 C WL OX eff C GS = 1 2 C OX WL M 30

Gate-to-Drain Capacitance! Channel + Overlap C GD = C GCD + C GDO C GD = C OX WL D + 1 2 C WL " OX eff = C OX W L L M eff $ # 2 % '+ 1 & 2 C WL OX eff C GD = 1 2 C OX WL M 31

Channel Evolution: Weak Inversion 32

Channel Evolution: Weak Inversion! What happens to capacitance here? " Capacitor plate distance? 33

Channel Evolution: Weak Inversion! Capacitance becomes dominated by Gate-to-Body capacitance (C GCS,D =0)! Gate-to-body capacitance drops as V GS increases toward V th 34

Capacitance vs V GS (V DS =0) WLC OX C GC 0.5WLC OX C GCS =C GCD C GCB V GS Increasing V GS 35

Saturation Capacitance? 36

Saturation Capacitance?! Source end of channel in inversion! Voltage at drain end of channel at or below threshold! Capacitance shifts to source " Total capacitance reduced 37

Saturation Capacitance WLC OX 0.5WLC OX C GC C GCS C GCD (2/3)WLC OX 0 1 V DS /(V GS -V T ) 38

Capacitance Roundup! C GS =C GCS +C GSO! C GD =C GCD +C GDO Simplifiy: what is C G?! C GB =C GCB! C SB =C diff! C DB =C diff intrinsic extrinsic 39

First Order Capacitance Summary Opearation Region Subthreshold Linear Saturation C GCB C GCS C GCD C GC C G 40

First Order Capacitance Summary Opearation Region Subthreshold C GCB C GCS C GCD C GC C G Linear 0 C OX WL/2 C OX WL/2 Saturation C GCS = C GCD = 1 2 C oxwl effective 41

First Order Capacitance Summary Opearation Region C GCB C GCS C GCD C GC C G Subthreshold C OX WL 0 0 Linear 0 C OX WL/2 C OX WL/2 Saturation WLC OX C GC 0.5WLC OX C GCS =C GCD C GCB V GS 42

First Order Capacitance Summary Opearation Region C GCB C GCS C GCD C GC C G Subthreshold C OX WL 0 0 Linear 0 C OX WL/2 C OX WL/2 Saturation 0 (2/3)C OX WL 0 WLC OX 0.5WLC OX C GC C GCS C GCD (2/3)WLC OX 0 1 V DS /(V GS -V T ) 43

First Order Capacitance Summary Opearation Region + + = C GCB C GCS C GCD C GC C G Subthreshold C OX WL 0 0 C OX WL Linear 0 C OX WL/2 C OX WL/2 C OX WL Saturation 0 (2/3)C OX WL 0 (2/3)C OX WL 44

First Order Capacitance Summary Opearation Region C GCB C GCS C GCD C GC C G Subthreshold C OX WL 0 0 C OX WL C OX WL+2C O Linear 0 C OX WL/2 C OX WL/2 C OX WL C OX WL+2C O Saturation 0 (2/3)C OX WL 0 (2/3)C OX WL (2/3)C OX WL +2C O C o = C ox WL D = C GSO = C GDO 45

Capacitance Roundup! C GS =C GCS +C GSO! C GD =C GCD +C GDO! C GB =C GCB! C SB =C diff! C DB =C diff intrinsic extrinsic 46

One Implication 47

Step Response? 48

Step Response Voltage peaking! 49

Impact of C GD! What does C GD do to the switching response here? " V 2 " V out 50

Impact of C GD 51

Big Idea! Capacitance " From-To every terminal " Voltage dependent WLC OX C GC 0.5WLC OX C GCS =C GCD C GCB V GS WLC OX 0.5WLC OX C GC C GCS C GCD 0 1 V DS /(V GS -V T ) (2/3)WLC OX 52

Journal Thursday Fengbo Ren, A Configurable 12 237 ks/s 12.8 mw Sparse-Approximation Engine for Mobile Data Aggregation of Compressively Sampled Physiological Signals

Compressive Sampling! Sample at lower than the Nyquist rate and still accurately recover the signal, and in some cases exactly recover 54

Compressive Sampling! Sample at lower than the Nyquist rate and still accurately recover the signal, and in some cases exactly recover Sparse signal in time Frequency spectrum 55

Compressive Sampling! Sample at lower than the Nyquist rate and still accurately recover the signal, and in some cases exactly recover Undersampled in time 56

Compressive Sampling! Sample at lower than the Nyquist rate and still accurately recover the signal, and in some cases exactly recover Undersampled in time Undersampled in frequency (reconstructed in time with IFFT) 57

Compressive Sampling! Sample at lower than the Nyquist rate and still accurately recover the signal, and in some cases exactly recover! Requires sparsity and incoherent sampling Undersampled in time Undersampled in frequency (reconstructed in time with IFFT) 58

Example: Sum of Sinusoids! Sense signal randomly M times " M > C μ2(φ,ψ) S log N! Recover with linear program 59

Compressive Sampling Implications! Useful for real-time signal reconstruction to promote on-site analysis and processing for realtime applications " Timely prediction and decision-making! data size for on-site storage or transmission to the cloud can be further reduced " Save on power hungry memory operations with reduced data " Shuffle-mode memory scheme to reduce memory size/ space and therefore leakage " Reported 2x memory size reduction, and 40% power savings due to leakage reduction 60

Chip Implementation! 40nm CMOS Process! Leakage reduction using high-threshold (HVT) standard cells only! I DS = I S # " W L $ &e %! # " V GS V th nkt /q $ & %!! # " 1 e # " V DS $ & kt /q % $ & 1+ λv DS % ( ) " Standard-threshold (SVT) devices used to reduce delay in critical paths 61

Admin! HW 4 due Thursday, 2/18! Homework posted over the weekend " Need next weeks lectures to complete 62