The Wire 1
Interconnect Impact on Chip 2
Example: a Bus Network transmitters receivers schematics physical 3
Wire Models All-inclusive model Capacitance-only 4
Impact of Interconnect Parasitics Interconnect parasitics reduce reliability affect performance and power consumption Classes of parasitics Capacitive Resistive Inductive 5
Capacitance: The Parallel Plate Model L Current flow W Electrical-field lines H t di Dielectric Substrate c int = ε t di di WL S Cwire = S S S L = 1 S L 6
Permittivity 7
Fringing Capacitance c fringe c pp (a) H W - H/2 + (b) 8
Fringing versus Parallel Plate 9
Interwire Capacitance fringing parallel 10
Impact of Interwire Capacitance 11
Wiring Capacitances (0.25 μm CMOS) 12
Interwire Capacitance between parallel wires (0.25 μm CMOS) 13
Wire Resistance R = ρ L H W H L Sheet Resistance R o W R 1 R 2 14
Interconnect Resistance 15
Sheet Resistance 16
Polycide Gate MOSFET Silicide PolySilicon SiO 2 n + n + p Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly 17
Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials reduce average wire-length e.g. copper, silicides More Interconnect Layers reduce average wire-length 18
Modern Interconnect 19
Skin effect 20
Skin Effect and Aluminum Wires (H=0.7 μm) 21
Inductance Voltage drop : l, c inductance and capacitance (per unit lenght) of a wire Propagation speed : 22
Dielectric constants and wave propagation speed (μ r 1) 23
Interconnect Modeling 24
The Lumped Model V out Driver c wi re R driver V out V in C lumped 25
The Lumped RC-Model The Elmore Delay s 26
The Elmore Delay: : RC Chain 27
Wire Model Assume: Wire modeled by N equal-length segments For large values of N: 28
The Distributed RC-line 29
Step-response of RC wire as a function of time and space 2.5 2 x= L/10 voltage (V) 1.5 1 0.5 x = L/4 x = L/2 x= L 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 time (nsec) x is the distance between the observation point and the source 30
RC-Models 31
Design Rules of Thumb rc delays should only be considered when t prc t pgate of the driving gate L crit = t pgate /0.38rc rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line t rise < RC when not met, the change in the signal is slower than the propagation delay of the wire 32
Driving an RC-line R s (r w,c w,l) V out V in 33
Simulation Models for Distributed RC line 34
The Transmission Line V in r l l l l r r x r V out g c g c g c g c The Wave Equation 35
Trasmission line with terminating impedences Z S Z 0 Z L 36
Trasmission Line Terminations 37
Matched Termination Z 0 Z 0 Z L Series Source Termination Z S Z 0 Z 0 Parallel Destination Termination 38
Design Rules of Thumb Transmission line effects should be considered when the rise or fall time of the input signal (t r, t f ) is smaller than the time-of-flight of the transmission line (t flight ). t r (t f ) << 2.5 t flight = 2.5 L wire /υ Transmission line effects should only be considered when the total resistance of the wire is limited: R < 5 Z 0 The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance, R < Z 0 / 2 39