INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC6 74HC/HCT/HCU/HCMOS ogic Family Specifications The IC6 74HC/HCT/HCU/HCMOS ogic Package Information The IC6 74HC/HCT/HCU/HCMOS ogic Package Outlines 74HC/HCT67 4 x 4 register file; 3-state File under Integrated Circuits, IC6 December 199
FEATURES Simultaneous and independent read and write operations Expandable to almost any word size and bit length Output capability: bus driver I CC category: MSI GENERA DESCRIPTION The 74HC/HCT67 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TT (STT). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT67 are 16-bit 3-state register files organized as 4 words of 4 bits each. Separated read and write address inputs (R A, R B and W A,W B ) and enable inputs (RE and WE) are available, permitting simultaneous writing into one word location and reading from another location. The 4-bit word to be stored is presented to four data inputs (D to D 3 ). The W A and W B inputs determine the location of the stored word. When the WE input is OW, the data is entered into the addressed location. The addressed location remains transparent to the data while the WE input is OW. Data supplied at the inputs will be read out in true (non-inverting) form from the 3-state outputs (Q to Q 3 ). D n and W n inputs are inhibited when WE is HIGH. Direct acquisition of data stored in any of the four registers is made possible by individual read address inputs (R A and R B ). The addressed word appears at the four outputs when the RE is OW. Data outputs are in the high impedance OFF-state when RE is HIGH. This permits outputs to be tied together to increase the word capacity to very large numbers. Design of the read enable signals for the stacked devices must ensure that there is no overlap in the OW levels which would cause more than one output to be active at the same time. Parallel expansion to generate n-bit words is accomplished by driving the enable and address inputs of each device in parallel. QUICK REFERENCE DATA GND = V; T amb =2 C; t r =t f = 6 ns TYPICA SYMBO PARAMETER CONDITIONS HC HCT UNIT t PH / t PH propagation delay D n to Q n C = 1 pf; V CC = V 23 23 ns C I input capacitance 3. 3. pf C PD power dissipation capacitance per package notes 1 and 2 122 124 pf Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V CC 2 f i + (C V CC 2 f o ) where: f i = input frequency in MHz f o = output frequency in MHz (C V 2 CC f o ) = sum of outputs C = output load capacitance in pf V CC = supply voltage in V 2. For HC the condition is V I = GND to V CC ; for HCT the condition is V I = GND to V CC 1. V ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS ogic Package Information. December 199 2
PIN DESCRIPTION PIN NO. SYMBO NAME AND FUNCTION, 4 R A, R B read address inputs 8 GND ground ( V) 1, 9, 7, 6 Q to Q 3 data outputs 11 RE 3-state output read enable input (active OW) 12 WE write enable input (active OW) 14, 13 W A, W B write address inputs 1, 1, 2, 3 D to D 3 data inputs 16 V CC positive supply voltage Fig.1 Pin configuration. Fig.2 ogic symbol. Fig.3 IEC logic symbol. Fig.4 Functional diagram. WRITE MODE SEECT TABE OPERATING MODE write data INPUTS WE H D n INTERNA ATCHES (1) H data latched H X no change Note 1. The write address (W A and W B ) to the internal latches must be stable while WE is OW for conventional operation. READ MODE SEECT TABE OPERATING MODE read INPUTS Notes 1. The selection of the internal latches by read address (R A and R B ) are not constrained by WE or RE operation. H = HIGH voltage level = OW voltage level X = don t care Z = high impedance OFF-state OUTPUT RE INTERNA ATCHES (1) Q n disabled H X Z H H December 199 3
Fig. ogic diagram. December 199 4
DC CHARACTERISTICS FOR 74HC For the DC characteristics see 74HC/HCT/HCU/HCMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI AC CHARACTERISTICS FOR 74HC GND = V; t r =t f = 6 ns; C =pf SYMBO t PH / t PH t PH / t PH t PH / t PH t PZH / t PZ t PHZ / t PZ PARAMETER propagation delay 8 R A, R B to Q n 21 17 propagation delay 77 WE to Q n 28 22 propagation delay 74 D n to Q n 27 22 3-state output enable time 39 RE to Q n 14 11 3-state output disable time 47 RE to Q n 17 14 t TH / t TH output transition time 14 4 t W t su t su t h t h t latch write enable pulse width OW set-up time D n to WE set-up time W A, W B to WE hold time D n to WE hold time W A, W B to WE T amb ( C) 74HC +2 4 to +8 4 to+12 min. typ. max. min. max. min. max. 8 16 14 6 12 1 6 12 1 latch time 1 WE to R A, R B 2 17 14 4 3 1 1 6 2 2 28 1 8 19 39 33 2 43 2 43 1 3 26 1 3 26 6 12 1 1 2 17 7 1 13 7 1 13 12 2 21 24 49 42 31 63 4 31 63 4 19 38 33 19 38 33 7 1 13 12 24 2 9 18 1 9 18 1 1 3 26 29 9 37 7 64 37 7 64 22 4 38 22 4 38 9 18 1 UNIT TEST CONDITIONS V CC (V) 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. 4. WAVEFORMS Fig.6 Fig.7 Fig.7 Fig.9 Fig.9 Fig.6 December 199
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see 74HC/HCT/HCU/HCMOS ogic Family Specifications. Output capability: bus driver I CC category: MSI Note to HCT types The value of additional quiescent supply current ( I CC ) for a unit load of 1 is given in the family specifications. To determine I CC per input, multiply this value by the unit load coefficient shown in the table below. INPUT D n WE, W A W B R A R B RE UNIT OAD COEFFICIENT.2.4.6.7 1.1 1.3 December 199 6
AC CHARACTERISTICS FOR 74HCT GND = V; t r =t f = 6 ns; C =pf T amb ( C) TEST CONDITIONS 21 4 6 ns 4. Fig.6 28 63 7 ns 4. Fig.7 27 63 7 ns 4. Fig.7 18 3 44 3 ns 4. Fig.9 19 3 44 3 ns 4. Fig.9 74HCT SYMBO PARAMETER UNIT V +2 4 to +8 4 to +12 CC (V) WAVEFORMS min. typ. max. min. max. min. max. t PH / t PH propagation delay R A, R B to Q n t PH / t PH propagation delay WE to Q n t PH / t PH propagation delay D n to Q n t PZH / t PZ 3-state output enable time RE to Q n t PHZ / t PZ 3-state output disable time RE to Q n t TH / t TH output transition time 12 1 18 ns 4. Fig.6 t W t su t su t h t h t latch write enable pulse width OW 18 9 23 27 ns 4. set-up time 12 4 1 18 ns 4. D n to WE set-up time 12 2 1 18 ns 4. W A, W B to WE hold time 1 ns 4. D n to WE hold time ns 4. W A, W B to WE latch time 2 11 31 38 ns 4. WE to R A, R B December 199 7
AC WAVEFORMS (1) HC : V M = %; V I = GND to V CC. HCT : V M = 1.3 V; V I = GND to 3 V. (1) HC : V M = %; V I = GND to V CC. HCT : V M = 1.3 V; V I = GND to 3 V. Fig.6 Waveforms showing the read address input (R A, R B ) to output (Q n ) propagation delays and output transition times. Fig.7 Waveforms showing the write enable input (WE) and data input (D n ) to output (Q n ) propagation delays, and the write enable pulse width. (1) HC : V M = %; V I = GND to V CC. HCT : V M = 1.3 V; V I = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance. The time allowed for the internal output of the latch to assume the state of the new data (t latch ) is important only when attempting to read from a location immediately after that location has received new data. This parameter is measured from the falling edge of WE to the rising edge of R A or R B, RE must be OW. Waveforms showing the write address input (W A, W B ) and data input (D n ) to write enable (WE) set-up, hold and latch times. December 199 8
(1) HC : V M = %; V I = GND to V CC. HCT : V M = 1.3 V; V I = GND to 3 V. Fig.9 Waveforms showing the read enable (RE) to output (Q n ) enable and disable times, and the read enable pulse width. PACKAGE OUTINES See 74HC/HCT/HCU/HCMOS ogic Package Outlines. December 199 9