Chapter 11 Inverter DC AC, Switching Ring Oscillator Dynamic Power Dissipation Layout LATCHUP Sizing PASS GATES (CHPT 10) Other Inverters Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 1
Inverter DC DESCRIPTION INPUT A > Vt, THEN OUT=NOT(IN) STATIC POWER ~ 0 VOLTAGE SWING RAIL-TO-RAIL SIZED TO DRIVE LOADS SWITCHING CHAR VARIES BY W/L VOLTAGE TRANSFER CURVES VOH, OUTPUT HIGH VIL DEFINED WHEN SLOPE=-1 VOL, OUTPUT LOW VIH DEFINED WHEN SLOPE=-1 IDEAL VIL=VIH WHY? Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 2
Inverter NOISE, SP DESCRIPTION NOISE MARGIN NMH = VOH VIH NML = VIL VOL SWITCHING POINT BOTH IN SATURATION INPUT=OUTPUT, CURRENTS SAME b N /2 (V SP -V THN ) 2 = b P /2(VDD-V SP -V THP ) 2 V SP = [ SQRT(b N /b P ) V THN + (VDD-V THP ) ] / [1 + SQRT(b N /b P ) ] Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 3
Inverter AC DESCRIPTION CAPS DUE TO OVERLAP, CH, SD WHAT ARE SPIKES DUE TO? I = C dv / dt CLOCK FEEDTHROUGH INTRINSIC DELAY NO EXTERNAL LOAD PROPAGATION DELAY INTRINSIC + EXTRINSIC MEASURE INTRINSIC DELAY? RING OSCILLATOR Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 4
0 Inverter RING OSC DESCRIPTION 1 0 1 0 1 RING OSCILLATOR ODD NUMBER OF STAGES INPUT STAGE N =OUTPUT STAGE N-1 PROCESS CHARACTERIZATION INV FANOUT=1 INV FANOUT=3 METAL1 LOADED METAL2 LOADED NAND NOR WHAT IS THIS DOING? NEED TO TEST ON ALL WAFERS Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 5
Inverter POWER DISSIPATION DESCRIPTION DYNAMIC DYNAMIC DYNAMIC So, in any one period, the total energy dissipated is: The average power is Energy per Unit Time (period): CHARGE, DISCHARGE CAPS I = C V / t P = V I = C V 2 / t = C V 2 f CLK STATIC REVERSE BIAS PN JUNCTION MODEL OF DIODE SHORT CIRCUIT BOTH N AND P ON DURING VSP RELATED TO RISE, FALL TIME Vout Vin PCH NCH Power Dissipation 0 1 off on none 0->1 1->0 off->on on->off PCH charging cap 1 0 on off none 1->0 0->1 on->off off->on NCH discharging cap SHORT CIRCUIT MARTIN Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 6
Inverter LAYOUT, LATCHUP DESCRIPTION WHAT IS COMMON? WHAT IS DIFFERENT? WHAT IS THE IMPACT? LATCHUP BIPOLAR EFFECT IN CMOS FEEDTHROUGH ON C2 Q2 ON, FEEDS Q1 BASE Q1 FEEDBACK TO Q2 BASE THERMAL RUNAWAY ELIMINATE LATCHUP SLOWER RISE TIME REDUCE C1, C2 AREA REDUCE RW1, RS2 MORE TAPS Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 7
Inverter SIZING DESCRIPTION NEED TO DRIVE OUTPUT LOADS WHAT IS DRIVE? I = C dv / dt CURRENT NEEDED TO CHANGE VOLTAGE IN GIVEN TIME TRADEOFFS WHY NOT PUT HUGE W/L? T = 95ps T = 407ps T = 580ps RESISTANCES DECREASE BY A R 2 = R 1 / A R3 = R2/A = R1 /A 2 INPUT, OUTPUT CAP INCR BY A C IN2 =C IN1 * A C IN FINAL = C IN1 AN = C LOAD A = [ C LOAD / C IN1 ] 1/N N = ln [C LOAD / C IN1 ] NMB OF STAGES A IS IDEALLY e EACH INVERTER DRIVES 2.718 INV WIDTHS OF NMOS X 2.718 Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 8
PASS GATES (Chpt. 10) DESCRIPTION NMOS PASSES 0 (source is at gnd) PMOS PASSES 1 (source is at vdd) REASON IS LOCATION OF SOURCE Current only flows if Vgs > Vtn Vg=VDD Vd=VDD Vs=? Vg Vs = Vtn VDD Vs = Vtn, manipulate terms VDD Vtn = Vs, Vs= VDD Vtn DROP A Vt, Source is not at zero Simliar for PMOS, Vs = Vtp (below) Vg=0 Vs=VDD Vsg=VDD Vg=0 Vd=0 Vsg=? Vs Vg = Vtp Vs 0 = Vtp Vs = Vtp Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 9
PASS GATES (Chpt. 10) DESCRIPTION Combine NMOS, PMOS to pass 1/0 If signal is a 1, PMOS passes it If signal is a 0, NMOS passes it Transmission Gates (no drop) Pass Gates (drops Vt) Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 10
Inverter Other Config DESCRIPTION (A) NMOS ONLY AVOIDS LATCHUP, NO PMOS (B), (C) PSUEDO-NMOS USEFUL FOR LARGE NMB INPUTS PMOS AS LOAD TRANSISTOR ASYMMETRIC SWITCHING TRADEOFFS DC CURRENT FLOW WITH LOGIC 1 How to minimize this current? VOL!= GROUND (C) VOH=VDD, OTHERS VDD-Vt BENEFITS LOWER CAP, SINCE NO PMOS REDUCED VOLTAGE SWING LOWER POWER AT HIGH FREQ Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 11
0 off 1 Baker Ch. 11 The Inverter off on on VDD-Vt off Inverter Other Config DESCRIPTION SUPER BUFFER No PMOS, no latchup Reduced voltage swing on off on 0 No direct path to GND IN = L, M1, M4 OFF; M2, M3 ON IN = H, M1, M4 ON; OUT=VDD-Vt DROP A Vt TRI-STATE BUFFER S=H INVERSION, S=L HIGH-Z (A) FASTER, MORE POWER (B) SLOWER, LESS POWER Vdd+Vt Vdd Vdd GND PUMPED VOLTAGE BUFFER GENERATE ON CHIP VDD+VADD NO LOSS OF Vt Joseph A. Elias, Ph.D. Adjunct Professor, University of Kentucky; CAD MTS, Cypress Semiconductor 12