EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 26 Memory References Rabaey, Digital Integrated Circuits Memory Design and Evolution, VLSI Circuits Short Course, 1998.» Gillingham, Evolution of DRAM» Nuhn, Cao, MacGillivray, DRAM Development Trends 1
Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM Memory Timing: Definitions Read Cycle READ Read Access Read Access Write Cycle WRITE Data Valid Write Access DATA Data Written 2
Memory Timing: Approaches MSB LSB Address Bus Row Address Column Address RAS CAS Address Bus Address Address transition initiates memory operation RAS-CAS timing DRAM Timing Multiplexed Adressing SRAM Timing Self-timed Array-Structured Memory Architecture Problem: ASPECT RATIO or HEIGHT >> WIDTH 2 L-K Bit Line Storage Cell AK AK+1 AL-1 Row Decoder Word Line Sense Amplifiers / Drivers M.2 K Amplify swing to rail-to-rail amplitude A0 AK-1 Column Decoder Selects appropriate word Input-Output (M bits) 3
Memory Cells Trends in Memory Capacity 4
Read-Write Memories (RAM) STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended CMOS SRAM Analysis (Write) WL M4 M5 Q = 0 Q = 1 M6 M1 = 1 = 0 k n, M6 ( V Tn ) ----------- V 2 DD V ----------- DD k 2 8 pm4, ( V Tp ) ----------- V 2 = ----------- DD 2 8 (W/L)n,M6 0.33 (W/L)p,M4 k -------------- nm5 V, V 2 DD DD ----------- V 2 2 Tn ----------- 2 k nm1, V V ( Tn ) DD V 2 - ----------- DD 2 8 = (W/L)n,M5 10 (W/L)n,M1 5
CMOS SRAM Analysis (Read) WL M4 M5 Q = 0 Q = 1 M6 M1 C bit C bit k nm5 ---------------, V V DD DD ------------ V 2 2 Tn ------------ 2 2 k nm1, ( V Tn ) = ------------ 2 2 V ------------ DD 8 (W/L)n,M5 10 (W/L)n,M1 (supercedes read constraint) 3-Transistor DRAM Cell 1 2 WWL RWL WWL RWL M1 X M2 M3 X 1 -V T C S 2 -V T V No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL -V Tn 6
1-Transistor DRAM Cell WL WL Write "1" Read "1" M1 C S X GND V T C /2 sensing VDD/2 Write: C S is charged or discharged by asserting WL and. Read: Charge redistribution takes places between bit line and storage capacitance C S V = V V PRE = ( V BIT V PRE )------------------------ C S + C Voltage swing is small; typically around 250 mv. DRAM 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than. 7
1-T DRAM Cell Capacitor Metal word line n + n + poly SiO 2 Field Oxide M1 word line poly Inversion layer induced by plate bias (a) Cross-section Diffused bit line Polysilicon Polysilicon plate gate (b) Layout Used Polysilicon-Diffusion Capacitance Expensive in Area Advanced 1T DRAM Cells Insulating Layer Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Transfer gate Storage electrode Isolation Trench Cell Stacked-capacitor Cell 8
Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder A NAND decoder using 2-input pre-decoders WL 1 WL 0 A0A1 A0A1 A0A1 A0A1 A2A3 A2A3 A2A3 A2A3 A1 A0 A0 A1 A3 A2 A2 A3 Splitting decoder into two or more logic layers produces a faster and cheaper implementation 9
Decoders Word line selection results in only one critical transition Skew the gates sizing Requires resetting for the next transition Precharging Self-resetting; Delayed-resetting Dynamic Decoders Precharge devices GND GND WL 3 WL 3 WL 2 WL 2 WL 1 WL 1 WL 0 WL 0 φ A 0 A 0 A 1 A 1 A 0 A 0 A 1 A 1 φ Dynamic 2-to-4 NOR decoder 2-to-4 MOS dynamic NAND Decoder Propagation delay is primary concern 10
Self-Resetting Decoders Chappell, JSSC 11/91 Self-Resetting Decoders Park, ISSCC 98 4Mb DDR SRAM 11
Source-Coupled Logic Static Dynamic Source-Coupled Nambu, JSSC 11/98 Source-Coupled Logic Conventional Decoder Source-Coupled 12
Sense Amplifiers C V t p = ---------------- I av large Idea: Use Sense Amplifer make V as small as possible small small transition s.a. input output Differential Sensing - SRAM VDD VDD VDD PC VDD y M3 M4 y EQ x M1 M2 SE M5 x x SE x WLi (b) Doubled-ended Current Mirror Amplifier SRAM cell i Diff. x Sense x Amp y y D D x y SE VDD y x (a) SRAM sensing scheme. (c) Cross-Coupled Amplifier 13
Latch-Based Sense Amplifier EQ SE SE Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point. Open Bitline Architecture EQ R L 1 L 0 R 0 R 1 SE L L R C S... C S C S SE... C S C S C S dummy cell dummy cell 14
DRAM Read Process with Dummy Cell 6.0 V (Volt) V (Volt) 4.0 2.0 0.00 1 2 3 4 5 t (nsec) (a) reading a zero 6.0 4.0 2.0 V (Volt) 5.0 4.0 3.0 2.0 1.0 WL SE EQ 0.00 1 2 3 4 5 (c) control signals 0.00 1 2 3 4 5 t (nsec) (b) reading a one Open Bit-line Architecture Cross Coupling EQ WL1 WL0 WLD CW WLD CW WL0 WL1 C Sense C C C C Amplifier C C C 15
Folded-Bitline Architecture WL 1 WL 1 WL 0 WL 0 WL D WL D C W C x y... C C C C C C EQ Sense Amplifier C x y CW Transposed-Bitline Architecture " C cross (a) Straightforward bitline routing. SA " C cross SA (b) Transposed bitline architecture. 16
Alpha Particles α-particle WL n + SiO 2 1 particle ~ 1 million carriers Redundancy Redundant columns Redundant rows Memory Array Row Address Row Decoder Fuse : Bank Column Decoder Column Address 17
Redundancy and Error Correction 18