ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec 12: October 4, 2017 Scaling Penn ESE 370 Fall 2017 - Khanna

Today! VLSI Scaling Trends/Disciplines! Effects! Alternatives (cheating) Penn ESE 370 Fall 2017 - Khanna 2

Scaling! Premise: features scale uniformly " everything gets better in a predictable manner! Parameters: # λ (lambda) -- Mead and Conway (Day14) # F -- Half pitch ITRS (F=2λ) # S scale factor Rabaey # F =S F Penn ESE 370 Fall 2017 - Khanna 3

ITRS Roadmap! International Technology Roadmap for Semiconductors " Try to predict where industry going! ITRS 2.0 started in 2015 with new focus " System Integration, Heterogeneous Integration, Heterogeneous Components, Outside System Connectiviy, More Moore, Beyond CMOS and Factory Integartion.! http://www.itrs2.net/ Penn ESE 370 Fall 2017 - Khanna 4

Microprocessor Trans Count 1971-2015 Curve shows transistor count doubling every two years 80486 Pentium 2-Core Itanium 2 Pentium 4 Pentium III Pentium II AMD K5 16-Core SPARC T3 6-Core i7 i7 AMD K10 AMD K7 AMD K8 10-Core Xenon IBM 4-Core z196 IBM 8-Core POWER7 4-Core Itanium Tukwilla AMD 6-Core Opteron 4-Core i7 2400 80286 Mot 68000 Mot 6800 8080 8006 4004 8086 Zilog Z80 MOS 6502 80386 80186 2015: Oracle SPARC M7, 20 nm CMOS, 32-Core, 10B 3-D FinFET transistors. Kenneth R. Laker, University of Pennsylvania, updated 20Jan15 Penn ESE 370 Fall 2017 - Khanna 2015 5

Trend Minimum Feature Size vs. Year 100 µm 10 µm 1 µm 0.1 µm Process Node/ Minimum Feature 0.18 µm in 1999 Integrated Circuit History ITRS Roadmap 10 nm 1 nm Transition Region Quantum Devices NOT SO Distant Future 0.1 nm Atomic Dimensions 1960 1980 2000 2020 2040 Year Minimum Feature Measure = line/gate conductor width or half-pitch (adjacent 1 st metal layer lines or adjacent transistor gates) Penn ESE 370 Fall 2017 - Khanna 6

Intel Cost Scaling http://www.anandtech.com/show/8367/intels-14nm-technologyin-detail Penn ESE 370 Fall 2017 - Khanna 7

Moore s Law Impact on Intel ucomputers Min Feature Size 2BT µp (Intel Itanium Tukwila) 4-Core chip (65 nm) introduced Q1 2010. 3BT mp (Intel Itanium Poulson) 8-Core chip (32 nm) to be introduced 2012. Serial data links operating at 10 Gbits/sec. Introduces 22 nm Tri-gate Transistor Tech. Increased reuse of logic IP, i.e. designs and cores. Complexity - # transistors Double every Two Years Penn ESE 370 Fall 2017 - Khanna 0.032um 2009 0.022um 2011 2010 YEAR 8

More Moore $ Scaling! Geometrical Scaling " continued shrinking of horizontal and vertical physical feature sizes! Equivalent Scaling " 3-dimensional device structure improvements and new materials that affect the electrical performance of the chip even if no geometrical scaling! Design Equivalent Scaling " design technologies that enable high performance, low power, high reliability, low cost, and high design productivity even if neither geometrical nor equivalent scaling can be used Penn ESE 370 Fall 2017 - Khanna 9

22nm 3D FinFET Transistor High-k gate dielectric Tri-Gate transistors with multiple fins connected together increases total drive strength for higher performance http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-details_presentation.pdf Penn ESE 370 Fall 2017 - Khanna 10

Scaling More-than-Moore More-than-Moore, International Road Map (IRC) White Paper, 2011. International Technology Road Map for Semiconductors Penn ESE 370 Fall 2017 - Khanna 11

Semiconductor System Integration More Than Moore's Law 10 10 10 10 Transistors/cm 2 10 9 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 SOP law for system integration. As components shrink and boards all but disappear, component density will double every year or so. Multichip Module Systemin-package (SIP) 10 9 10 8 10 7 10 6 10 5 10 4 System- 10 3 on-package (SOP) 10 2 10 Components/cm 2 1970 1980 1990 2000 2010 2020 R. Tummala, Moore's Law Meets Its Match, IEEE Spectrum, June, 2006 Penn ESE 370 Fall 2017 - Khanna 12

Improvement Trends for VLSI SoCs Enabled by Geometrical and Equivalent Scaling! TRENDS:! Higher Integration level " exponentially increased number of components/ transistors per chip/package.! Performance Scaling " combination of Geometrical (shrinking of dimensions) and Equivalent (innovation) Scaling.! System implementation " SoC + increased use of SiP - > SOP! CONSEQUENCES:! Higher Speed " CPU clock rate at multiple GHz + parallel processing.! Increased Compactness & less weight " increasing system integration.! Lower Power " Decreasing energy requirement per function.! Lower Cost " Decreasing cost per function. Penn ESE 370 Fall 2017 - Khanna 13

Societal Needs Penn ESE 370 Fall 2017 - Khanna 14

More Moore $ Scaling! Examples: " Design-for-variability " Low power design (sleep modes, clock gating, multi- Vdd, etc.) " Multi-core SOC architectures Penn ESE 370 Fall 2017 - Khanna 15

Preclass 1! Scaling from 32nm $ 22nm? " Scaling minimum gate length " And pitch distance Penn ESE 370 Fall 2017 - Khanna 16

Half Pitch (= Pitch/2) Definition Metal Pitch Poly Pitch (Typical DRAM) (Typical MPU/ASIC) Source: 2001 ITRS - Exec. Summary, ORTC Figure, Andrew Kahng Penn ESE 370 Fall 2017 - Khanna 17

MOS Transistor Scaling - (1974 to present) S=0.7 per technology node [0.5x per 2 nodes] Pitch Gate Source: 2001 ITRS - Exec. Summary, ORTC Figure, Andrew Kahng Penn ESE 370 Fall 2017 - Khanna 18

Scaling Calculator Node Cycle Time: 0.7x 0.7x 250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16 0.5x N N+1 N+2 Log Half-Pitch 1994 NTRS -.7x/ 3yrs Actual -.7x/2yrs Linear Time Source: 2001 ITRS - Exec. Summary, ORTC Penn ESE 370 Fall 2017 - Khanna Figure, Andrew Kahng 19

Scaling! Channel Length (L)! Channel Width (W)! Oxide Thickness (T ox )! Doping (N a )! Voltage (V) Penn ESE 370 Fall 2017 - Khanna 20

Full Scaling (Ideal Scaling)! Channel Length (L) S! Channel Width (W) S! Oxide Thickness (T ox ) S! Doping (N a ) 1/S! Voltage (V) S Penn ESE 370 Fall 2017 - Khanna 21

Effects on Physical Properties and Specs?! Area! Capacitance! Resistance! Threshold (V th )! Current (I d )! Gate Delay (τ gd )! Wire Delay (τ wire )! Power Penn ESE 370 Fall 2017 - Khanna 22

Area! λ % λs! Area impact?! Α = L W! Α % ΑS 2! 32nm % 22nm! 50% area! 2 transistor capacity for same area L S=0.7 W Penn ESE 370 Fall 2017 - Khanna 23

Capacitance! Capacitance per unit area scaling? " C ox = ε SiO 2 /T ox " T ox % S T ox " C ox % C ox /S S=0.7 Penn ESE 370 Fall 2017 - Khanna 24

Capacitance! Gate Capacitance scaling? # C gate = A C ox # Α % Α S 2 # C ox % C ox /S # C gate % S C gate Penn ESE 370 Fall 2017 - Khanna 25

Resistance! Resistance scaling?! R=ρL/(W*t)! W$ S W! L, t remain similar (not scaled)! R $ R/S Penn ESE 370 Fall 2017 - Khanna 26

Threshold Voltage! V TH % S V TH Penn ESE 370 Fall 2017 - Khanna 27

Current! Which Voltages matters here? (V gs,v ds,v th )! Transistor charging looks like voltage-controlled current source! Saturation Current scaling? I d =(µc OX /2)(W/L)(V gs -V TH ) 2 V gs =V$ S V V TH $ S V TH W$ S W L$ S L C ox $ C ox /S Penn ESE 370 Fall 2017 - Khanna 28

Current! Velocity Saturation Current scaling? V gs =V$ S V V TH $ S V TH L$ S L W$ S W C ox $ C ox /S Penn ESE 370 Fall 2017 - Khanna 31

Current! Velocity Saturation Current scaling? V gs =V$ S V V TH $ S V TH L$ S L W$ S W C ox $ C ox /S V DSAT Lν sat µ n V DSAT $ S V DSAT Penn ESE 370 Fall 2017 - Khanna 32

Current! Velocity Saturation Current scaling? V gs =V$ S V V TH $ S V TH L$ S L W$ S W C ox $ C ox /S V DSAT Lν sat µ n % I DS ν sat C OX W V GS V TH V DSAT ' & 2 ( * ) V DSAT $ S V DSAT I d $ S I d Penn ESE 370 Fall 2017 - Khanna 33

Gate Delay # Gate Delay scaling? # τ gd =Q/I=(CV)/I # V$ S V Note: I ds modeled as current source; V is changing with scale factor # I d $ S I d # C $ S C Penn ESE 370 Fall 2017 - Khanna 34

Gate Delay # Gate Delay scaling? # τ gd =Q/I=(CV)/I # V$ S V Note: I ds modeled as current source; V is changing with scale factor # I d $ S I d # C $ S C # τ gd $ S τ gd Penn ESE 370 Fall 2017 - Khanna 35

Wire Delay # Wire delay scaling? # τ wire =R C # R $ R/S! assuming (logical) wire lengths remain constant... # C $ S C # τ wire $ τ wire Penn ESE 370 Fall 2017 - Khanna 36

Power Dissipation (Dynamic)! Capacitive (Dis)charging scaling?! P=(1/2)CV 2 f! V$ S V! C $ S C! P$ S 3 P Penn ESE 370 Fall 2017 - Khanna 37

Power Dissipation (Dynamic)! Capacitive (Dis)charging scaling?! P=(1/2)CV 2 f! Increase Frequency?! V$ S V! C $ S C! P$ S 3 P! τ gd $ S τ gd! So: f $ f/s! P $ S 2 P Penn ESE 370 Fall 2017 - Khanna 38

Effects?! Area S 2! Capacitance S! Resistance 1/S! Threshold (V th ) S! Current (I d ) S! Gate Delay (τ gd ) S! Wire Delay (τ wire ) 1 S=0.7! Power S 3, S 2 (w/ freq scaling) Penn ESE 370 Fall 2017 - Khanna 39

Power Density! P% S 2 P (increased frequency)! P% S 3 P (same frequency)! A % S 2 A! Power Density: P/A two cases? " P/A % P/A increase freq. " P/A % S P/A same freq. Penn ESE 370 Fall 2017 - Khanna 40

Cheating! Don t like some of the implications! High resistance wires! Higher capacitance! Atomic-scale dimensions!. Quantum tunneling! Need for more wiring! Not scale speed fast enough Penn ESE 370 Fall 2017 - Khanna 41

Improving Resistance! R=ρL/(W t)! W$ S W! L, t similar! R $ R/S Penn ESE 370 Fall 2017 - Khanna 42

Improving Resistance! R=ρL/(W t)! W$ S W! L, t similar! R $ R/S What might we do? Didn t scale t quite as fast $ now taller than wide. Decrease ρ (copper) introduced 1997 http://www.ibm.com/ibm100/us/en/icons/copperchip/ Penn ESE 370 Fall 2017 - Khanna 43

Capacitance and Leakage! Capacitance per unit area " C ox = ε SiO 2 /T ox " T ox % S T ox " C ox % C ox /S What s wrong with t ox = 1.2nm? source: Borkar/Micro 2004 Penn ESE 370 Fall 2017 - Khanna 44

Capacitance and Leakage! Capacitance per unit area " C ox = ε SiO 2 /T ox " T ox % S T ox " C ox % C ox /S What might we do? Reduce dielectric constant, ε, and increase thickness to mimic t ox scaling. Penn ESE 370 Fall 2017 - Khanna 45

ITRS 2009 Table PIDS3B Low Operating Power Technology Requirements Grey cells delineate one of two time periods: either before initial production ramp has started for ultrathin body fully depleted (UTB FD) SOI or multi-gate (MG) MOSFETs, or beyond when planar bulk or UTB FD MOSFETs have reached the limits of practical scaling (see the text and the table notes for further discussion). Year of Production MPU/ASIC Metal 1 (M1) ½ Pitch (nm) 2009 2010 2011 2012 2013 2014 2017 2017 2017 2018 2019 2020 2021 2022 2023 2024 (contacted) Lg: Physical Lgate for High Performance 54 45 38 32 27 24 21 18.9 16.9 15 13.4 11.9 10.6 9.5 8.4 7.5 logic (nm) 29 27 24 22 20 18 17 15.3 14 12.8 11.7 10.7 9.7 8.9 8.1 7.4 L g : Physical Lgate for Low OperatingPower (LOP) logic (nm) [1] 32 29 27 24 22 18 17 15.3 14 12.8 11.7 10.7 9.7 8.9 8.1 7.4 EOT: Equivalent Oxide Thickness (nm) [2] Extended planar bulk 1 0.9 0.9 0.85 0.8 UTB FD 0.9 0.85 0.8 0.75 0.7 MG 0.8 0.8 0.75 0.73 0.7 0.7 0.65 0.65 0.6 0.6 Gate poly depletion (nm) [3] Bulk 0.27 0.27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Channel doping (E18 /cm3) [4] Extended Planar Bulk 3 3.7 4.5 5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 Junction depth or body Thickness (nm) [5] Extended Planar Bulk (junction) 14 13 11.5 10 9 UTB FD (body) 7 6.2 6 5.1 4.7 MG (body) 8 7.6 7 6.4 5.8 5.4 4.8 4.4 4.2 4 EOT elec : Electrical Equivalent Oxide Thickness (nm) [6] Extended Planar Bulk 1.64 1.53 1.23 1.18 1.14 UTB FD 1.3 1.25 1.2 1.15 1.1 MG 1.2 1.2 1.15 1.13 1.1 1.1 1.05 1.05 1 1 Penn ESE 370 Fall 2017 - Khanna 46

High-K dielectric Survey Wong/IBM J. of R&D, V46N2/3P133 168, 2002 Penn ESE 370 Fall 2017 - Khanna 47

Intel NYT Announcement! Intel Says Chips Will Run Faster, Using Less Power " NYT 1/27/07, John Markov " Claim: most significant change in the materials used to manufacture silicon chips since Intel pioneered the modern integratedcircuit transistor more than four decades ago " Intel s advance was in part in finding a new insulator composed of an alloy of hafnium will replace the use of silicon dioxide. Penn ESE 370 Fall 2017 - Khanna 48

Wire Layers = More Wiring Penn ESE 370 Fall 2017 - Khanna 49

Gate Delay # τ gd =Q/I=(CV)/I # V$ S V # I d =(µc OX /2)(W/L)(V gs -V TH ) 2 How might we accelerate? # I d $ S I d # C $ S C # τ gd $ S τ gd Penn ESE 370 Fall 2017 - Khanna 50

Improving Gate Delay More # τ gd =Q/I=(CV)/I # V$ V # I d =(µc OX /2S)(SW/SL)(V gs -V TH ) 2 # I d $ I d /S How might we accelerate? Don t scale V! # C $ S C # τ gd $ S 2 τ gd Penn ESE 370 Fall 2017 - Khanna 51

But Power Dissipation (Dynamic)! Capacitive (Dis)charging # P=(1/2)CV 2 f # V$ V # C $ S C # P$ S P Penn ESE 370 Fall 2017 - Khanna 52

But Power Dissipation (Dynamic)! Capacitive (Dis)charging # P=(1/2)CV 2 f # V$ V # C $ S C! Increase Frequency? # f $ f/s 2 # P $ P/S # P$ S P If don t scale V, power dissipation doesn t scale down! Penn ESE 370 Fall 2017 - Khanna 53

And Power Density! P$ P/S (increase frequency)! Α $ S 2 Α! What happens to power density? Penn ESE 370 Fall 2017 - Khanna 54

And Power Density! P$ P/S (increase frequency)! Α $ S 2 Α! What happens to power density?! P/A $ (1/S 3 )P! Power Density Increases this is where some companies have gotten into trouble Penn ESE 370 Fall 2017 - Khanna 55

Historical Voltage Scaling http://software.intel.com/en-us/articles/gigascale-integration-challenges-and-opportunities/! Frequency impact?! Power Density impact? Penn ESE 370 Fall 2017 - Khanna 56

Scale V separately with Factor U! τ gd =Q/I=(CV)/I! V$U V Penn ESE 370 Fall 2017 - Khanna 57

Scale V separately with Factor U! τ gd =Q/I=(CV)/I! V$U V! I d =(µc OX /2S)(SW/SL)(UV gs -UV TH ) 2! I d $ U 2 /S I d! C $ S C Penn ESE 370 Fall 2017 - Khanna 58

Scale V separately with Factor U! τ gd =Q/I=(CV)/I! V$U V! I d =(µc OX /2S)(SW/SL)(UV gs -UV TH ) 2! I d $ U 2 /S I d! C $ S C! τ gd $ (SU/(U 2 /S)) τ gd! τ gd $ (S 2 /U) τ gd Penn ESE 370 Fall 2017 - Khanna 59

Scale V separately with Factor U! τ gd =Q/I=(CV)/I! V$U V! I d =(µc OX /2S)(SW/SL)(UV gs -UV TH ) 2! I d $ U 2 /S I d Ideal scale factors: S=1/100 U=1/100 τ=1/100 f ideal =100! C $ S C! τ gd $ (SU/(U 2 /S)) τ gd! τ gd $ (S 2 /U) τ gd! f $ (U/S2 ) f Penn ESE 370 Fall 2017 - Khanna 60

Scale V separately with Factor U! τ gd =Q/I=(CV)/I! V$U V! I d =(µc OX /2S)(SW/SL)(UV gs -UV TH ) 2! I d $ U 2 /S I d! C $ S C! τ gd $ (SU/(U 2 /S)) τ gd! τ gd $ (S 2 /U) τ gd Ideal scale factors: S=1/100 U=1/100 τ=1/100 f ideal =100 Cheating factors: S=1/100 U=1/10! f $ (U/S2 ) f How much faster are gates? Penn ESE 370 Fall 2017 - Khanna 62

Scale V separately with Factor U! τ gd =Q/I=(CV)/I! V$U V! I d =(µc OX /2S)(SW/SL)(UV gs -UV TH ) 2! I d $ U 2 /S I d! C $ S C! τ gd $ (SU/(U 2 /S)) τ gd! τ gd $ (S 2 /U) τ gd! f $ (U/S2 ) f f cheat /f ideal =10 Ideal scale factors: S=1/100 U=1/100 τ=1/100 f ideal =100 Cheating factors: S=1/100 U=1/10 τ=1/1000 f cheat =1000 Penn ESE 370 Fall 2017 - Khanna 63

Power Density Impact! P = 1/2CV 2 f! P $ S U 2 (U/S 2 ) = U 3 /S! P/A = (U 3 /S) / S 2 = U 3 /S 3 Penn ESE 370 Fall 2017 - Khanna 64

Power Density Impact! P = 1/2CV 2 f! P $ S U 2 (U/S 2 ) = U 3 /S! P/A = (U 3 /S) / S 2 = U 3 /S 3! U=1/10 S=1/100! P/A $ 1000 (P/A) Penn ESE 370 Fall 2017 - Khanna 65

Power Density Impact! P = 1/2CV 2 f! P $ S U 2 (U/S 2 ) = U 3 /S! P/A = (U 3 /S) / S 2 = U 3 /S 3! U=1/10 S=1/100! P/A $ 1000 (P/A)! Compare with ideal scaling:! P/A $ (1/S 3 )P (ideal scaling)! P/A $ 1,000,000 (P/A) (ideal scaling) Penn ESE 370 Fall 2017 - Khanna 66

uproc Clock Frequency MHz The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011 Penn ESE 370 Fall 2017 - Khanna http://www.nap.edu/catalog.php?record_id=12980 67

up Power Density Watts The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011 Penn ESE 370 Fall 2017 - Khanna http://www.nap.edu/catalog.php?record_id=12980 68

Conventional Scaling! Ends in your lifetime! Perhaps already: " "Basically, this is the end of scaling. " May 2005, Bernard Meyerson, V.P. and chief technologist for IBM's systems and technology group Penn ESE 370 Fall 2017 - Khanna 69

ITRS 2.0 Report 2015! After 2021, the report forecasts, it will no longer be economically desirable for companies to continue traditional transistor miniaturization in microprocessors. Penn ESE 370 Fall 2017 - Khanna 70

BUT Source:https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/09/mark-bohr-on-continuing-moores-law.pdf Penn ESE 370 Fall 2017 - Khanna 71

BUT Source:https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/09/mark-bohr-on-continuing-moores-law.pdf Penn ESE 370 Fall 2017 - Khanna 72

Big Ideas! Moderately predictable VLSI Scaling " unprecedented capacities/capability growth for engineered systems " change " be prepared to exploit " account for in comparing across time " but not for much longer Penn ESE 370 Fall 2017 - Khanna 73

Admin! HW5 " More transistor practice " Hard prepares you for design project 1 " Due Wednesday! Midterm " Grades and solutions posted " Pick up from me after class Penn ESE 370 Fall 2017 - Khanna 74