Dsign Optimiztion Bs on Dignosis Thniqus Anrs Vnris Mgy S. Air Irhim N. Hjj Univrsity of Toronto Motorol Univrsity of Illinois ECE Dprtmnt 77 W. Prmr ECE Dprtmnt n CSL Toronto, ON M5S 34 Austin, T 78729 Urn, IL 6181 vnris@g.toronto.u m.ir@motorol.om hjj@uivlsi.sl.uiu.u Astrt Logi optimiztion is th stp of th VLSI sign yl whr th signr prforms moifitions on th sign otin to stisfy iffrnt onstrints suh s r, powr or ly. In this ppr w propos novl ATPs optimiztion mthoology tht orrows from prvious sign rror ignosis n orrtion thniqus. W lso prsnt xmpls n xprimnts tht init tht our pproh hs itionl potntil whn ompr to prvious ATP/simultion-s optimiztion mthos. 1 Logi Dsign Optimiztion Th sign of igitl iruits usully strts with hviorl sription (spifition) o in som high lvl sription lngug. At som point of th sign yl, logi synthsis is rri out to otin multilvl implmnttion (ntlist) using lls (gts) from som thnology lirry. As nxt stp, logi optimiztion is usully prform, whr th ojtiv is to moify th ntlist to hiv iffrnt onstrints suh s minimiz th r, ru powr onsumption, stisfy timing onstrints, ru swithing nois or improv th tstility of th finl iruit. Rntly, ATP/simultion-s optimiztion thniqus [6] [7] [8] [9] [1] [11] [16] hv gin inrsing populrity. Thir min strngth, ompr to forml Booln funtion (i.. symoli) [4] s optimiztion mthos, lis in thir flxiility sin thy r mmory ffiint, thy hv goo filur hrtristis n lthough, thortilly, thy n xponntil in tim, in prti this is rrly th s. In this rsrh w propos nw pproh to ATP-s sign optimiztion. Th propos pproh orrows from our prvious fforts on Dsign Error Dignosis n Corrtion (DEDC) n it provis mor powrful rout to ATP-s optimiztion. To illustrt th ntrl points of th propos rsrh w n to tk losr viw on xisting ATP-s optimiztion thniqus n th prolm of DEDC. This is th topi of stions 2 n 3, rsptivly. In stion 4 w xmin th rltionship of ths two prolms n prsnt our mtho. Stion 5 ontins th xprimntl rsults n stion 6 onlus this ppr. 2 Dsign Optimiztion Vi Rwiring ATP-s sign optimiztion thniqus r usully s on sign rwiring s thy try to optimiz givn ntlist with squn of simpl logi trnsformtions suh s ing/lting singl wir, gt..., t. A signifint mount of optimiztion through rwiring is prform through runny ition n rmovl [6] [7] [8] [9] [1] [16]. Ths mthos trgt wir tht violts rtin spifition onstrints n ttmpt to rmov it y ithr ing runnt logi (so tht th trgt wir oms itslf runnt), or y loking ll possil snsitiz pths tht xist from th trgt wir to primry outputs. Th following xmpl, tkn from [9], outlins th mjor stps of th singl wir runny ition/rmovl sign optimiztion mtho. Exmpl: Consir th simpl iruit in Figur 1() whr wir g5 g9, init y ott lin, is not prt of th originl ntlist. Also ssum tht wir w T = g1 g4, nm trgt wir hrftr, ns to rmov us it violts som spifition onstrint(s). In runny ition/rmovl, th trgt wir w T is rmov without ltring th funtion(s) implmnt t th primry output(s) y ing nw runnt onntion tht mks w T runnt. Suh
runnt onntion is wir w R = g5 g9, shown s ott lin. Unr th prsns of w R, wir w T oms runnt n nw runnis r introu in th iruit suh s wir g 6 g 7. As nxt stp, w R is n runnis w T n g 6 g 7 r rmov s wll s logi tht no longr hs n influn on th primry outputs suh s gts g 6 n g 4, wir g 4 g 8, t. Th nw, simplifi, iruit is shown in Figur 1() whr wir w T hs n rmov n th gt ount hs n ru ling to n optimiz sign. f f g1 g2 g3 g1 g2 g3 g4 g5 g6 () g5 () Trgt Wir g8 g7 g9 g8 O1 O2 Figur 1: Optimiztion through rwiring 3 Dsign Error Dignosis n Corrtion Logi sign rrors my our uring th sign yl of VLSI hip whn th signr hs to just mnully th ntlists gnrt y synthsis tools in orr to stisfy spifi sign gols. Dsign rrors r funtionl mismths twn th spifition n th gt lvl sription. Exprimntl t hs shown tht th ntur of th sign rrors usully involvs th funtionl mishvior of som gt lmnt(s) n/or som intronntion rror(s). Th vrg numr of sign rrors is 2. Most of th litrtur, inluing our work in th fil [12] [13], uss sign rror (orrtion) mol, i.. smll prtrmin st of possil rror typs, propos y Air t l. [1]. This mol ontins tn iffrnt typs of possil sign rrors suh s missing invrtr, xtr invrtr, gt rplmnt, xtr gt, g9 O1 O2 xtr input wir, missing input wir,... t. For xmpl, rmoving w T from th iruit in Figur 1() givs missing input wir sign rror. DEDC is th prolm whr givn n rronous sign n spifition w n to intify lins in th sign tht r potntil sours of rror (ignosis) n suggst pproprit moifitions, from th sign rror mol, tht rtify it (orrtion). In [12] [13] w prsnt run-tim ffiint mtho for multipl DEDC. Th input to th lgorithm is n rronous sign n its spifition. Th output of th lgorithm is list of ll pplil orrtions tht rtify th sign from th sign rror mol n th tst vtor st tht it is us. Sin thr my mor thn on wy to synthsiz prtiulr funtion, thr my quivlnt orrtions, long with th tul on, tht rtify th sign. Th xistn of quivlnt orrtions is of prmount importn for th potntil of th propos optimiztion mtho. With rspt to th xmpl in Figur 1(), rmoving trgt wir w T n running th DEDC lgorithm sri in [12] [13], it rturns onntion g 5 g 9, mong othrs, in th list of quivlnt orrtions. 3.1 Th Signl Error Cs In this sustion w rviw our DEDC [12] [13] mthoology for singl sign rrors s it will us for th optimiztion pross sri in stion 4. Dignosis uss th pth tr prour, lin mrking lgorithm vlop for fult ignosis y Vnktrmn t l. [14] [15] tht is s on th ritil pth tring lgorithm [2]. In til, lt iruit C orrupt with sign rror n input tst vtor v with filing primry output rspons(s) for C. Pth tr [14] [15] strts from n rronous primry output n trs kwrs towr th primry inputs mrking lins s follows: if th output of gt hs n mrk n hs on or mor fn in(s) with ontrolling vlus thn th prour rnomly mrks ny on ontrolling fn in; if hs ll fn ins with non ontrolling inputs, thn ll fn ins r mrk; if rnh is mrk, thn th lgorithm utomtilly mrks th stm of th rnh. For xmpl, onsir th iruit of Fig. 2 with primry outputs O 1 n O 2. If O 1 hs n mrk y pth tr, it n pro y mrking st of lins S 1 = {O 1, 4, 3, B 1, I 2 }. If pth tr gins from O 2, st of lins S 2 = {O 2, B 4, 2, B 2, I 2 } r mrk. It n shown [12] [13], tht givn n rronous iruit C n st of input tst vtors v 1, v 2,..., v k h of thm filing primry output rsponss for C, vry lin tht my ontin sign rror is gurnt to in th intrstion of th lins mrk y istint pth-tr runs for iffrnt rronous primry outputs
1 I1 3 I2 I3 1 B1 B2 2 B3 B4 4 O1 Figur 2: Singl sign rror ignosis n orrtion n vtors v j, j = 1,..., k. Agin, onsir th iruit of Fig. 2 n ssum tht thr is n invrtr missing on lin I 2. In suh s, input vtor (1,, 1) prous rronous rsponss t oth primry outputs O 1 n O 2 n vry lin with sign rror longs in th intrstion of th st of lins S 1 n S 2 mrk y pth tr, nmly S 1 S2 = {I 2 }. To ompil list of nit rror sits uring ignosis, w simply run pth-tr for th vtors v 1, v 2,..., v k n iffrnt filing primry outputs n w rturn th intrstion of th lins mrk t vry istint run of th prour. For rror orrtion, th lgorithm xhustivly ompils list of ll possil orrtions for vry nit tht qulifi ignosis. In til, for vry nit rror lin l it pplis ll moifitions of th mol of Air t l. [1], on t tim, on th gt riving l n kps th orrtion if n only if it givs omplmnt logi vlus for vry vtor v j, j = 1,..., k t th output of th gt. 4 Dsign Optimiztion Bs on Dignosis Thniqus A losr viw of th two prolms sri ov shows tht th prour of rwiring n viw from DEDC prsptiv s follows. Suppos tht trgt wir w T ns to rmov. Inst of ttmpting to fin runnt onntion tht mks w T runnt, w n tully rmov th trgt wir n rtifiilly introu sign rror. Unlik DEDC whr th lotion of th sign rror is unknown n tst vtor gnrtion (in th gnrl s) is iffiult prolm [1] [3] [13], in th sitution sri ov, th lotion of th rror is known n w n riv input tst vtors with PODEM-lik prour [5] to tt it. Ths vtors n us to run DEDC lgorithm n otin st of orrtions tht rtify th sign. Susquntly, th lgorithm slts n pproprit orrtion tht stisfis th optimiztion ritri from th list of quivlnt orrtions n simultion-s vrifition of th finl O2 sign is prform. It shoul not tht in th DEDC ontxt, vrifition, long with tst vtor gnrtion, of th finl sign with th us of tst vtor simultion is hr prolm [1] [3] [13]. In til, it is thortilly [1] n xprimntlly [3] [13] provn tht unlss xhustiv tst vtor simultion is prform, whih is prtilly unrlisti for most ommril signs, logi vrifir is rquir t th k-n of DEDC mtho to gurnt th qulity of th propos orrtions. Howvr, this is not prtil for DEDCs optimiztion lgorithm tht itrts for signifintly lrg numr of trgt logi n forml vrifir t th k-n of h itrtion will gr th ovrll prformn signifintly. To llvit this prolm w vlop run-tim/mmory ffiint ATP-s thniqus tht gurnt th orrtnss of th finl sign. Ths thniqus r sri in sustion 4.1. In sns, th optimiztion prour sri ov (rmov/ logi) works in th opposit irtion from wht xisting ATP/simultion-s optimiztion thniqus o (/rmov logi). Howvr, whn oprting in this nw irtion, our pproh hs th potntil to l to grtr optimiztion gins sin, s illustrt in th xmpl of sustion 4.2, it n rturn logi trnsformtions ( orrtions ) tht r not nssrily runnt in th prsns of th trgt wir ( sign rror ) w T. 4.1 Mtho Ovrviw Th propos optimiztion mtho ompriss of four min stps: (1) introu sign rror y rmoving th trgt logi, (2) riv tst vtors for this sign rror, (3) us DEDC lgorithm to srh for orrtion tht rtifis th sign, n (4) vrify th orrtnss of th finl sign. All four stps r s on th rsults of n ATP-lik lgorithm. In th prgrphs tht follow w isuss th implmnttion of th iffrnt stps of our mtho. During this isussion, w ssum tht non-runnt trgt wir w T is fn-in to gt T n T is th nm of tht gt whn w T is rmov. W lso ssum tht A is gt whr w n fn-in wir w A, rsulting in gt A. As xplin rlir, th first stp of th lgorithm rtifiilly introus sign rror in th iruit y rmoving trgt wir w T. Nxt, 2-input multiplxr is in th iruit with fn-ins th outputs of gts T n T. To riv vtors tht tt th sign rror w run PODEM-lik [5] prour for S stukt 1 or, whr S is th slt lin of th multiplxr. Eh of th vtors rturn y th ATP lgorithm will lso vtor tht istinguishs twn th ol (orrt) n nw (rronous) iruit.
To implmnt th thir stp of our mtho w run th simultion-s DEDC lgorithm outlin in sustion 3.1. Th input to this lgorithm is th orrt n rronous iruit long with th tst vtors riv in stp (2). Th output of this lgorithm is list of ll (tul n quivlnt) orrtions tht rtify th sign for ll th tst vtors rturn y th ATP tool. Missing input wir w A is ontin in this list of quivlnt orrtions. 3 4 () 1 3 1 3 2 4 1 2 () () () S M U 2 S M U S M U 1 2 () Figur 3: A Ciruit with OR gts () Originl Dsign () Driving Tst Vtors () Ciruit Corrtnss () Finl Dsign () Inorrt Dsign As lst stp, w n to vrify th orrtnss of th finl sign whn w A is n w T is rmov. To prform this vrifition stp, w tth son 2-input multiplxr to th fn-outs of A n A with th sm slt lin S n run th PODEM-lik [5] prour for S stuk-t 1 or. It is lr tht if th prour rturns with non-mpty tst-vtor st it inits tht th nw iruit (w T rmov, w A ) is inorrt. Howvr, if th prour rturns with filur, i.. nnot fin vtors for th stuk-t fult, thn w gurnt th orrtnss of th nw sign. 4.2 Exmpl In this stion w giv n xmpl to illustrt th stps of th lgorithm sri in sustion 4.1. This xmpl lso inits th potntil of our pproh ompr to prvious runny ition/rmovl logi optimiztion mthos. With rspt to th iruit in Fig. 3() ssum tht w T =, tht is, fn-in of gt T = 1, ns to rmov. During first two stps of th lgorithm, gt T = 3 is introu whr w T is rmov long with multiplxr MU tht fn-ins th outputs of 1 n 3 n hs slt lin S, s shown in Fig. 3(). As xplin in th prvious sustion, input tst vtors tht tt th fult S stuk-t 1 or r lso vtors tht giv rronous primry output rsponss whn w T is rmov from th iruit in Fig. 3(). Without loss of gnrlity, w ssum tht th ATP tool rturns with vtor V = (,,,, ) = (1, v, v, v, v), whr v inits som wll-fin vlu ( or 1). During th thir stp of our lgorithm, DEDC [12] [13] is prform. Th input to th DEDC lgorithm is th originl iruit (Fig. 3()), th rronous on (Fig. 3() with w T rmov) n vtor st V. Th DEDC lgorithm rturns with th tul rror (missing input wir to 1 ) n quivlnt orrtion missing input wir w A = fn-in to 2. To vrify th orrtnss of th finl sign whn trgt logi w T is rmov n th quivlnt orrtion is ppli, stp (4) rquirs th ition of gt 4 n son multiplxr with th sm slt lin S s th first on tht fn-ins 2 n 4, s shown in Fig. 3(). A PODEM-lik [5] prour for fult S stuk-t 1 or rturns with filur, initing tht th fult is runnt. Thrfor, th iruits in Fig. 3() n Fig. 3() implmnt th sm funtion t th primry output n th orrtion qulifis. Not, tht th solution rturn y th propos mtho nnot foun y runny ition/rmovl optimiztion prour, s monstrt in Fig. 3(). It is lr tht wir w A is not runnt in prsns of w T n our solution woul
Tl 1: Exprimntl Rsults kt # of primry # of # w A # w A suss mx. # of vrg nm inputs/outputs lins sm gt iff. gt rtio w A rturn CPU tim C432 36/7 545 8.4 1. 1 % 31 5.7 C88 6/26 88 1.3 2. 85 % 9 7.9 C499 41/32 1224. 4.8 4 % 15 1.7 C1355 41/32 1355.6 5. 4 % 12 14.2 C198 33/25 198 3.4 4.5 9 % 1 19.4 C267 157/63 267 4.6 26.3 8 % 192 17.3 C5315 178/123 5315 3.3 2.8 45 % 14 21.9 C7522 27/18 7552 4.5 1.6 7 % 9 35.1 not onsir y xisting singl runny ition/rmovl mthos. 5 Exprimnts W implmnt our lgorithm in C lngug n rn it on n Ultr 5 Spr worksttion for th ISCAS 85 nhmrk iruits. W rn 2 xprimnts for h iruit. During h xprimnt w rnomly pik n lt n input wir to gt n w ount th numr of ltrnt wirs tht n orrt th sign. In th s tht th gt originlly h 2 fn-ins w rpl th AND/OR (NAND/NOR) gt with BUFFER (NOT). Th vrg vlus of th rsults of our xprimnts r rport in Tl 1. All run tims r in sons. Th first thr olumns of Tl 1 ontin iruit hrtristis, i.. th nm, numr of primry inputs/outputs n th numr of intrnl lins for h iruit. In h of our xprimnts, w first rnomly pik th trgt wir w T whih is fn-in to gt T n run th lgorithm sri in sustion 4.1 to fin ltrnt wirs w A tht n fn-in to gt A n orrt th sign. In th ontxt of DEDC [12, 13], w rnomly slt n lt wir, introuing sign rror in th sign, n thn w ttmpt to fin quivlnt missing input wir orrtions. W ivi th orrtions w fin in two istint fmilis, th ons tht fn-in to th originl gt ( T = A ) n th ons tht fn-in to iffrnt gt ( T A ). Th vrg numr of wirs tht fn-in to th sm gt n foun in olumn 4 of Tl 1 whil th vrg numr of wirs tht fn-in to iffrnt gt is ontin in olumn 5. Ths numrs r th vrg vlus ovr th numr xprimnts whr our lgorithm rturn with non-mpty numr of quivlnt orrtions (lq 2). Th numr of tims tht our pproh oul not fin ltrnt wirs to orrt th sign is ontin in olumn 6. It is mong our futur rsrh plns to vlop fmily of mor omplx logi trnsformtions, suh s ing multipl input wirs n/or gts, to prform orrtion whn singl wir ition is not suffiint to rtify th sign. In olumn 7 w prsnt th mximum numr of ltrnt wirs tht our pproh rturn throughout ths 2 xprimnts for h iruit n th lst olumn ontins th ovrll run tim to fin ll quivlnt orrtions. 6 Conlusions W prsnt novl ATP-s logi optimiztion mthoology. Our mthoology trgts wir tht violts som optimiztion onstrints n ttmpts to fin ltrnt onntions with th us of xisting sign rror ignosis n orrtion prours. W lso propos ffiint thniqus to gurnt th orrtnss of th finl sign n w prov, with th us of n xmpl, tht th propos mtho xhiits itionl potntil for optimiztion gins whn ompr to xisting singl wir runny ition/rmovl prour. This is lso onfirm y our xprimntl rsults. In th futur, w intn to vlop n pply fmily of mor omplx logi trnsformtions uring th orrtion stg. It is lso mong our futur rsrh plns to vlut th prformn of our mtho on iruits wr th gts hv n ompos, s sri in [8], n for iffrnt optimiztion gols suh s powr n ly. Rfrns [1] M. S. Air, J. Frguson n T. E. Kirkln, Logi Vrifition Vi Tst nrtion, in IEEE Trns. on Computr Ai Dsign, vol. 7, pp. 138 148, Jnury 1988. [2] M. Armovii, P. R. Mnon n D. T. Millr, Critil pth tring: n ltrntiv to fult simultion, in IEEE Dsign n Tst of Computrs, vol. 1, pp. 89 93, Frury 1984.
[3] H. A. As, n J. Hys, Dsign vrifition vi simultion n utomti tst pttrn gnrtion, in Pro. IEEE/ACM Int l Conf. on Computr Ai Dsign, pp. 174 18, 1995. [4] R. E. Brynt, rph s lgorithms for Booln funtion mnipultion, in IEEE Trns. on Computrs, vol. C 35, no. 8, pp. 677 691, 1986. [5] P. ol, An Impliit Enumrtion Algorithm to nrt Tst for Comintionl Ciruits, in IEEE Trns. on Computrs, vol. C-3, pp. 215 222, Mrh 1981. [6] S. C. Chng, K. T. Chng, N. S.Woo, n M. M.- Sowsk, Lyout Drivn Logi Synthsis for FP- As, in Pro. of ACM/IEEE Dsign Automtion Confrn, pp.38 313, 1994. [7] S. C. Chng n M. Mrk-Sowsk, Prtur n Simplify:Multi-Lvl Booln Ntwork Optimizr, in Pro. Int l Conf. on Computr-Ai Dsign, pp. 2-5, 1994. [8] S. C. Chng, J. C. Chung, n Z. Z. Wu, Synthsis for Multipl Input Wirs Rplmnt of t for Wiring Consirtion, in Int l Conf. on Computr Ai Dsign, pp. 115 118, 1999. [9] L. A. Entrn, n K. T. Chng, Comintionl n Squntil Logi Optimiztion y Runny Aition n Rmovl, in IEEE Trns. on Computr Ai Dsign of Intgrt Ciruits n Systms, vol.14, no.7, pp.99-916, July 1995. [1] R. C-Y. Hung, Y. Wng, n K. T. Chng, Lir A Lir-Inpnnt Frmwork for Post- Lyout Prformn Optimiztion, in Pro. Int l Symp. on Physil Dsign, pp. 135-14, 1998. [11] M. Chttrj, D. Prhm, n W. Kunz, LOT: Logi Optimiztion with Tstility Nw Trnsformtions Using Rursiv Lrning, in Int l Conf. on Computr Ai Dsign, pp. 115 118, 1995. [12] A. Vnris, S.Vnktrmn, I. N. Hjj n W. K. Fuhs, Multipl sign rror ignosis n orrtion in igitl VLSI iruits, in Pro. of IEEE VLSI Tst Symp., pp. 58-63, 1999. [13] A. Vnris, n I. N. Hjj, Dsign Error Dignosis n Corrtion Vi Tst Vtor Simultion, in IEEE Trns. on Computr Ai Dsign,vol. 18, no. 12, pp. 183 1816, Dmr 1999. [14] S. Vnktrmn, I. Hrtnto n W. K. Fuhs, Dynmi ignosis of squntil iruits s on stuk t fults, in Pro. of th VLSI Tst Symp., pp. 198 23, 1996. [15] S. Vnktrmn n W. K. Fuhs, A utiv thniqu for ignosis of riging fults, in Pro. IEEE/ACM Int l Conf. on Computr Ai Dsign, pp. 562 567, 1997. [16] Q. Wng, n S. B. K. Vruhul, Multi Lvl Optimiztion for Low Powr Using Lol Logi Trnsformtions, in Pro. ACM/IEEE Dsign Automtion Confrn, pp.27 277, 1996.