ZY5/ZY5D SYSTEM BLOCK DIAGRAM

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PU ORE ISL PGE ZY/ZY SYSTEM LOK IGRM N ORE.V PGE N RUN.V PGE R II SMR_VTERM.VSUS(TPSREGR) PGE SYSTEM POWER ISL PGE INT or EV selector Resistor RII-SOIMM PGE RII-SOIMM PGE RII /00 MHz RII /00 MHz M Griffin SG Processor Lion Sabie P (upg)/w PGE,,, PU THERML SENSOR PGE PU Fan PGE SYSTEM HRGER (ISL) PGE ISHRGER /.V_S,.V,.V PGE 0 LVS PGE ZY NO USE MXM onnector PGE ZY NO USE PI-Express X LVS RT HMI HT LINK NORTH RIGE & SOUTH RIGE PI-E X Mini PI-E ard (Wireless LN) PGE X Mini PI-E ard (TV TUNER) US.0 x PGE X X X Express ard ard reader LN (NEW R) roadom JMicron PIE-LN US.0 Ports M/ JM-LGEZ0 x (0/00/GigaLN) PGE PGE 0 PGE RJ/RJ PGE LE OK LN/VG/VI/US/UIO PGE SNTLVPWR Switch PGE TSV0RHUR Switch PGE ST - H PGE ST0 MPM US.0 RT VI- HMI ST - H PGE O(PT) PGE ST ST mm X mm, pin G PI US.0 Ports luetooth x PGE x PGE x PGE Fingrprinter x PGE LE OK US x PGE RT PGE LE OK PGE HMI ONN. PGE.MHz PGE,,,0,,, LP H zalia udioontroller RealTek L/ PGE M. PGE ard us PMI O Micro OZ0TN PGE P STK UP Keyboard PGE IR PGE K (WPE0G) PGE udio mplifier TEST MOIFY Int MI LYER : TOP LYER : S LYER : IN LYER : IN LYER : V LYER : Touch SPI Pad ROM PGE PGE LE OK UIO PGE Speaker PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com SPIF/Phone Jack Line in MI Jack Quanta omputer Inc. PROJET : ZY Size ocument Number Rev lock iagram Wednesday, July 0, 00 ate: Sheet of

HT_RX#[..0] HT_RX#[..0] HT_TX[..0] HT_RX[..0] HT_RX[..0] HT_TX#[..0] HT_TX[..0] HT_TX#[..0] HOLE0 *PU_HOLE HOLE *PU_HOLE HOLE *PU_HOLE HOLE0 *PU_HOLE HOLE *H-P HOLE *H-P HOLE *H-P HOLE *H-P PROESSOR HYPERTRNSPORT INTERFE VLT_x N VLT_x RE ONNETE TO THE LT_RUN POWER SUPPLY THROUGH THE PKGE OR ON THE IE. IT IS ONLY ONNETE ON THE OR TO EOUPLING NER THE PU PKGE HOLE *MINI_HOLE HOLE *MINI_HOLE HOLE *MINI_HOLE HOLE *MINI_HOLE HOLE *H-P HT_PU_UPLK0 HT_PU_UPLK#0 HT_PU_UPLK HT_PU_UPLK# VLT_RUN HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# E E E F G G G H J K L L L M N N E F F F G H H H K K L M M M N P J J J K U VLT_0 VLT_ VLT_ VLT_ L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H0 L0_IN_L0 L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_IN_H L0_IN_L L0_LKIN_H0 L0_LKIN_L0 L0_LKIN_H L0_LKIN_L HT LINK VLT_0 VLT_ VLT_ VLT_ L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H0 L0_OUT_L0 L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_OUT_H L0_OUT_L L0_LKOUT_H0 L0_LKOUT_L0 L0_LKOUT_H L0_LKOUT_L E E E E W W V U U U T R Y W V V V U T T Y W Y Y.u/.V_ HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# REV: Modify HT_PU_WNLK0 HT_PU_WNLK#0 HT_PU_WNLK HT_PU_WNLK#.V L 0 ohm() VLT_RUN FJHS00_0 HOLE *O_HOLE HOLE *H-P MOIFY 0/,LEX Note:on MP,(HT=.V) and PU(HT=.V) and therefore cannot be connected to the same HT power rail..u/.v_ O HT_PU_UPTL0 HT_PU_UPTL#0 HT_PU_UPTL HT_PU_UPTL# NO STU for HT VLT_RUN thlon Sg Processor Socket SOKET PIN HT_PU_WNTL0 HT_PU_WNTL#0 HT_PU_WNTL HT_PU_WNTL# HOLE HOLE HOLE HOLE *MXM_HOLE *MXM_HOLE *MXM_HOLE *MXM_HOLE P *EMIP P *EMIP HOLE *O_HOLE HOLE *H-P HOLE *H_HOLE HOLE0 *H_HOLE 0P_ N L0_TLIN_H0 P L0_TLIN_L0 P L0_TLIN_H P L0_TLIN_L L0_TLOUT_H0 L0_TLOUT_L0 L0_TLOUT_H L0_TLOUT_L thlon Sg SOKET PIN R R T R LYOUT: Place bypass cap on topside of board NER HT POWER PINS THT RE NOT ONNETE IRETLY TO OWNSTREM HT EVIE, UT ONNETE INTERNLLY TO OTHER HT POWER PINS PLE LOSE TO VLT0 POWER PINS Quanta omputer Inc. PROJET : ZY Size ocument Number Rev M Griffin HT I/F ate: Wednesday, May, 00 Sheet of HOLE *H-P HOLE *H-P HOLE HOLE HOLE HOLE HOLE *M_HOLE *M_HOLE *MXM_HOLE *MXM_HOLE 0.u/.V_.u/.V_ HOLE *H_HOLE 0P_ HOLE *H-P HOLE *H_HOLE R */F_ *H-P L FJHS00_0.u/.V_ HOLE *NONP_HOLE HOLE *H-P R */F_ HOLE *FN_HOLE HOLE *H-P PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com

E V_VTT_SUS_PU IS ONNETE TO THE V_VTT_SUS POWER SUPPLY THROUGH THE PKGE OR ON THE IE. IT IS ONLY ONNETE ON THE OR TO EOUPLING NER THE PU PKGE Processor R Memory Interface SMR_VTERM SMR_VTERM MEM:T M Q[0..] M Q[0..] M Q0 G M Q0 PLE THEM LOSE TO U M Q M_T0 M_T0 M Q M Q M_T M_T F M Q PU WITHIN ".VSUS M Q M_T M_T H 0 M Q VTT VTT W0 M Q M_T M_T G 0 MEM:M/TRL/LK M Q VTT VTT 0 G M Q M_T M_T H 0 M Q VTT VTT 0 E M Q M_T M_T H 0 M Q M Q M_T M_T R./F_ VTT VTT 0 R M Q M_ZP VTT 0 M Q M_T M_T E F0 M Q M_ZN MEMZP PU_VTT_SUS_F M Q M_T M_T H.VSUS E0 K/F_ M Q T M Q0 M_T M_T E R./F_ MEMZN VTT_SENSE Y0 M Q0 MEM_M_RESET# PU_M_VREF M Q M_T0 M_T0 E M Q T0 H RSV_M MEMVREF W 0 M Q M_T M_T H M Q MEM_M_RESET# M Q M_T M_T E M Q M OT0 T M0_OT0 RSV_M T M Q M_T M_T F M Q M OT V 0 R M OT0 M0_OT M Q M_T M_T M Q T U M OT M_OT0 M0_OT0 W M OT0 M Q M_T M_T G.u/0V_ M Q T V 000p_ K/F_ M_OT M0_OT W M OT0 M OT 0 M Q M_T M_T G M Q M_OT0 Y T M Q M_T M_T M Q M S#0 T0 M0_S_L0 M Q M_T M_T M Q M S# U M S#0 M S#0 M0_S_L M0_S_L0 V M Q0 M_T M_T E0 M Q0 T0 U0 M S# M S# M_S_L0 M0_S_L W 0 M S#0 M Q M_T0 M_T0 E M Q T V0 M_S_L M_S_L0 U T 0 M Q M_T M_T F M Q M Q M_T M_T M Q M KE0 J M_KE0 M_KE0 J M KE0 M Q M_T M_T M Q M KE J0 M_KE M_KE H M KE E M Q M_T M_T F0 E M Q M Q M_T M_T F M Q T N M_LK_H M_LK_H P T G M Q M_T M_T H G M Q T N0 M_LK_L M_LK_L R T M Q M_T M_T J M Q M LKOUT E M_LK_H M_LK_H M LKOUT M Q M_T M_T E M Q M LKOUT# F M_LK_L M_LK_L M LKOUT# M Q0 M_T M_T E M Q0 M LKOUT Y M_LK_H M_LK_H F M LKOUT G M Q M_T0 M_T0 H0 M Q M LKOUT# M_LK_L M_LK_L F M LKOUT# G M Q M_T M_T H M Q T0 P M_LK_H M_LK_H R T M Q M_T M_T Y M Q T P0 M_LK_L M_LK_L R T M [0..] M Q M_T M_T M Q M [0..] M 0 M 0 M Q M_T M_T N E M Q M M_0 M_0 P M M Q M_T M_T M0 M Q M M_ M_ N M M Q M_T M_T W N M Q M M_ M_ P M M Q M_T M_T W M M Q M M_ M_ N M M Q M_T M_T Y M E M Q M M_ M_ N M M Q0 M_T M_T L0 M Q0 M M_ M_ L M M Q M_T0 M_T0 Y0 M M Q M M_ M_ N M M Q M_T M_T 0 L E0 M Q M M_ M_ L M M Q M_T M_T L F0 M Q M M_ M_ M M M Q M_T M_T K F M Q M 0 M_ M_ K M 0 M Q M_T M_T R F M Q M M_0 M_0 T M M Q M_T M_T L 0 M Q M M_ M_ L M M Q M_T M_T K0 0 M Q M M_ M_ L M M Q M_T M_T Y V M Q M M_ M_ W M M Q M_T M_T K E M Q M M_ M_ J M M Q0 M_T M_T W K M Q0 M_ M_ J M Q M_T0 M_T0 W M Q M S#0 M Q M_T M_T Y M Q M S#0 R0 M_NK0 M_NK0 R F M S# M Q M_T M_T Y M Q M S# R M_NK M_NK U M Q M_T M_T M Q M S# J M_NK M_NK J M S# F M Q M_T M_T F M Q M Q M_T M_T M Q M RS# R M_RS_L M_RS_L U M RS# F M Q M_T M_T M Q M S# T M_S_L M_S_L U M S# M Q M_T M_T M Q M WE# T M_WE_L M_WE_L U M WE# M Q M_T M_T Y Y M Q M Q0 M_T M_T W E M Q0 M Q M_T0 M_T0 F M Q M Q M_T M_T F M Q M Q M_T M_T thlon Sg SOKET PIN M Q M_T M_T thlon Sg Processor Socket SOKET PIN M QS0 M QS0 M QS#0 M_QS_H0 M_QS_H0 G M QS#0 M LKOUT M LKOUT M QS M_QS_L0 M_QS_L0 H M QS M QS# M_QS_H M_QS_H G M QS# M QS M_QS_L M_QS_L G M QS M QS# M_QS_H M_QS_H.p_NPO_.p_NPO_ M QS# M QS M_QS_L M_QS_L M QS M LKOUT# M LKOUT# F PLE LOSE TO PROESSOR PLE LOSE TO PROESSOR M QS# M_QS_H M_QS_H G E M QS# M QS M_QS_L M_QS_L G M QS M LKOUT WITHIN. INH M LKOUT WITHIN. INH M QS# M_QS_H M_QS_H M QS# M QS M_QS_L M_QS_L F M QS M QS# M_QS_H M_QS_H 0 F M QS# M QS M_QS_L M_QS_L 0.p_NPO_.p_NPO_ E M QS M QS# M_QS_H M_QS_H Y M QS# M LKOUT# M LKOUT# M QS M_QS_L M_QS_L W F M QS M QS# M_QS_H M_QS_H W E M QS# M_QS_L M_QS_L W To reverse SOIMM socket M M[0..] M M0 M M M M M M M M M M M M M M E E U M_M0 M_M M_M M_M M_M M_M M_M M_M M_M0 M_M M_M M_M M_M M_M M_M M_M E E F Y Y M M0 M M M M M M M M M M M M M M M M[0..] To normal SOIMM socket SMR_VTERM 0 0.u/.V_.u/.V_.u/.V_.u/.V_ 0 0 0.u/.V_.u/.V_.u/.V_.u/.V_ 000P_ 0 000P_ 000P_ 000P_ 0P_ 0 0P_ 0P_ 0P_ M QS[0..] M QS0 M QS M QS M QS M QS M QS M QS M QS thlon Sg SOKET PIN thlon Sg Processor Socket SOKET PIN M QS0 M QS M QS M QS M QS M QS M QS M QS M QS[0..] M QS#[0..] M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M QS#[0..] PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com Quanta omputer Inc. PROJET : ZY Size ocument Number Rev M Griffin RII MEMORY I/F Wednesday, May, 00 ate: Sheet of E

THLON ontrol and ebug.vsus.v LYOUT: ROUTE V TRE PPROX. 0 mils WIE (USE x mil TRES TO EXIT LL FIEL) N 00 mils LONG. PU_V_RUN L LMPG0SN_ PU_V_RUN.VSUS If M SI is not used, the SI pin can be left unconnected and SI should have a 0- ( %) pulldown to VSS. R 0_ R0 0_ R R 0 Ohm *0_ *K/F_ PU_SI PU_SI PU_LERT PU_SI PU_SI PU_THERMTRIP# PU_THERMTRIP#.VSUS R00 00_ R 0_ R0 00_ Q MMT0 SYS_SHN#,0 00u/.V_.u/.V_.u/.V_.VSUS 00p/0V_ PU_LKP PU_LKN PU_LKP PU_LKN place them to PU within." VLT_RUN 00P_ R /F_ 00P_ PU_V_RUN Keep trace from resisor to PU within 0." keep trace from caps to PU within." PU_LKIN_S_P PU_LKIN_S_N R R./F_./F_ PU_HT_RESET# PU_HT_PWRG PU_HT_LTSTOP# PU_LT_REQ#_PU PU_SI PU_SI PU_LERT PU_HTREF0 PU_HTREF F F F0 F F E R P U V V LKIN_H LKIN_L RESET_L PWROK LTSTOP_L LTREQ_L SI SI LERT_L HT_REF0 HT_REF KEY KEY SV SV THERMTRIP_L PROHOT_L MEMHOT_L THERM THERM M W F W W PU_SV_R PU_SV_R PU_THERMTRIP# PU_PROHOT# PU_MEMHOT# PU_THERM PU_THERM connect to PU VIO power F PU_PROHOT#.VSUS R 00_ R.VSUS R 0_ *0_ HEK MP thermal Q MMT0 E_PROHOT# MP_PROHOT#.VSUS HTPU_PWRG HTPU_STOP# HTPU_RST# R 0_ R 0_ R 0_ R 00_.VSUS R 00_.VSUS R 00_ PU_HT_PWRG PU_HT_LTSTOP# PU_HT_RESET# 0.u/0V_ REV: Modify connect to PU ORE power F REV:E Modify by M.VSUS R0 00_ R 00_ T T T T T T0 T T T PU_V0_F_H PU_V0_F_L PU_V_F_H PU_V_F_L PU_RY PU_TMS PU_TK PU_TRST# PU_TI PU_TEST_TSTUP PU_TEST_PLLTEST PU_TEST_PLLTEST0 PU_TEST_H_YPSSLK_H PU_TEST_L_YPSSLK_L PU_TEST_SNEN PU_TEST0_SNLK PU_TEST_SNLK PU_TEST_SNSHIFTEN PU_TEST_SNSHIFTEN PU_TEST_SINGLEHIN R 0_ PU_TEST_NLOGIN PU_TEST_IERKMON T F E Y G0 F H0 G E E F E E F V0_F_H V0_F_L V_F_H V_F_L RY TMS TK TRST_L TI TEST TEST TEST TEST_H TEST_L TEST TEST0 TEST TEST TEST TEST TEST TEST RSV RSV RSV RSV RSV VIO_F_H VIO_F_L VN_F_H VN_F_L REQ_L TO TEST_H TEST_L TEST TEST TEST TEST TEST TEST0 TEST TEST_H TEST_L RSV0 RSV RSV RSV RSV W Y H G E0 E J H E F K H H PU_REQ# PU_TO PU_TEST_H_PLLHRZ_P PU_TEST_L_PLLHRZ_N PU_TEST_P PU_TEST_P PU_TEST_P PU_TEST_P0 PU_TEST_NLOG_T PU_TEST0_NLOGOUT PU_TEST_IG_T V_N_F_H V_N_F_L PU_TEST_H_FLKOUT_P PU_TEST_L_FLKOUT_N PU_VIO_F_H PU_VIO_F_L T T T T T T T T T T T0 connect to PU VN power F route as differential as short as possible testpoint under package PU_SV_R PU_SV_R PU_MEMHOT# R 0_ R 0_.VSUS R *00_ VI Override ircuit.vsus R *0_ Serial VI lock SV Serial VI ata SV PUMEMHOT# connect to PU ORE power controlier R K_ R K_ Q *MMT0 dd pull up.vsus R 00_ thlon Sg SOKET PIN thlon Sg Processor Socket SOKET PIN HTPU_PWRG R 0_ R *0_ R *0_ PG_IN PU_LT_REQ#_PU PU H/W MONITOR /0/0' Reserve 0 ohm for PU thermal issue on -test V R R *0_ PU_THERM /F_ 00P_ PU_THERM 0 mil trace / 0 mil space MIL V_THM 0.u/0V_ R 0_ ddress H U V XN XP -OVT G -LT SMT SMLK HTPU_REQ# R 0K_ Q KSMT KSMLK V V R 0K_ N00E HTPU_REQ# To S GPIO To FN THERM_LERT# PUFN#_ON N_MT N_MLK PU_TEST_SINGLEHIN PU_TEST_PLLTEST PU_TEST_PLLTEST0 PU_TEST_P PU_TEST_P0 PU_TEST_TSTUP PU_TEST_SNEN PU_TEST0_SNLK PU_TEST_SNLK PU_TEST_SNSHIFTEN PU_TEST_SNSHIFTEN PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com V Rev:E dd R by M esign guide 0 V_0 on /. R0.K_ V R.K_ Q N00E Q N00E R R0 R0 R0 R Need heck with nvidia *00_ *00_ *00_ *00_ *00_ R 00_ R 00_ R 00_ R 00_ R *00_ R *00_.VSUS PU_HT_RESET#.VSUS V R Q *MMT0.VSUS R *0_ *0K_ R0 *0_ R *0_ R R *0_ *K/F_ R 00_ H_HTPU_RST# PU_REQ# PU_RY PU_TK PU_TMS PU_TI PU_TRST# PU_TO VFIX MOE SV SV Voltage Output(PU Power) 0 0.V 0.V 0.0V 0.V HT ONNETOR.VSUS T T T T T T T N *SP-00-0-P-LV HT RSV RSV0 REQ_L RY 0 TK TMS TI TRST_L TO 0 V_PRO_IO_ V_PRO_IO_RESET_L KEY H_HTPU_RST# Quanta omputer Inc. PROJET : ZY Size ocument Number Rev M Griffin TRL & EUG Wednesday, May, 00 ate: Sheet of 0 0

E PROESSOR POWER N GROUN UF J VSS VSS J VSS VSS J0 PU_ORE0 PU_ORE VSS VSS J VSS VSS J PU_ORE0 UE VSS VSS0 J VSS VSS J VSS VSS G P K V0_ V_ VSS VSS H P0 K V0_ V_ VSS VSS J R K V0_ V_ VSS0 VSS J R K 0u_V_ u/.v_.u/.v_.0u/v_ 0P_ V0_ V_ VSS VSS J R K V0_ V_ VSS VSS J R K V0_ V_ VSS VSS K T K V0_ V_ VSS VSS K0 T L V0_ V_ VSS VSS0 K T L V0_ V_ VSS VSS K T0 L0 PU_ORE V0_0 V_0 VSS VSS L T L V0_ V_ VSS VSS L T L V0_ V_ VSS VSS L U L V0_ V_ VSS0 VSS L U E L 0 V0_ V_ VSS VSS L U E M 0u_V_ V0_ V_ VSS VSS L U E M 0u_V_ u/.v_.u/.v_.0u/v_ 0P_ V0_ V_ VSS VSS M U E V0_ V_ VSS VSS M V E M V0_ V_ VSS VSS0 M V E N V0_ V_ VSS VSS M0 V0 E N V0_0 V_0 VSS VSS N V N0 V0_ V_ VSS VSS N V N V0_ V_ VSS VSS N W N PU_VN_ORE V0_ V_ VSS0 VSS Y P V_ VSS VSS PU_VN_ORE K P VN_ V_ VSS VSS M P VN_ V_ VSS VSS P P VN_ VSS VSS T Y VN_ VIO.VSUS P VSS VSS00 V V R 0 VN_ VIO VSS VSS0 V R0 u/.v_ u/.v_ u/.v_ VIO VSS VSS0.VSUS H V R VIO VIO VSS VSS0 J V R VIO VIO VSS VSS0 K U T VIO VIO VSS0 VSS0 K T T VIO VIO VSS VSS0 K T T VIO VIO0 VSS VSS0 K T T VIO VIO VSS VSS0 L T T VIO VIO VSS VSS0 M R T VIO VIO VSS VSS0 M P U VIO VIO VSS VSS M P U VIO0 VIO VSS VSS M P U EOUPLING ETWEEN PROESSOR N IMMs VIO VIO VSS VSS N P U0 VIO VIO VSS VSS U VSS0 VSS E U PLE LOSE TO PROESSOR S POSSILE VSS VSS F thlon Sg SOKET PIN VSS VSS U F VSS VSS U.VSUS thlon Sg F VSS VSS V F Processor Socket VSS VSS0 V F VSS VSS V SOKET PIN F VSS VSS V F VSS VSS V F VSS VSS V 0 0 F.u/.V_.u/.V_ VSS0 VSS V.u/.V_.u/.V_.u/.V_.u/.V_.u/.V_.u/.V_.0u/V_.0u/V_ 0P_ H VSS VSS W H VSS VSS Y H VSS VSS Y H VSS VSS N J VSS M Sg Griffin upg thlon Sg SOKET PIN thlon Sg Processor Socket SOKET PIN Top View F Quanta omputer Inc. PROJET : ZY Size ocument Number Rev M Griffin PWR & ate: Wednesday, May, 00 Sheet of E PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com

E E MEM_SMLK MEM_SMT M Q0 M Q MEM_SMT M M 0 M M M M M M Q MEM_SMLK M M 0 M M M M M M Q M Q0 M Q M MVREF_IM M Q M Q M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M QS# M Q M Q MVREF_IM MEM_SMLK M Q M Q M Q M Q M Q M Q M Q M Q M Q M M M0 M Q MVREF_IM M Q M M M M M M M M M M M QS0 M M M M M QS M QS M QS M QS M QS M QS M QS M Q0 M Q M Q M Q M Q M Q M Q M Q0 M Q M M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M 0 M Q M Q M M Q M M Q M M M Q M Q M M Q M M Q M Q M Q M Q M QS#0 M QS# M QS# M QS# M QS# M QS# M QS# M M M M M M0 M M M M M M M M M QS# M M QS M QS M QS M QS M QS M QS M QS0 M QS M Q M M M Q M Q M M M Q M Q0 M Q M M 0 M M Q M M Q M Q M Q M Q M M Q M Q0 MEM_SMT M Q M Q M Q M Q M Q M Q M S# M OT0 M S#0 M M M KE0 M OT M S# M WE# M S# M RS# M KE0 M OT0 M S# M RS# M S# M 0 M S#0 M S# M M S# M OT M 0 M S# M M M M S#0 M M S#0 M M M WE# M M M M M M M M M 0 M M M M M M 0 M M M M KE M M KE M M MEM_SMT MEM_SMLK MSM_T MSM_LK.VSUS V V SMR_VTERM.VSUS SMR_VTERM V V.VSUS.VSUS.VSUS.VSUS.VSUS SMR_VREF V SMR_VTERM V V M [0..] M KE0 M KE M RS# M S# M WE# M S#0 M S# M OT0 M Q[0..] M LKOUT M LKOUT# M LKOUT M LKOUT# M OT M S# M S# M S#0 M QS#[0..] M QS[0..] M M[0..] M LKOUT M LKOUT# M LKOUT M LKOUT# M OT0 M KE0 M KE M OT M [0..] M S# M S#0 M S# M QS#[0..] M QS[0..] M M[0..] M RS# M S# M WE# M Q[0..] M S#0 M S# Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R-II SOIMM* Wednesday, May, 00 ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R-II SOIMM* Wednesday, May, 00 ZY Size ocument Number Rev ate: Sheet of Quanta omputer Inc. PROJET : R-II SOIMM* Wednesday, May, 00 ZY REVERSE (H=.) REVERSE (H=.) M suggestion : 00 XR 0.U each R-Pack between.vsus and SMR_VTERM M suggestion : 00 XR for each R-pack NEE UT 0U/.V_ 0U/.V_ R0 _ R0 _.u/0v_ 0.u/0V_ 0.u/0V_.u/0V_ R _ R _ R _ R _ T T RP0 X_ RP0 X_ Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST 0 0 0 00 0 0 0 0 0 0 M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 SO-IMM J RII_SOIMM_R H. SO-IMM J RII_SOIMM_R H..u/0V_.u/0V_ RP X_ RP X_.u/0V_.u/0V_.u/0V_.u/0V_ *.U/0V_ *.U/0V_.u/0V_.u/0V_ *0u/0V_ *0u/0V_ RP X_ RP X_ R 0K_ R 0K_ *.U/0V_ 0 *.U/0V_ 0.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.U/.V_.U/.V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_ 0.u/0V_ 0.u/0V_.u/0V_.u/0V_.u/0V_.U/.V_.U/.V_.u/0V_.u/0V_ RP X_ RP X_ RP X_ RP X_ R _ R _ RP X_ RP X_.u/0V_.u/0V_ U_ U_ T T *0u/0V_ *0u/0V_ R _ R _.u/0v_.u/0v_.u/0v_.u/0v_.u/0v_.u/0v_.u/0v_.u/0v_.u/0v_.u/0v_ *0u/0V_ *0u/0V_.u/0V_.u/0V_ RP *.K_PR RP *.K_PR RP X_ RP X_.u/0V_.u/0V_ RP X_ RP X_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_ RP X_ RP X_ R0 _ R0 _.u/0v_.u/0v_ RP X_ RP X_ *.U/0V_ *.U/0V_.u/0V_ 00.u/0V_ 00.u/0V_.u/0V_ RP X_ RP X_ 0.u/0V_ 0.u/0V_.u/0V_.u/0V_ RP0 X_ RP0 X_.u/0V_ 0.u/0V_ 0 Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q 0 Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q0 Q Q Q Q 0 Q Q Q Q Q Q0 Q Q Q 0 Q Q Q Q Q Q Q0 0 Q Q Q N 0 N N N 0 N/TEST 0 0 0 00 0 0 0 0 0 0 M0 0 M M M M 0 M M 0 M QS0 QS QS QS 0 QS QS QS QS K0 0 K0 K K KE0 KE 0 VREF RS 0 S WE 0 S0 0 S S0 S 00 S SL Vspd V0 V V V V V V 0 V V 0 V V0 V VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS VSS0 0 VSS VSS VSS VSS VSS0 VSS VSS VSS VSS VSS VSS VSS VSS 0 VSS QS0 QS QS QS QS QS QS QS OT0 OT VSS VSS VSS VSS 0 VSS VSS VSS VSS VSS0 SO-IMM J RII_SOIMM_R H. SO-IMM J RII_SOIMM_R H..u/0V_ 0.u/0V_ 0 R K/F_ R K/F_ RP X_ RP X_ RP X_ RP X_.u/0V_.u/0V_.u/0V_.u/0V_ R _ R _.u/0v_.u/0v_.u/0v_.u/0v_ RP X_ RP X_ R 0_ R 0_ RP X_ RP X_.u/0V_.u/0V_.u/0V_.u/0V_ RP X_ RP X_.u/0V_.u/0V_.u/0V_.u/0V_ RP X_ RP X_.u/0V_ 0.u/0V_ 0.u/0V_.u/0V_ T T R *0_ R *0_ RP X_ RP X_ T0 T0 Q0 *N00E Q0 *N00E T T *.U/0V_ *.U/0V_ *.U/0V_ *.U/0V_.u/0V_ 0.u/0V_ 0 R K/F_ R K/F_.u/0V_.u/0V_ *0U *0U RP X_ RP X_ *0u/0V_ *0u/0V_ RP X_ RP X_.u/0V_.u/0V_ RP X_ RP X_.u/0V_.u/0V_ R0 _ R0 _ R 0_ R 0_ RP X_ RP X_.u/0V_.u/0V_.u/0V_.u/0V_ R 0_ R 0_ R _ R _.u/0v_ 0.u/0V_ 0 Q *N00E Q *N00E *0U *0U.u/0V_.u/0V_ R _ R _.u/0v_.u/0v_.u/0v_.u/0v_ 0U/.V_ 0U/.V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_ T T.u/0V_.u/0V_ PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com

HT_TX[..0] HT_RX[..0] HT_TX#[..0] U FG-NVII-MP :JMP0T00 :JMP0T0 HT_RX#[..0] HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX0 HT_TX#0 HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# HT_TX HT_TX# F G H J J K K L G F L K L K J K E F G H J L K E E HT_MP_RX0_P HT_MP_RX0_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX0_P HT_MP_RX0_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N HT_MP_RX_P HT_MP_RX_N SE OF HT HT_MP_TX0_P HT_MP_TX0_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX0_P HT_MP_TX0_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N HT_MP_TX_P HT_MP_TX_N K J K L K L L K K L K L H J L0 M0 G H F G H J E F E F G 0 0 E F HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX0 HT_RX#0 HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_RX HT_RX# HT_PU_WNLK0 HT_PU_WNLK#0 HT_PU_WNLK HT_PU_WNLK# J H L K HT_MP_RX_LK0_P HT_MP_RX_LK0_N HT_MP_RX_LK_P HT_MP_RX_LK_N HT_MP_TX_LK0_P HT_MP_TX_LK0_N HT_MP_TX_LK_P HT_MP_TX_LK_N K J G H HT_PU_UPLK0 HT_PU_UPLK#0 HT_PU_UPLK HT_PU_UPLK# V V_PLL L0 TI00U00_ REV: Modify NV FE: HTMP_OMP_V ONNET TO.V_HT_PLL.U/.V_ m m HT_PU_WNTL0 HT_PU_WNTL#0 HT_PU_WNTL HT_PU_WNTL# PU_THERMTRIP# MP_PROHOT#.u/0V_.V_N.V_N.V_N.V_HT_PLL L 0 L 0 R R 0m PU_THERMTRIP# MP_PROHOT# V_PLL TI00U00_.U/.V_.V_HT_PLL.u/0V_ TI00U00_.U/.V_.V_PLL_PU.u/0V_ R0 0_ R 0/F_ HTMP_OMP_V M 0/F_ HTMP_OMP_ L.u/0V_ PU_SVREF *.K/F_ MP_TERM_J REV: Modify H G R G HT_MP_RXTL0_P HT_MP_RXTL0_N HT_MP_RXTL_P HT_MP_RXTL_N THERMTRIP#/GPIO_ PROHOT#/GPIO_0.V_LL_HT.V_PLL_HT.V_PLL_PU HT_MP_OMP_V HT_MP_OMP_ PU_SVREF LK00_TERM_ HT_MP_TXTL0_P HT_MP_TXTL0_N HT_MP_TXTL_P HT_MP_TXTL_N HT_MP_REQ# HT_MP_STOP# HT_MP_RST# HT_MP_PWRG LKOUT_00MHZ_P LKOUT_00MHZ_N LKOUT_MHZ.V_HT_.V_HT_.V_HT_.V_HT_.V_HT_.V_HT_.V_HT_ K0 J0 0 L M K Y Y Y V V W W HTPU_REQ# LKOUT_MHz.V_HT_ U_.V_HT_ U_ U_ U_ T HT_PU_UPTL0 HT_PU_UPTL#0 HT_PU_UPTL HT_PU_UPTL# HTPU_REQ# HTPU_STOP# HTPU_RST# HTPU_PWRG PU_LKP PU_LKN.u/.V_ u/.v_ L TI00U00_.u/.V_.u/.V_ u/.v_.v_n L PY00T_ 00m.V_N 0m MP_PROHOT# R 00_ PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com.vsus Quanta omputer Inc. PROJET : ZY Size ocument Number Rev MP HyperTransport us ate: Wednesday, May, 00 Sheet of

PEG_RXP[:0] PEG_RXN[:0] PEG_TXP[:0] PEG_TXN[:0] V_S Page 0 : R *0K_ MXM circuit ZY no use it [TV] [NEW R] PIE_WKE#,, [MINI R] [Giga LN] PIE_WKE# PE0_PRSNTX# MXM_ON# PIE_RXP PIE_RXN MINI_LKREQ# PIE_RXP PIE_RXN TV_LKREQ# PIE_RXP PIE_RXN LN_LKREQ# PIE_RXP PIE_RXN NEW_LKREQ# PPE#.V_N T T T R0 0 PEG_RXP0 PEG_RXN0 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP0 PEG_RXN0 PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PEG_RXP PEG_RXN PIE_WKE# PE0_PRSNTX PE0_PRSNTX PE0_PRSNTX PE0_PRSNTX# *_EV^0_ MINI_LKREQ# TV_LKREQ# R 0_ LN_LKREQ# R 0_ NEW_LKREQ# S PPE#_.V_PLLPE_SS F G F F 0 0 F F F F H H H H H H K K K K K K J J0 K K0 H U U0 U U L L0 W W M M U U N N U U N0 N R U P P0 T V P P U V0 U FG-NVII-MP PE0_RX0_P PE0_RX0_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX0_P PE0_RX0_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE0_RX_P PE0_RX_N PE_WKE#/GPIO_ PE0_PRSNT_# PE0_PRSNT_# PE0_PRSNT_# PE0_PRSNT_# PE_RX_P PE_RX_N PE_LKREQ# PE_PRSNT# PE_RX_P PE_RX_N PE_LKREQ# PE_PRSNT# PE_RX_P PE_RX_N PE_LKREQ# PE_PRSNT# PE_RX_P PE_RX_N PEE_LKREQ#/GPIO_ PEE_PRSNT# PE_RX_P PE_RX_N PEF_LKREQ#/GPIO_ PEF_PRSNT# PE_RX_P PE_RX_N PEG_LKREQ#/GPIO_ PEG_PRSNT# SE OF PIE PE0_TX0_P PE0_TX0_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX0_P PE0_TX0_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE0_TX_P PE0_TX_N PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PE_REFLK_P PE_REFLK_N PE_TX_P PE_TX_N PEE_REFLK_P PEE_REFLK_N PE_TX_P PE_TX_N PEF_REFLK_P PEF_REFLK_N PE_TX_P PE_TX_N PEG_REFLK_P PEG_REFLK_N.V_PE_ 0 0 E E0 F F0 G G0 H H0 H H R R0 M M T T M M T T0 M M T T M0 M T T P P T T P P P R W _PEG_TXP0 0 _PEG_TXN0 0 _PEG_TXP 0 _PEG_TXN 0 _PEG_TXP 0 _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP 0 _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP0 _PEG_TXN0 _PEG_TXP 0 _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP 0 _PEG_TXN _PEG_TXP _PEG_TXN _PEG_TXP _PEG_TXN PE0_REFLK_P R PE0_REFLK_N R PIE_TXP_ PIE_TXN_ LK_PIE_MINI_R LK_PIE_MINI#_R PIE_TXP_ PIE_TXN_ LK_PIE_TV_R LK_PIE_TV#_R PIE_TXP_ PIE_TXN_ LK_PIE_LN_R LK_PIE_LN#_R PIE_TXP_ PIE_TXN_ LK_PIE_NEW R LK_PIE_NEW_#_R 00m.V_PE *_EV^.u/0V_ PEG_TXP0 *_EV^.u/0V_ PEG_TXN0 *_EV^.u/0V_ PEG_TXP *_EV^.u/0V_ PEG_TXN *_EV^.u/0V_ PEG_TXP *_EV^.u/0V_ PEG_TXN *_EV^.u/0V_ PEG_TXP *_EV^.u/0V_ PEG_TXN *_EV^.u/0V_ PEG_TXP *_EV^.u/0V_ PEG_TXN *_EV^.u/0V_ PEG_TXP *_EV^.u/0V_ PEG_TXN *_EV^.u/0V_ PEG_TXP *_EV^.u/0V_ PEG_TXN *_EV^.u/0V_ PEG_TXP *_EV^.u/0V_ PEG_TXN *_EV^.u/0V_ PEG_TXP *_EV^.u/0V_ PEG_TXN *_EV^.u/0V_ PEG_TXP *_EV^.u/0V_ PEG_TXN *_EV^.u/0V_ PEG_TXP0 *_EV^.u/0V_ PEG_TXN0 *_EV^.u/0V_ PEG_TXP *_EV^.u/0V_ PEG_TXN *_EV^.u/0V_ PEG_TXP *_EV^.u/0V_ PEG_TXN *_EV^.u/0V_ PEG_TXP *_EV^.u/0V_ PEG_TXN *_EV^.u/0V_ PEG_TXP *_EV^.u/0V_ PEG_TXN *_EV^.u/0V_ PEG_TXP *_EV^.u/0V_ PEG_TXN *_EV^_ *_EV^_ R R 0.u/0V_.u/0V_ R0 _ R0 _.u/0v_.u/0v_ R _ R _ 00 R0 R0 Page 0 : LK_PIE_MXM LK_PIE_MXM# *_MINI^.u/0V_ *_MINI^.u/0V_ *_MINI^_ *_MINI^_ MXM circuit ZY no use it PIE_TXP PIE_TXN LK_PIE_MINI LK_PIE_MINI# PIE_TXP PIE_TXN LK_PIE_TV LK_PIE_TV# PIE_TXP PIE_TXN LK_PIE_LN LK_PIE_LN# *_NEW^.u/0V_ PIE_TXP *_NEW^.u/0V_ PIE_TXN *_NEW^_ LK_PIE_NEW_ *_NEW^_ LK_PIE_NEW_#.V_N [MXM] [MINI R ZY only] [TV ZY only, MINI R ZY only] [Giga LN] ZY modify use single stack _wireless ard [ard Reader] y Jack Weng L 0_ [NEW R] Page 0 : NEW R circuit ZY no use it For EMI LK_PIE_MXM LK_PIE_MXM# LK_PIE_MINI LK_PIE_MINI# REV: Modify 0m.V_N POWER connect to LL_HT REV: Modify *0P_ *0P_ 0 *0P_ 0 *0P_ L0 MLG00NJ_ L V_PLL 0m.u/.V_.U/.V_.V_PLLPE_SS U.V_PLL_PE_SS MLG00NJ_.V_PLLPE R0.V_PLL_PE.U/.V_ R N/.V_PLL_PE.u/0V_ V_PLL P0 N/.V_PLL_PE_SS PE_LK_OMP V PE_LK_OMP.u/0V_ R *.K/F_ <00mil Remove R for Nvidia suggest..v_pe_.v_pe_.v_pe_.v_pe_.v_pe_.v_pe_.v_pe_.v_pe_.v_pe_.v_pe_.v_pe_.v_pe_ PE_RST0# PE_RST# W V V W Y Y Y Y W Y W Y W0 W 0m.V_PE R *0_.u/0V_.u/0V_ U_.u/0V_ U_.u/0V_ u/.v_ U_ PIE_RST0#, dd 0R resistor, The resistor should only be stuffed for MP PIE_RST#.u/.V_ u/.v_ u/.v_ ( For MXM, LN,ard Reader ) ( For New card, WL,TV ) L0 u/.v_ PY00T_.V_N LK_PIE_NEW_ LK_PIE_NEW_# *0P_ *0P_ Internal K to.v LK_PIE_LN LK_PIE_LN# *0P_ *0P_ R0 *K_ MINI_LKREQ# R *K_ NEW_LKREQ# LK_PIE_TV *0P_ LK_PIE_TV# *0P_ R *K_ PPE#_ R *K_ TV_LKREQ# R *K_ LN_LKREQ# PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com Quanta omputer Inc. PROJET : ZY Size ocument Number Rev MP PI-Express us Friday, July, 00 ate: Sheet of

REQ0# MXM_PWR_EN [..0] INT# MXM_PWR_EN REQ0# REQ# REQ# REQ# 0 0 0 0 INT# INT# INT# INT# E0 G0 J0 M E 0 0 0 L K J J H G F E G E J K L G J E H F L J K U FG-NVII-MP PI_REQ0# PI_REQ#/FNRPM PI_REQ#/GPIO_0/RS_SR# PI_REQ#/GPIO_/RS_TS# PI_REQ#/GPIO_/RS_SIN# PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ PI_INTW# PI_INTX# PI_INTY# PI_INTZ# MP SE OF PI PI_GNT0# PI_GNT#/FNTL PI_GNT#/GPIO_/RS_TR# PI_GNT#/GPIO_/RS_RTS# PI_GNT#/GPIO_/RS_SOUT# PI_E0# PI_E# PI_E# PI_E# PI_EVSEL# PI_FRME# PI_IRY# PI_PR PI_PERR#/GPIO_/RS_# PI_SERR# PI_STOP# PI_PME#/GPIO_0 PI_RESET0# PI_RESET# PI_RESET# PI_LK0 PI_LK PI_LK PI_LK PI_LK PI_LKIN F0 H0 K0 L0 F K K F K L J H J J K K GNT0# EVSEL# FRME# IRY# PR PERR# SERR# STOP# PI_PME# PIRST_R# PIRST# PIRST# R T T PI_LK R R PI_LK T PI_LK T PI_LK T PI_LK PI_LKIN *^_ *^_ R _ GNT0# E0# E# E# E# EVSEL# FRME# IRY# PR PERR# SERR# STOP# PI_PME# PIRST# PLK_PM L:match to within 000 = Length of PI feedback and onboard devices = PI/LP PULL-UP RP INT# INT# INT# TRY# INT# REQ0# PERR# EVSEL# V 0.KX_0PR RP MXM_PWR_EN REQ# REQ# REQ# SERR# IRY# STOP# FRME# V 0.KX_0PR LKRUN# R.K_ MXM_ON# R0.K_ PI_PME# R *.K_ V_S SERIRQ R *.K_ V For OZ0 LOK YPSS LP_LK_E *P_ V V V TRY# TRY# K PI_TRY#,, LKRUN# MXM_ON# SERIRQ MXM_ON# R T LRQ#0 SERIRQ 0K_ F0 L K K K J L L J K L J J L K G0 PI_LKRUN#/GPIO_ LP_RQ#/GPIO/FNRPM LP_RQ0#/GPIO_0 LP_SERIRQ IE_T_P0/WUS_T0 IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P/WUS_T IE_T_P IE_T_P IE_T_P0 IE_T_P IE_T_P IE_T_P IE_T_P IE_T_P IE LP LP_FRME# LP_PWRWN#/GPIO_/EXT_NMI# LP_RESET0# LP_RESET# LP_0 LP_ LP_ LP_ LP_LK0 LP_LK IE_R_P0/WUS_STOP IE_R_P/WUS_RX_EN IE_R_P/WUS_TX_EN IE_S_P#/WUS_PHY_RESET# IE_S_P# IE_K_P# L G E H J K J LFRME#_ LP_P# LP_RST0# LP_RST# L0_ L_ L_ L_ LP_LK_E_R LP_LK_EUG R T T R _ R _ R0 _ R0 _ R0 _ R0 _ R _ R _ LFRME#,, LP_RST_E#, L0, L, L, L, LP_LK_E LP_LK_EUG LP_LK_EUG R *P_ PI_LKIN *P_ Reserve EMI solution V R R R.K_ 0K_.K_ PREQ K IE_INTR H0 PIORY K0 L0 LE_ET_P F IE_REQ_P/WUS_PLK IE_INTR_P/WUS_PHY_TIVE IE_RY_P/WUS_T_EN IE_IOR_P#/WUS_SERIL_T LE_ET_P/GPIO_ IE_IOW_P#/WUS STTUS IE_OMP_PV IE_OMP_ J0 M K IE_OMP_V R IE_OMP_V_ /F_ V R K_ R /F_ PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com Quanta omputer Inc. PROJET : ZY Size ocument Number Rev MP PI/LP/IE Wednesday, May, 00 ate: Sheet of

U FG-NVII-MP R0 R 0K_ 0 0 0K_ E F G J0 LN_RXER LN_OL J LN_RS RGMII_RX0/MII_RX0 RGMII_RX/MII_RX RGMII_RX/MII_RX RGMII_RX/MII_RX RGMII_RX/MII_RXLK RGMII_RXTL/MII_RXV MII_RXER/GPIO_ MII_OL/MSM_T MII_RS/MSM_LK SE OF LN.V_UL_RMGT.V_UL_RMGT RGMII_TX0/MII_TX0 RGMII_TX/MII_TX RGMII_TX/MII_TX RGMII_TX/MII_TX RGMII_TXLK/MII_TXLK RGMII_TXTL/MII_TXEN L N J K L L H K R 0K_ V_UL.V_UL m m m.v_ul R 0K_ LN_INT N RGMII/MII_INTR/GPIO.V_PLL_M_UL RGMII/MII_M RGMII/MII_MIO RGMII/MII_PWRWN#/GPIO_ K0 L0 MIO R 0K_ MII_OMP_PV MII_OMP_ UF_MHZ MII_RESET# MII_VREF G H0 RGMII_VREF R 0K_ R /F_ RG RSET K.0u/V_RG VREF RG RSET RG VREF RG RE RG GREEN RG LUE RT_RE RT_GRN RT_LU RT_RE RT_GRN RT_LU m.v_n L TI00U00_.u/0V_ E H.V_PLL_ISP N E F.U/.V_ REV: Modify TV RSET TV VREF.V_PLL_ISP TV_XTLIN TV_XTLOUT S RG HSYN RG VSYN _LK0 _T0.V_RG_ G H G H E V.u/0V_ L TI00U00_ 0 0.u/.V_.u/.V_ RT_HSYN RT_VSYN RTLK RTT m V RT_RE RT_GRN RT_LU R R R 0/F_ 0/F_ 0/F_ FOR UM ONLY Remove R,R V R0 R L_LON L_V_ON *.K_ *.K_ T MP_GPIO MP_GPIO U T E E GPIO_/FERR/SYS_SERR/IGPU_GPIO_* GPIO_/NFERR/SYS_PERR/IGPU_GPIO_* L_KL_TL L_KL_ON L_PNEL_PWR.V_TV_ TV RE TV GREEN TV LUE IFP_TX_P IFP_TX_N F E0 E V m INT_TXLLKOUT INT_TXLLKOUT- REV: Modify PGE : 0 HMI circuit ZY no use it.v_n 00m HMILKP HMILKN HMITX0P HMITX0N HMITXP HMITXN HMITXP HMITXN V REV: Modify 0m.V L 0m V.V_PLLPE_SS TI00U00_.u/.V_ R R R0 R00.u/0V_ 0 0 0 0 0 *_HMI^.u/0V_ HMI_TXP_ *_HMI^.u/0V_ HMI_TXN_ *_HMI^.u/0V_ HMI_TX0P_ *_HMI^.u/0V_ HMI_TX0N_ *_HMI^.u/0V_ HMI_TXP_ *_HMI^.u/0V_ HMI_TXN_ *_HMI^.u/0V_ HMI_TXP_ *_HMI^.u/0V_ HMI_TXN_ *0K_ *0K_ K_ *0K_ HP_ROM_SLK HP_ROM_ST HPLUG_ET HMI_HP L 0_.u/.V_ *U_.V_IFP.u/0V_ L TI00U00_.U/.V_.V_PLL_IFPP.u/0V_.u/0V_ R0 K/F_ m.v_p_v HMI_RSET HMI_VPROE L M K J M0 L0 K0 J0 E L U0 H K K HMI_TX_P/ML0_LNE_P HMI_TX_N/ML0_LNE_N HMI_TX0_P/ML0_LNE_P HMI_TX0_N/ML0_LNE_N HMI_TX_P/ML0_LNE_P HMI_TX_N/ML0_LNE_N HMI_TX_P/ML0_LNE0_P HMI_TX_N/ML0_LNE0_N UX_H0_P UX_H0_N HPLUG_ET HPLUG_ET.V_IFP.V_IFP.V_IFP_HV.V_HMI_PLL_HV.V_PLL_P.V_P_V HMI_RSET HMI_VPROE 0 Remove,R *.U/0V_ for Nvidia suggest. FLT PNEL IFP_TX0_P IFP_TX0_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N IFP_TX_P IFP_TX_N _LK _T _LK _T IFP_RSET IFP_VPROE 0 0 J J E E F0 F G0 G H H0 L J L K 0 INT_TXLOUT INT_TXLOUT- INT_TXUOUT INT_TXUOUT- HMILK HMIT IFP_RST IFP_VPROE Remove,R for Nvidia suggest. T T T T *.0u/V_ INT_TXLOUT0 INT_TXLOUT0- INT_TXLOUT INT_TXLOUT- INT_TXLOUT INT_TXLOUT- INT_TXULKOUT INT_TXULKOUT- INT_TXUOUT0 INT_TXUOUT0- INT_TXUOUT INT_TXUOUT- INT_TXUOUT INT_TXUOUT- INT_LVS_EILK INT_LVS_EIT HMILK HMIT R *K/F_ [LVS] PGE : 0 HMI circuit ZY no use it HMILK HMIT R R V *_HMI^0K_ *_HMI^0K_ REV: Modify / NV FE HEK IT. HMI_HP HMI_HP PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com Quanta omputer Inc. PROJET : ZY Size ocument Number Rev MP LN and Graphics Wednesday, May, 00 ate: Sheet of 0

UE FG-NVII-MP REV: Modify [ST H ] [ST H ] [ST O] ST_TXP0 ST_TXN0 ST_RXN0 ST_RXP0 ST_TXP ST_TXN ST_RXN ST_RXP ST_TXP ST_TXN ST_RXN ST_RXP REV: Modify.0u/V_ST_TXP0_.0u/V_ST_TXN0_.0u/V_ST_TXP_.0u/V_ST_TXN_.0u/V_ST_TXP_.0u/V_ST_TXN_ T T T T ST_TXP ST_TXN ST_RXN ST_RXP E E G G E E G G H H G G F F L L K L J J K K ST_0_TX_P ST_0_TX_N ST_0_RX_N ST_0_RX_P ST TX_P ST TX_N ST RX_N ST RX_P ST_0_TX_P ST_0_TX_N ST_0_RX_N ST_0_RX_P ST TX_P ST TX_N ST RX_N ST RX_P ST_0_TX_P ST_0_TX_N ST_0_RX_N ST_0_RX_P ST TX_P ST TX_N ST RX_N ST RX_P ST SE OF US US0_P US0_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US_P US_N US0_P US0_N US_P US_N US_P US_N US_P US_N US_P US_N RSV RSV RSV RSV RSV RSV U U U U U U V V W W W W W W Y Y USP USP- USP USP- USP USP- USP USP- USP USP- USP USP- USP USP- USP0 USP0- USP USP- USP0 USP0- USP USP- USP USP- USP USP- USP USP- USP USP- USP0 USP0- USP USP- USP USP- USP USP- USP 0 USP- 0 USP USP- USP USP- USP0 USP0- USP USP- USP USP- USP USP- USP USP- VSUS MINI R * MINI R * LUETOOTH REV: Modify INT LEFT US R REER INT LEFT US Fingerprint EXT US * ocking EXT US * NEW R REV: Swap Modify US PULL-OWN USP0- USP0 RN USP- RN USP USP- USP RN0 USP USP- RN USP RN USP- USP RN USP- USP RN0 USP- USP RN USP- USP RN USP- USP0 RN USP0- USP RN USP- KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ KX_ 0m.V_N 0m m 0m R 0_.V_N.V_N.V_N.V_SP_ 0u/.V_ ST_LE# L MLG00NJ_.V_PLL_SP_V.u/0V_.U/.V_ L MLG00NJ_.u/0V_.U/.V_.V_PLL_SP_SS L TI00U00_ 0.u/0V_.V_PLL_LEG 0.U/.V_ 0 0u/.V_.u/.V_.u/0V_.u/0V_ W V P E E E E.u/0V_ 0 ST_LE#/GPIO_.V_PLL_SP_V.V_PLL_SP_SS.V_PLL_LEG.V_SP_.V_SP_.V_SP_.V_SP_.V_SP_.V_SP_ US_O0#/GPIO_ US_O#/GPIO_ US_O#/GPIO_ US_O#/GPIO_/MGPIO_ US_O#/GPIO_/MGPIO_.V_PLL_US.V_US_UL.V_US_UL T T T T T P Y Y USO#0 USO# USO# USO# USO#.V_US_PLL.V_US_UL R R R R R0 L 0.u/0V_.u/.V_.u/0V_ 0K_ 0K_ 0K_ 0K_ 0K_ TI00U00_ L m.u/0v_ V TI00U00_ V_S 0m USP USP- RN USP USP- RN USP USP- RN USP USP- RN.V_N KX_ KX_ KX_ KX_.V_N L PY00T_ 0m.u/.V_.u/.V_.u/0V_.u/0V_.V_SP_ ST_THRM.u/0V_ R.K/F_ 0 0 E0 J.V_SP_.V_SP_.V_SP_ ST_TERMP US_RIS_ T US_RIS_ R /F_ REV: Modify Ohm for MP checklist 0 000p_ 000p_ PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com Quanta omputer Inc. PROJET : ZY Size ocument Number Rev MP ST and US ate: Wednesday, May, 00 Sheet of

V V_S PE_RESET_MXM# Z_SIN0 Z_SIN Z_SIN PU LEGY PULL-UP R R R R MXM_RUNWORK need to onnect from MXM card GTE0 RIN# KSMI# SIO_PME# MXM_PRESENT# MXM_RUNPWROK GTE0 RIN# E_SI# KSMI# SM_INTRUER# MP_LI# PMU PULL-UP R R R0 R R *0K_ *0K_.K_ 0K_ *0K_ *0K_ *0K_ *0K_ *0K_ R PE_RESET_MXM_R# *_EV^0_ RSTTN# RI# MP_GPIO PM_TLOW# NSWON# PU V for KSMI# & SIO_PME#,0/0 LEX T0 T T MP_GPIO MXM_PRESENT# MP_GPIO MXM_RUNPWROK PE_RESET_MXM_R# R0 0_ MP_GPIO SIO_PME# RI# MP_LI# PM_TLOW# MP_GPIO MP_GPIO Z_SOUT Z_ITLK Z_RESET# Z_SYN SUSR# R 0_ SLP_RMGT# T SUSR# R0 0_ VORE.I0_R R_PPE# R_WKE# PSPK R T T T T T R 0_ R 0_ MSM_LK MSM_T SM_LERT# H Z_SOUT Z_SYN Z_RESET# Z_ITLK REV:E Modify by NV EMI Solution *K_ PLK_SM PT_SM Z_SOUT Z_SYN Z_RESET# Z_ITLK SUS# SUS# REV: Modify PSPK ZY TEST EL MOEM Y JK WENG R0 _ R * R *_*EV^_ R _ R * R *_*EV^_ R _ R * R *_*EV^K_ L NQ00T-Y-N_ L *_NQ00T-Y-N_ L *_*EV^NQ00T-Y-N_ PLK_SM,, PT_SM,, MSM_LK MSM_T THERM_LERT# R 0_ Z_SOUT_UIO Z_SOUT_M Z_SOUT_MXM Z_SYN_UIO Z_SYN_M Z_SYN_MXM Z_RESET#_UIO Z_RESET#_M Z_RESET#_MXM Z_ITLK_UIO Z_ITLK_M Z_ITLK_MXM 0P_ 0P_ 0P_ 0P_ V_S V_S V_S STRPPING H_RESET# (LN) 0 MII RGMII (EFULT) H_SOUT_R, LFRM# (IOS) 00 LP (EFULT) 0 PI IOS 0 SPI IOS RESERVE (SPI) MP_SPKR (oot MOE) 0 USER TLE (EFULT) SFE TLE H_SYN_R (SIO LOK) 0.MHz (EFULT) MHz SPI_O, SPI_LK (SPI LOK) 00 MHz 0 MHz 0 MHz MHz V V V V R R R00 R R R R R R R R0 R R R 0K_ *0K_ *.K_.K_ *.K_.K_ *0K_ 0K_ *0K_ 0K_ 0K_ *0K_ *0K_ 0K_ Z_RESET# Z_SOUT PSPK Z_SYN LFRME#,, MP_SPI_O MP_SPI_LK.VSUS NSWON# elay 0ms RTRST# after S powerok RSMRST#, PWROK_E, HWPG_.V,0 HWPG_.V, PU_OREPG PWRTN# RSTTN# MP_GPIO MP_GPIO0_I0 MP_GPIO_I MP_GPIO_I R 00_ PU_SI PU_SI.VSUS PU_SI R *00_ PU_SI R *00_ confirm by n-vidia FE 0/ V T V R R0 R R P_ P_ *K_ *K_ *0K_ K_ P N R M M0 M K K M P P L P N0 V W W0 Y0 0 W Y UF FG-NVII-MP H_ST_IN0/GPIO_ H_ST_IN/GPIO_/MGPIO_0 H_ST_IN/GPIO_/MGPIO_ GPIO_/PWRN_OK/SPI_S GPIO_/NMI/PS_LK0 GPIO_/SMI#/PS_T0 GPIO_/SI/PS_LK GPIO_/INIT#/PS_T GPIO_/SUS_STT/LMTR_EXT_TRIG# 0GTE/GPIO_/FNTL KRRSTIN#/GPIO_/FNRPM SIO_PME#/GPIO_/SPI_S EXT_SMI#/GPIO_ RI#/GPIO INTRUER# LI# LL# FI_RSV0 FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV FI_RSV SE OF H MIS H_OK_EN#/GPIO_ H_OK_RST#/GPIO H_ST_OUT/GPIO_ H_ITLK H_RESET# H_SYN/GPIO_ SLP_S# SLP_RMGT# SLP_S# MP_VI0/GPIO_ MP_VI/GPIO_ MP_VI/GPIO_ SPKR SM_LK0 SM_T0 SM_LK/MSM_LK SM_T/MSM_T SM_LERT#/GPIO_ THERM#/GPIO_ R P R H H H K E G E F F K R *K_ U_ R _ R0 P M L T0 M P M PWRTN# RSTTN# RT_RST# PWRG_S PWRG MEM_VL MP_VL/HT_VL PU_VL THERM_SI/GPIO_/MSM_LK THERM_SI/GPIO_/MSM_T THERM_LERT#/GPIO_/PWR_LE# FNRPM0/GPIO_0 FNTL0/GPIO_ FNTL/GPIO_ F F F Y MHZ MP_TI MP_TO MP_TMS MP_TRST# MP_TK XTL XTL U T T U T H H JTG_TI JTG_TO JTG_TMS JTG_TRST# JTG_TK XTLIN XTLOUT MPV_EN/HTV_EN PUV_EN SPI_S0/GPIO_0 SPI_LK/GPIO_ SPI_I/GPIO_ SPI_O/GPIO_ SUS_LK/GPIO_ UF_SIO_LK N M K K M J P J HTV_EN PU_VRON MP_GPIO0 MP_SPI_LK MP_SPI_O SUS_LK_R SIO_LK T T T HTV_EN,0 PU_VRON REV: elete T0 Strap pin only MP_TRST# MP_TO MP_TI MP_TMS MP_TK N 0 *NV_JTG 0 P_ LK_KX LK_KX H H XTLIN_RT XTLOUT_RT TEST_MOE_EN PKG_TEST P P0 TESTMOE_EN R *0M_ P_ SM/I PULL-UP PLK_SM PT_SM SM_LERT# MXM_PRESENT# :Z timing issue, modify to P : HNGE P FROM 0.U TO U FOR ELY HT_VL Y.KHz R0 R R0 R.K_.K_.K_ 00K_ R 0K_ R *0K_ V_S V_S R 0K_ R *0K_ MSM_LK MSM_T MXM_RUNPWROK PE_RESET_MXM_R# R0 IV^0K_ MP_GPIO0_I0 MP_GPIO_I MP_GPIO_I PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com R0 EV^0K_ R R R R.K_.K_ K_ *0K_ R K_ REV: Modify V??? HEK M I M/ I for "/" VPU I0 I I M/ 0 0 0 " 0 0 X 0 0 " 0 0 " U 0 " ual ore PU & MXM 0 " ual ore PU & UM " Single ore PU & UM HP -WIRE ROM ZY Modify R PLK_SM PT_SM *0K_ HP_WP U SL S WP TS00 R 0 0K_ y Jack Weng VPU.u/V_ Quanta omputer Inc. PROJET : ZY Size ocument Number Rev MP H/SM/PMU/GPIO/RT Friday, July, 00 ate: Sheet of V

MP POWER PLNE/ & YPSS UH FG-NVII-MP change footprint from 00 to 00 N_ORE 0.V~.0V 0m V 0.u/.V_ V_S 0m 0m.V_S 0.u/0V_.u/0V_.u/0V_.u/0V_ 0m U_.u/0V_ m V_UL VRT V_UL V W0 Y0 Y 0 V U/.V_0 u/.v_.u/.v_.u/.v_.u/0v_.u/0v_.u/0v_.u/0v_.u/0v_.u/0v_.u/0v_ Y0 U U Y W Y U V 0 0 u/.v_.u/.v_.u/.v_ U_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_.u/0V_ W W 0.V_UL V0 U_ R 0_ R 0_ VRT N.u/0V_.V_UL J G F H L L N N.u/0V_.u/0V_ UG FG-NVII-MP SE OF.V.V.V.V.V_UL.V_UL.V_VT.0V.0V0.0V.0V.0V.0V.0V.0V.0V.0V.0V.0V.0V0.0V.0V.0V.0V.0V.0V.0V.0V.0V.0V.0V.0V.0V.0V.0V.0V.V_UL.V_UL PWR/ H E Y M E U E V R N G Y F V M M F H E M F F V L P L V H N K M R H R G G J R M H U R R M N U J J J Y E Y N E H T J 0 N G G P T E J J U T0 M F J G E F F G E M R G N0 N M M V J L P H L M U U0 N M M G L SE OF T T J W M R V N M F N L G H N R R F H P E E V0 J N E E L J J E0 J G G0 V F F0 0 E V J F T J Y T Y P J E R N T P N RT RT_ONN 0MIL VRT_ R0 R RT_HG RT_HG Q K/F_ MMT0 RT_HG 0_ VPU R.K/F_ R 0K_ 0MIL R K_ VRT_ H00H VPU H00H *.u/v_ 0MIL VRT *.u/0v_ SM_INTRUER# RTRST# R R u/0v_ M/F_ 0K_ u/0v_ RTRST# G *SHORT P Quanta omputer Inc. PROJET : ZY Size ocument Number Rev MP POWER/ ate: Wednesday, May, 00 Sheet of PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com

G N,, MXM_PWREN MXM_PWREN MXM_T MXM_LK MXM_PWR_EN.V V Page : V PWREN#.V_MXM V_MXM *_EV^0u/V_0 VTHM_T VTHM_LK MXM_PWREN MXM_PWREN MXM_PWREN VG_THERM#.V V PWREN#.V_MXM V_MXM MXM circuit ZY no use it Q *_EV^FS R0 Q *_EV^FN_NL *_EV^K_ Q *_EV^N00E Q *_EV^N00E Q *_EV^N00E R *_EV^K_ R *_*EV^00K_ Q *_EV^FN_NL Q *_EV^FN_NL R VG_THERM# *_*EV^00K_ S 0 0 0 0 0 0 0 0 0 Q0 LVS_ULK# LVS_ULK LVS_UTX0# LVS_UTX# LVS_UTX# LVS_UTX# LVS_UTX0 LVS_UTX LVS_UTX LVS_UTX LVS_LLK# LVS_LLK LVS_LTX0# LVS_LTX# LVS_LTX# LVS_LTX# LVS_LTX0 LVS_LTX LVS_LTX LVS_LTX LVS_PPEN LVS_LEN LVS_L_RGHT _LK _T VG_HSYN VG_VSYN VG_RE VG_GREEN VG_LUE _LK _T TV_/HTV_Pr *_EV^O MXM_ *_EV^0.U/XR/0V_ TV_Y/HTV_Y/TV_VS TV_VS/HTV_Pb THERM# SM_T SM_LK *_EV^MXM_TYPEII 0 LVS RT TV VI / HMI VI- VI- *_EV^0u/V_0 *_EV^0.U/XR/0V_ HMI_VI LK# / VI LK# 0 HMI_VI LK / VI LK 0 HMI_VI TX0# / VI TX0# HMI_VI TX# / VI TX# HMI_VI TX# / VI TX# HMI_VI TX0 / VI TX0 HMI_VI TX / VI TX HMI_VI TX / VI TX HMI_VI HP / VI HP 0 _LK 0 _T P_L# / IGP/VI LK# P_L / IGP/VI LK P_L# / IGP/VI TX0# P_L# / IGP/VI TX# P_L0# / IGP_/VI TX# P_L / IGP/VI TX0 P_L / IGP/VI TX P_L0 / IGP_VI TX 0 0 P_HP / VI HP/ H_SI / IGP_RSV H_SO / IGP_RSV IGP_RSV / IGP P_UX#/VI T/IGP P_UX/VI LK/IGP IGP_RSV / IGP IGP_RSV / IGP IGP_RSV / IGP IGP_RSV / IGP IGP_RSV / IGP IGP_RSV / IGP *_*EV^0u/V_0 RSV RSV IGP_RSV / RSV IGP_RSV / RSV H_LK / RSV H_SYN / RSV RUNPWROK /TT# VI HP VI HP SIN_MXM R0 R0 Q R HEK IT Nvidia MXM VG R NEE TI MXM VG R NO NEE *_EV^TYU R R R *_EV^0_ *_*EV^S 0K *_*EV^0_ *_*EV^0K_ V K Q MXM_RUNPWROK *_EV^00K_ *_EV^00K_ *_EV^_ IN *_EV^N00E R0 V Z_SIN Z_SOUT_MXM Z_ITLK_MXM Z_SYN_MXM PWROK_E, Z_RESET#_MXM, *_EV^0u/V_0 *_EV^0.U/XR/0V_ V,0. *_EV^u/0V_ *_EV^.u/V_ V,. *_EV^0u/.V_ *_EV^.u/V_ *_EV^000p_.V,0. *_EV^u/0V_ *_EV^.u/V_ *_EV^000p_.V,. *_EV^0u/0V_ *_EV^0u/0V_ *_EV^.u/V_ dd H for MXM, 0/ lex *_EV^0K_ *_*EV^00u/.V_ IN, SPIF_MXM 0 0 MXM_ V_MXM V_MXM 0.V_MXM.V_MXM 0 0 0 0 0 0 0 0 0 0 00 0 N PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR PWR_SR VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN VRUN H_RST# / SPIF / *_EV^MXM_TYPEII LK_REQ# PEX_RST# PEX_REFLK# PEX_REFLK PEX_RX0# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX0# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX# PEX_RX0 PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX0 PEX_RX PEX_RX PEX_RX PEX_RX PEX_RX PEX_TX0# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX0# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX# PEX_TX0 PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX0 PEX_TX PEX_TX PEX_TX PEX_TX PEX_TX P P PRSNT# PRSNT# 0 0 0 0 00 0 0 0 0 0 0 0 0 R *_*EV^0_ LK_PIE_MXM# LK_PIE_MXM PEG_RXN0 PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN0 PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXN PEG_RXP0 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP0 PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_RXP PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN0 PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXN PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP0 PEG_TXP PEG_TXP PEG_TXP PEG_TXP PEG_TXP R PE0_PRSNTX_R R PE_RESET_MXM# PIE_RST0#, LK_PIE_MXM# LK_PIE_MXM PEG_RXN[:0] PEG_RXP[:0] PEG_TXN[:0] PEG_TXP[:0] *_EV^0_ MXM_PRESENT# PE0_PRSNTX# *_*EV^0_ Q *_EV^N00E REV:E change to PMOS V_ON MXM_PWR_EN MXM_PWR_EN MXM_RUNPWROK U *_EV^TSH0FU MXM_RUNPWROK Size ocument Number Rev MXM Quanta omputer Inc. PROJET : ZY Wednesday, May, 00 ate: Sheet of PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com

RT V V V_RT V.u/0V_ OK_INSERT_V 0 0 0 0 0 0 0 0 VG_RE_SYS VG_GRN_SYS VG_LU_SYS 0 0 0 LVS amera R0 0 RT_RE RT_GRN RT_LU V _PWR V.u/0V_ RT_R RT_G RT_ Page : R.K_ *0_.u/0V_ HMILK_ HMIT_ OK_INSERT_V RT_RE RT_GRN RT_LU OK_INSERT_V _L HMI circuit ZY no use it Q TEU R 0/F PWR L_ON RT_RE RT_LU _PWRON# R 0_ RT_GRN mil V _POWERON U SE EN# 00 0p_ U V_SYN V_ YP V_VIEO VIEO_ VIEO_ VIEO_.u/V_ R 0/F_, V M_HMI_LK RT_SENSE# M_HMI_T VSYN HSYN RTLK RTT RTLK_R RTT_R REV: Modify footprint for -test REV: MOIFY VG_RE_SYS VG_RE_OK VG_GRN_SYS VG_GRN_OK VG_LU_SYS VG_LU_OK V L_V VG_RE_SYS VG_GRN_SYS VG_LU_SYS RIGHTNESS V_RT _L _PWR V_RT _OUT RT circuit ZY no use it U SE EN# V 0 0 0 0 0 SYN_OUT SYN_OUT N R0 V 0 0 0 0 0 *_EZ^SNTLVPWR 0p_ M00 SYN_IN SYN_IN _IN _IN _OUT R0 R 0 0 0 0 L_ON0X 0u/V_0 R *_HMI^EZ^SNTLVPWR Q 0 R 0/F_ 0 0 0 0 L NZ^0_ 0u/V_0 RN L L L NZ^0_ NZ^0_ *0_ O0 0p_ NHW *LWHN00SQL VG_RE_OK VG_GRN_OK VG_LU_OK INT_TXULKOUT 0 INT_TXULKOUT- 0 INT_TXUOUT0 0 INT_TXUOUT0-0 INT_TXUOUT 0 INT_TXUOUT- 0 INT_TXUOUT 0 INT_TXUOUT- 0 RT_R RT_G RT_ INT_LVS_EIT 0 INT_LVS_EILK 0 RT_SEN# PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com HS_0/S HS_/S HS_/S HS_/S HS_0/S HS_/S HS_/S HS_/S *_EZ^.K_ *_*0_ HS_MS VSYN_ HSYN_ ONTRST INT_LVS_EILK INT_LVS_EIT HMILKN HMILKP HMITX0N HMITX0P HMITXN HMITXP HMITXN HMITXP HMILKP_ HMILKN_ HMITXP_ HMITXN_ HMITXP_ HMITXN_ HMITX0P_ HMITX0N_ HMILK HMIT HS_MS HS_0/S HS_/S HS_/S HS_/S HS_SEL_IN RT_SEN# RIGHTNESS OK_INSERT_V HMILKN_ HMILKP_ HMITX0N_ HMITX0P_ HMITXN_ HMITXP_ HMITXN_ HMITXP_ HMILK_ HMIT_ HMI_HP_ RT_VSYN_OK RT_HSYN_OK RT_T_OK *_HMI^.u/V_ *_HMI^.u/V_ M_HMITX *_HMI^.u/V_ *_HMI^.u/V_ M_HMITX# M_HMITX M_HMILK M_HMILK# M_HMITX M_HMITX# M_HMITX M_HMITX# M_HMITX0 M_HMITX0# OK_HMILK OK_HMILK# OK_HMITX OK_HMITX# OK_HMITX OK_HMITX# OK_HMITX0 OK_HMITX0# HS_SEL_IN 0 L_V_ON RT_VSYN 0 0 RT_HSYN 0 V_RT 0p_ 0p_ acklight ontrol.k_ RT circuit V RTLK 0 R R0.K_.K_.K_ V ZY no use it V RTT 0 R *_EZ^0_ RT_LK_OK V 0mil OK_HMI_LK OK_HMI_T SE L LM0SN 0. R0 R0.u/V_ 0_PR LM0SN 0..u/.V_ FUN US 0 H US R R LM0SN 0. 0p_ 0p_ 0K_ R 0_.u/V_ MIL V *0_.u/.V_ M00-0 have internal ohm R _ RIGHTNESS L EI SMus PU HMI V V 0 0p_ R R R R R R R0 R 0 V V R R SEL_IN H L MS H 0 0 0 0 0 0 0 0 0 0 0 R _ HMILKN HMILKP HMITX0N HMITX0P HMITXN HMITXP HMITXN HMITXP HMILK HMIT HMI_HP R *_EZ^H00H *_.u/0v_ *_.u/v_ *_*.K_ *_*.K_ *_*.K_ *_*.K_ *_EZ^0_ *_EZ^0_ *_EZ^0_ *_EZ^0_ FUN OK (port ) M (port ) FUN R0 *_*0_ N RT *_HMI^0K_ I ONTROL R R R R R R R R *_.u/v_ L OK (port ) 00 0p_ *_HMI^K_ *_HMI^0_ *_HMI^0_ *_HMI^*0_ *_HMI^0_ *_HMI^*0_ *_HMI^*0_ *_HMI^*0_ 0 *_.u/v_ R0 U P0 P Page : SL S HP OE# I_EN# RT_EN# REXT PRE R R 0_ R TEST TEST.K_ V[] V[] V[] V[] V[] V[] V[] V[] [] [] [] [] [] [] [] [] [] [0] *_EZ^0_ V V 0 SL_SINK S_SINK HP_SINK 0 0 *_HMI^PERIOM_PIVPLS U 0 0 0 R R0 0p_ V V V V V V V V REV: HNGE I 0 0- - - 0 LK LK- 0 0- - - LK LK- SL/S S/S MS 0 0/S /S /S /S TEST_OUT SEL_OUT N TEST_IN SEL_IN.K_ *_EZ^0_ *_EZ^0_ OE *_EZ^PIHMI Page : VI circuit ZY no use it *0U R *_EZ^.K_ R V R0 R V 000p_ V *_EZ^S *_*S *_EZ^0_ *_HMI^0K_ *_HMI^0K_ OK_HMILK OK_HMILK# OK_HMITX OK_HMITX# OK_HMITX OK_HMITX# OK_HMITX0 OK_HMITX0#,,,,,, V L_ON V V PT_SM MXM_T PLK_SM MXM_LK V M_HMITX# M_HMITX0 M_HMITX0# M_HMILK M_HMILK# HMI circuit ZY no use it R *_*.K_ 0 *_HMI^NHW HMI_HP_ OK_HMILK OK_HMITX OK_HMITX OK_HMITX0 OK_HMILK OK_HMITX OK_HMITX OK_HMITX0 R 00K_ 0 L_LON M_HMI_LK M_HMI_T R R R R R R Q PTTT V R 00K_ VPU LVS_LON HMI_HP_ V V *_EZ^00/F_OK_HMILK# *_EZ^00/F_OK_HMITX# *_EZ^00/F_OK_HMITX# *_EZ^00/F_OK_HMITX0# OK_HMILK# OK_HMITX# OK_HMITX# OK_HMITX0# V L# LON# HMIT HMILK LONG 0K_ L_ON V M_HMI_LK M_HMI_T HMI_HP_ M_HMITX M_HMITX# M_HMITX M_HMITX# M_HMITX0 M_HMITX0# M_HMILK M_HMILK# HMILKN_ HMILKP_ HMITX0N_ HMITX0P_ HMITXN_ HMITXP_ HMITXN_ HMITXP_ HMIT_ HMILK_ mil LV mil LISHG REV : R Modify connect to U pin0; add R connect from U pin to U Pin L. Page : VI circuit OK_INSERT_V ZY no use it Q *_EZ^N00E *_HMI^*0_ *_HMI^0_ *_HMI^.u/V_ *_HMI^.u/V_ *_HMI^.u/V_ R R *_HMI^*0_ *_HMI^0_ R 00K_ *_HMI^H00H Q *_HMI^*N00E 0 Q *_HMI^*N00E *_*EZ^.P/V_ *_*EZ^.P/V_ *_*EZ^.P/V_ *_*EZ^.P/V_ R R N *_HMI^0_ R 0K_ *_HMI^0_ R USP USP- USP- USP USP- USP INT_TXLOUT0 INT_TXLOUT0- INT_TXLOUT INT_TXLOUT- INT_TXLOUT INT_TXLOUT- INT_TXLLKOUT INT_TXLLKOUT- IN_ IN_- IN_ IN_- IN_ IN_- IN_ IN_- OUT_ OUT_- OUT_ OUT_- OUT_ OUT_- OUT_ OUT_- 0 0- - - LK LK- SHELL 0 Shield - Shield - 0 0 Shield 0- K K Shield K- E Remote N LK T V HP ET SHELL *_HMI^HMI ONN Q N00E *_HMI^*00K_ R R 0K_.0u/V_ *_HMI^*.K_ *_HMI^*.K_ Q N00E Q N00E R R Q N00E R R _ Q O0 S Q TEU Q0 *_HMI^SS S *_HMI^K_ E_FPK# V Page :VI circuit Q ZY no use it *_EZ^SS OK_VI_HP V V RN RN RN RN RN U.u/V_ V U V U L 0_ R V *_HMI^000p_ mil MP_LI# LI#, L_V HMI_HP_ M_HMI_LK M_HMI_T HMI_HP_ *_HMI^*Rlamp0M_G M_HMITX 0 0 M_HMITX# M_HMITX M_HMITX# *_HMI^*Rlamp0M_G M_HMITX0 0 0 M_HMITX0# M_HMILK M_HMILK#.0u/V_ *_HMI^NZ^0_PR M_HMILK# M_HMILK *_HMI^NZ^0_PR M_HMITX0# M_HMITX0 *_HMI^NZ^0_PR M_HMITX# M_HMITX *_HMI^NZ^0_PR M_HMITX# M_HMITX *_HMI^NZ^0_PR M_HMI_T M_HMI_LK Quanta omputer Inc. PROJET : ZY REV: Modify Size ocument Number Rev LVS/RT/TVOUT//VI ate: Wednesday, May, 00 Sheet of *_HMI^*Rlamp0M_G *_HMI^0K_ *_HMI^*.U/0V_ 0 0 0 *_HMI^000p_ 0 u/.v_ *_HMI^000p_

To NEW-R & EXT. US,, PT_SM,, PLK_SM, USON# USP- USP USP- USP USP- USP USP0- USP0 PPE#_E 0m.V PT_SM PLK_SM USON# USP- USP USP- USP USP- USP USP0- USP0 R VPU 0 0 0 0 0 0 0 0 N PPE# *_NEW^0_. m V V_S NEW^NEW R_ON0X REV: Modify PIE_RST# PPE# NEW_LKREQ# LK_PIE_NEW_# LK_PIE_NEW_ PIE_RXN PIE_RXP PIE_TXN PIE_TXP Fingerprint REV: Modify footprint for -test REV: Modify V VSUS L V Page : NEW R circuit ZY no use it Finger print circuit ZY no use it RN *_NEW^.u/.V_ R R *_FP^0_PR *_FP^*LWHN00SQL *_NEW^u/0V_ *_FP^*0_ *_FP^0_ N *_FP^Finger_H. *_NEW^.u/V_ luetooth T_POWERON# INT. US VSUS USP USP- T_LE Q *_T^O0 RN L Page : /T circuit ZY no use it T_POWER *_T^0_PR *_T^*LWHN00SQL 0mil USP USP- L 0mil USPWRP USPWR N TI00G RN *0_PR USP- USP- USP USP, USON# L 0p_ 0u/.V_X. REV: Modify SYUIN_US LWHN00SQL *_T^.u/.V_ N0 *_T^US_T_P USPWRP IR U *_IR^IR VPU R IR_V VPU *_IR^_ R *_IR^*_ *_IR^.u/V_ IRRX_ 0u/0V_ u/0v_ USON# Page : IR circuit ZY no use it VPU Q0 R OE# V Y VPU *_IR^*NSZPX U RTPF IN OUT IN OUT OUT EN# - O# *_IR^0_ R 0mil USPWR *.K/F_ IRRX MINI-R V_MINI R N *_MINI^0_ V_MINI.V _.Vaux _.V _.V _.Vaux _.V V_MINI_ R 0_ V_MINI USP- USP RN L *0_PR LWHN00SQL USP- USP N0 SYUIN_US 0p_ USP USP- USP USP- 0 REV: Modify RF_LE# R *_MINI^0_ RF_LE#_ USP R *_MINI^0_ USP_ USP- R *_MINI^0_ USP-_ MINI_SMT MINI_SMLK PIE_TXP PIE_TXN PIE_RXP PIE_RXN PIE_RST# LK_PIE_TV LK_PIE_TV# PIE_WKE_WL_R_# WKE_WL_# R 0_.V 0 USP USP- PIE_TXP PIE_TXN PIE_RXP PIE_RXN PIE_RST# LK_PIE_TV LK_PIE_TV# TV_LKREQ# _LE_WPN# _LE_WLN# _LE_WWN# _US US_- _SM_T _SM_LK _PETp0 _PETn0 _PERp0 _PERn0 _PERST# _REFLK _REFLK- _LKREQ# _WKE# _LE_WPN# _LE_WLN# _LE_WWN# _US US_- _SM_T _SM_LK _PETp0 _PETn0 _PERp0 _PERn0 _PERST# _REFLK _REFLK- _LKREQ# _WKE# 0 0 RF_LE#_ USP0_ USP0-_ MINI_SMT MINI_SMLK PIE_TXP PIE_TXN PIE_RXP PIE_RXN PIE_RST# LK_PIE_MINI LK_PIE_MINI# WKE_WL_# R.V R0 0_ R 0_ R 0_ PIE_WKE_WL_R_# *_MINI^0_ ZY modify RF_LE# USP0 USP0- PIE_TXP PIE_TXN PIE_RXP PIE_RXN PIE_RST# LK_PIE_MINI LK_PIE_MINI# MINI_LKREQ# Jack W V R 0_ V for WWN card is. V_MINI.u/.V_.V V.u/.V_ R0.u/.V_ *_MINI^0_ 00m, mil V_TV-R REV: Modify V_MINI_.u/V_.u/V_.u/V_ V.u/V_ MLVG00R MLVG00R MLVG00R MLVG00R.u/.V_.u/V_ R0 0K_ V_MINI_.u/V.V _.V _.V _.V _.V _.V.u/V_.u/V_.u/.V_ *_MINI^.u/.V_,, PT_SM *_MINI^.u/V_ Q N00E MINI_SMT,,,,,, LFRME# L L L L0 ebug, LP_RST_E# LP_LK_EUG R R R00 R R0 R0 R0 V_MINI *_MINI^0_ *_MINI^*0_ *_MINI^*0_ *_MINI^*0_ *_MINI^*0_ *0_ *0_ R0 TV use V LFRME#_R_ L_R_ L_R_ L_R_ L0_R_ LP_RST_E#_R_ LP_LK_EUG_R_ *_MINI^0_ V_MINI_R_ 0 N N N N N N -Link_RST -Link_T -Link_LK N N N N N N 0 N N 0 -Link_RST -Link_T -Link_LK N N V_MINI_R_ LFRME#_R_ L_R_ L_R_ L_R_ L0_R_ LP_RST_E#_R_ LP_LK_EUG_R_ R R 0_ R *0_ R *0_ R *0_ R *0_ R R *_MINI^*0_ *_MINI^*0_ V_MINI *_MINI^*0_ LFRME#,, L, L, L, L0, ebug LP_RST_E#, LP_LK_EUG,, PIE_WKE# VSUS Q *TEU R.K_ PIE_WKE_WL_R_# Page : UL MINI R circuit ZY no use it,, PLK_SM V R R *0_ *0_ R0 0K_ Q N00E MINI_SMLK RF_EN V_TV-R R R0 TV use V *_MINI^*0_ *_MINI^0_ *_MINI^.u/V RF_EN Page : UL MINI R circuit ZY no use it V_TV-R_R_ N N _W_ISLE# _T_HLK _T_T _W_ISLE# _T_HLK _T_T SP@QUSR-00-0N_P N N 0 0 0 _RF_EN V_TV-R_R_ *_MINI^*.u/V_ R0 0_ R RF_EN V_TV-R *_MINI^*0_ REV: Modify RF_EN ZY test has modified to single stack no TV card, only Wireless card PITOR on Module *0P_ R *_ LP_LK_EUG For EMI ouble Stack MINI R MOULE '' TV card MOULE '' Wireless card Quanta omputer Inc. PROJET : ZY Size ocument Number Rev NEW&MINI&TV R/US/T/IR Thursday, July, 00 ate: Sheet of PF created with FinePrint pdffactory Pro trial version http://www.fineprint.com

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