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YTEM PE REF. PE ontent lock iagram ystem etting PU()_MI,PE,FI,LK,MI PU()_R PU()_F,RV, PU()_PWR PU()_XP R OIMM_0 R OIMM_ R _Q VOLTE VI controller 0 PH_IEX()T,IH,RT,LP PH_IEX()_PIE,LK,M,PE PH_IEX()_FI,MI,Y PWR PH_IEX()_P,LV,RT PH_IEX()_PI,NVRM,U PH_IEX()PU,PIO,MI PH_IEX()_POWER, PH_IEX()_POWER, PH_PI ROM,OTH LK_ILR 0 E_IT(/) E_IT(/)K, TP RT_Reset ircuit LN_R LN_RJ Hybrid witch OEL U_mp & Jack ET 0 _U _Neward U_ebug RT_L Panel RT_ub TV_HMI 0 FN_Fan & ensor X_H & O U_U Port * MINIR(WLN) TUN_TV Tuner LE_Indicator _ischarge PW_PROTET 0 _ & T onn. T_luetooth U & udio Jack OR POWER OR FUNTION OR ME_onn & kew Hole NE U.0 0 V_Madison NJv HEMTI Revision.0 HMI Page RT NJv LOK IRM Page L Panel Page Touchpad Page Keyboard Page INT. MI Page HMI Int.peaker Page HP/PIF.JackPage MI.Jack Page RT H Page O Page et Page NPV LV ebug onn. E ITE IT0 zalia odec Realtek L Port.0 Port. Port. Page 0 LV RT HMI Page Page 0 Page PIE x LP zalia T PU rrandale FI x PH Ibex PeakM HM U Port.0 Port. Port. Port. Port. Port. Port. Port. Port. Port. Port.0 Port. Port. Port. Page ~ MI x Page 0~ Function U port (IO/) U port(io/) U port.0/.0 R 00/0MHz R 00/0MHz PIE x ard Reader(.0) Page 0 TV turner Newcard annot use annot use WiFi/WiMax amera T (.) Page Page Page Page Page Page Page Page U.0 Port. Port. Port. Port. Port. R OIMM0 lave dd. 0 Page ~ R OIMM lave dd. Page ~ PI ROM Mbit TVF0 Page NE UP000F U.0 igaln RPage Page RJ Page Power VORE ystem.v &.0V R & VTT +.V harger etect Load witch Power Protect Page 0 Page Page Page Page Page Page 0 Page Page 0 0 PW_VORE(MX0) PW_YTEM(MX00) PW_I/O_VTT_PU&+.VM PW_I/O_R & VTT& +.V PW_I/O_VM & ME_+VM_PWE PW_+VFX_ORE(MX0) PW_HRER(MX0) PW_ETET PW_LO WITH PW_INL PW_FLOWHRT PWM Fan Page 0 OR_LK_PH _REF_LK_PH M_/No_LK_PU Reset ircuit Page lock enerator I ILR lave dd. Page ischarge ircuit & TT. onn. Page Page 0 LK_PH MI_LK_PH T_LK_PH kew Holes Page lock iagram yunfeng_yan UTeK OMPUTER IN. N NJv.0 Thursday, ecember, 00 ate: heet of

PH_IEX PIO PH_IEX PIO Use s ignal Name PIO 00 PO N_TP PIO 0 PO N_TP PIO [:] PI PI_INT[E:H]# PIO 0 PO N_TP PIO 0 PO N_TP PIO 0 PI EXT_MI# PIO 0 Native N_PU PIO 0 Native N_PU PIO PI EXT_I# PIO Native N_TP PIO PO N_TP PIO PO N_PU PIO PO T_LE PIO PI PU_HOL_RT# PIO PI PU_PWROK PIO PI LKREQ#_TV PIO PI TP PIO 0 Native LKREQ#_WLN PIO PI T0P PIO PO WLN_LE PIO Native N_TP PIO PO N_TP PIO PI LKREQ#_NEWR PIO PI LK_REQ#_ PIO PO N_TP PIO PO WLN_ON# PIO Native N_TP PIO 0 PO ME_usPwrnck PIO Native ME PREENT PIO PIO PM_LKRUN# PIO PI H_OK_EN# PIO Native N_TP PIO PO T_LK_REQ# PIO PI PU_PWR_EN# PIO PI PU_PRNT# PIO PI P_I0 PIO PI P_I PIO 0 Native N_PU PIO Native N_PU PIO Native N_PU PIO Native N_PU PIO Native LK_REQ# PIO Native N_TP PIO Native N_TP PIO PI LKREQ_PE# PIO PO N_TP PIO PIO PH_TEMP_LERT# PIO 0 Native PI_REQ# PIO Native PI_NT# PIO Native PU_ELET#_R PIO PO PU_PWM_ELET# PIO Native PI_REQ# PIO Native PI_NT# PIO PI LKREQ_LN# PIO PO T_ON PIO PIO ML_LK PIO Native N_PU PIO 0 Native ML0LERT# PIO Native N_TP PIO Native N_TP PIO Native N_TP PIO Native N_TP PIO Native N_TP PIO Native N_TP PIO Native EI_ELET# PIO Native PM_TLOW# PIO Native LK_REQ0# PIO Native MLLERT# PIO PIO ML_T Internal & External Power Pullup/down +V INT T +V EXT PU +V INT T +V INT T +V EXT PU & INT PU +VU EXT PU +VU EXT PU +VU EXT PU +VU +VU +VU EXT PU +VU INT P +VU EXT PU +V EXT P & INT T +V EXT P +V EXT PU +V EXT P +V EXT PU +V EXT P +V INT PU +V +VU EXT P +VU EXT P +VU INT WEK PU +VU EXT P +VU EXT PU(NI)/P(NI) +VU EXT PU +VU EXT PU +VU EXT PU +V +V +V EXT P +V EXT PU +V EXT PU +V EXT P +V EXT P +V EXT PU +VU EXT PU +VU EXT PU +VU EXT PU +VU EXT PU +VU EXT PU +VU EXT PU +VU EXT PU +VU +V EXT PU +V EXT PU INT PU EXT PU INT PU EXT PU INT PU EXT P EXT PU(IOE) EXT PU EXT PU EXT PU INT T INT T INT T INT T EXT PU EXT PU EXT PU EXT PU +V +V +V +V +V +V +VU +VU +VU +VU +VU +VU +VU +VU +V +V +V +V +VU +VU +VU +VU E IT E PIO Use s ignal Name E IT0 R. removed P0 O PWR_LE# E PIO Use s ignal Name P O H_LE# PIO0 I ME_PM_LP_M# P PIO I ME_usPwrnck P PIO P O L_L_PWM PIO P O FN0_PWM PIO I ME_+VM_PWR P PIO I ME_PM_LP_LN# P PIO O ME PREENT P0 O TEL_0 PIO P O TEL_ PIO P ME PREENT_E PIO P IO M0_LK PIO0 P IO M0_T PIO P O 0TE PIO O ME_PWROK P O RIN# PIO P O PM_RMRT# PIO O ME_LP_M_E# P0 PIO P IO M_LK PIO P IO M_T PIO P O PM_PWRTN# PIO P I _IN_O# PIO P O OP_# PIO0 P I T_IN_O# PIO P I RFON_W# PIO P0 I PWRLIMIT# PIO P I PM_U# PIO P I UF_PLT_RT# PIO P O EXT_I# PIO P O EXT_MI# PIO P O L_KOFF# PIO P I FN0_TH PIO P PIO0 PE0 O VU_ON PIO PE O E (IT0 ddress/ata connect) PIO PE O E (IT0 ycle tart connect) PIO PE O ELK (IT0 lock connect) PIO PE I PWR_W# PIO PE PIO PE I LI_W# PIO PE PF0 O M_U RE : PF PH Master PF I EXP_TE# Mus evice Mus ddress PF lock enerator(ilr) 000x ( ) PF I TP_LK OIMM 0 00000x ( 0 ) PF IO TP_T OIMM 0000x ( ) PF O THRO_PU VI ontroller(m) 000x ( ) PF O PH_PI_OV WiFi/WiMax N/ P0 I ME_UPWRNK_E E Master (M) P I PM_U# Mus evice Mus ddress P PU Thermal ensor() 0000x ( ) P V Thermal I() 000x ( E ) PH0 IO PM_LKRUN# PH O FX_VR_ON evice Identification PH O H_EN PU Thermal ensor P/N: component name PH O U_E# st 0000 F PH O U_E# PH O NUM_LE# PH O P_LE# PI0 PI I U_PWR lock en P/N: component name PI I LL_YTEM_PWR st 00000 ILR PI I VRM_PWR PI I PH_TEMP_LERT# PI I L_ V Thermal ensor component name PI I P_K_# st 00000 PI I P_K_# PJ0 O PU_VRON PJ O PM_PWROK PJ O VET_E PJ O IET_E PJ O TP_LE PJ PIE Minicard TV Tuner PIE Minicard WLN PIE Newcard PIE PIE ard reader PIE LN PIE PIE T 0 T H () T T O T T H () T ET U 0 U Port () U U Port () U U Port () U U Port () U Minicard TV Tuner U Neward U U U WLN U MO amera U 0 U U luetooth U Finger Printer ystem etting yunfeng_yan UTeK OMPUTER IN. N NJv.0 Wednesday, November, 00 ate: heet of

JT MPPIN FI_FYN0 FI_FYN FI_LYN0 FI_LYN FI_INT XP_TI_R XP_TO_M XP_TI_M XP_TO_R FI disable: (For discrete graphic). N: FI_TX#[0:],FI_TX[0:],FI_RX#[0:],FI_RX[0:] V_XENE,V_XENE. Pulldown to via K % resistor: FI_FYN[0:],FI_LYN[0:],FI_INT,FX_IMON ~mw power saving.( R0. P.0). onnected to : VX,. an be connected to directly: PLL_REF_LK,PLL_REF_LK#. onnect to +V.0 rail: VFIPLL R0 L0 00 R00 R0 L0 00 KOhm KOhm KOhm KOhm KOhm R0 R0 R0 R0 R0 R. P.: *FI_FYN[0],FI_FYN[], FI_LYN[0], FI_LYN[] can be ganged together with one resistor. *On the other hand,fi_fyn[0], FI_FYN[], FI_LYN[0], FI_LYN[], and FI_INT signals on PH side can be left as no connect without any power or functional impact. XP_TI XP_TO R00,R0,R0 near U00 FI_TXN[:0] FI_TXP[:0] MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FI_FYN0 FI_FYN FI_INT FI_LYN0 FI_LYN For Intel FX display FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP F H F E E E F 0 E0 F0 F E F 000 U00 MI_RX#[0] MI_RX#[] MI_RX#[] MI_RX#[] MI_RX[0] MI_RX[] MI_RX[] MI_RX[] MI_TX#[0] MI_TX#[] MI_TX#[] MI_TX#[] MI_TX[0] MI_TX[] MI_TX[] MI_TX[] FI_TX#[0] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX#[] FI_TX[0] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_TX[] FI_FYN[0] FI_FYN[] FI_INT FI_LYN[0] FI_LYN[] OKET MI Intel(R) FI PI EXPRE RPHI PE_IOMPI PE_IOMPO PE_ROMPO PE_RI PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[0] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX#[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[0] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_RX[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[0] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX#[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[0] PE_TX[] PE_TX[] PE_TX[] PE_TX[] PE_TX[] KTO#:pulled to ground on processor. may use to determine if PU is present K J J F F E 0 J H H F E F F 0 0 L M M M0 L K M J K H0 H F E L M M L0 M K M H K 0 F E PE_IROMP_R EXP_RI PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN0 PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXN PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP0 PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_RXP PIEN_TXN0 00 PIEN_TXN 00 PIEN_TXN 00 PIEN_TXN 00 PIEN_TXN 00 PIEN_TXN 00 PIEN_TXN 00 PIEN_TXN 00 PIEN_TXN 00 PIEN_TXN 00 PIEN_TXN0 0 PIEN_TXN 0 PIEN_TXN 0 PIEN_TXN 0 PIEN_TXN 0 PIEN_TXN 0 PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP0 PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP PIEN_TXP R00 R00 0 0 0 00 0 0 0 0 0 0 0 0 0 00 0 0 % % 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V.Ohm PIE_RXN0 PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN0 PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXN PIE_RXP0 PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP0 PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIE_RXP PIEN_RXN[:0] 0 PIEN_RXP[:0] 0 PIE_RXN[:0] 0 PIE_RXP[:0] 0 RMPWROK: (U R.) VPWROO_R R.,item +.V R00.KOhm % R0.0KOHM % Main oard 0,0 0 THRO_PU,,,0,,,0,,,,,0 H_THRMTRIP# H_PURT# PM_YN# H_PUPWR H_RM_PWR H_VTTPWR H_PWR_XP UF_PLT_RT# % R00 % R00.Ohm % R00.Ohm % R00 R0 H_OMP H_OMP H_OMP H_OMP0 T00 TP_KTO# H +VTT_PU For E request, to read PEI via E..Ohm % R00 H_TERR# K onnection: R0.>Q00.>U00. THRO_PU R0 +VTT_PU H_PEI_IO H_PEI T R00 don't remove R0 OHM PWRLIMIT# 00 RV0 H_PROHOT_# H_PROHOT_#_R N R00 Q00 N00 T0 H_THRMTRIP#_R PM_YN#_R VPWROO R L00 00 T0 VPWROO_0_R L0 00 T0 VPWROO_R L0 00 T0 L0 00 R0.KOhm % PLT_RT#_R T0 T T T K P L N N K M M L U00 OMP OMP OMP OMP0 KTO# TERR# PEI PROHOT# THERMTRIP# REET_O# PM_YN VPWROO_ VPWROO_0 M_RMPWROK VTTPWROO TPPWROO RTIN# MI THERML PWR MNEMENT LOK R MI JT & PM LK LK# LK_ITP LK_ITP# PE_LK PE_LK# PLL_REF_LK PLL_REF_LK# M_RMRT# M_ROMP[0] M_ROMP[] M_ROMP[] PM_EXT_T#[0] PM_EXT_T#[] LK_PU_LK LK_PU_LK# R0 LK_ITP_LK_R T0 LK_ITP_LK#_R E F L M N N P LK_EXP_P LK_EXP_N LKREF LKREF# M_ROMP0 R0 % M_ROMP R0 % M_ROMP R0 % PM_EXTT# +VTT_PU RN00 RN00 PRY# T PREQ# P TK N TM P TRT# T XP_TI_R TI T XP_TO_R TO R XP_TI_M TI_M R XP_TO_M TO_M P H_R#_R R# N PM#[0] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] PM#[] J K K J J H K H T0 L0 00 L0 00 L0 00 L0 00 L0 00 L0 00 R0 R00 0KOHM 0KOHM T0 0.Ohm T0 T0 T T T R0 XP_O0 XP_O XP_O XP_O XP_O XP_O XP_O XP_O LK_PU_P_PH LK_PU_N_PH LK_ITP_LK LK_ITP_LK# LK_MI_PH LK_MI#_PH LK_REF LK_REF# 0MHz from PH. M_RMRT#, PM_EXTT#0, XP_PRY# XP_PREQ# XP_TLK XP_TM XP_TRT# XP_REET#, XP_O[:0] H_PURT# XP_TM XP_TI_R XP_PREQ# XP_TLK XP_TRT# LKREF LKREF# +VTT_PU R0 OHM R0 Ohm R0 Ohm R0 Ohm R0 Ohm R0 Ohm R0 R R.0 R0 % OKET UTeK OMPUTER IN. N MI,PE,FI,LK yunfeng_yan NJv Friday, ecember, 00 ate: heet of.0

Main oard U00 U00 M Q[:0] M 0 M M M # M R# M WE# M Q0 0 M Q 0 M Q M Q M Q 0 M Q 0 M Q E0 M Q M Q M Q F0 M Q0 E M Q F M Q E M Q M Q E M Q M Q H0 M Q M Q K M Q J M Q0 M Q 0 M Q J M Q J0 M Q L M Q M M Q M M Q L M Q L M Q K M Q0 N M Q P M Q H M Q F M Q K M Q K M Q F M Q M Q J M Q J M Q0 J0 M Q J M Q L0 M Q K M Q K M Q L M Q K M Q L M Q N M QM0 M Q0 R M Q L M Q M M Q N M Q T M Q P M QM M Q N M QM M Q T M Q0 T M Q L M Q R M Q P U E E _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _[0] _[] _[] _# _R# _WE# R YTEM MEMORY _K[0] _K#[0] _KE[0] _K[] _K#[] _KE[] _#[0] _#[] _OT[0] _OT[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _Q#[0] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[0] _M[] _M[] _M[] _M[] _M[] P Y Y P E E F H M M N0 N M M0 M M M M M M M M M M M M M M F J M Q#0 M Q# M Q# N M Q# H M Q# K M Q# P M Q# T M Q# F H M H K0 N R Y W V V T Y U T U T V M Q0 M Q M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M M 0 M M M M M M_LK_R0 M_LK_R#0 M_KE0 M_LK_R M_LK_R# M_KE M_#0 M_# M_OT0 M_OT M M[:0] M Q#[:0] M Q[:0] M [:0] M Q[:0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M 0 M M M # M R# M WE# E F F F F H J J J J J K L M K K M N F J K J H K K M N K K M M P N T N N N T T N P P T T P R0 T0 W R Y _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[0] _Q[] _Q[] _Q[] _[0] _[] _[] _# _R# _WE# R YTEM MEMORY _K[0] _K#[0] _KE[0] _K[] _K#[] _KE[] _#[0] _#[] _OT[0] _OT[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _Q#[0] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q#[] _Q[0] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _Q[] _M[0] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[] _M[0] _M[] _M[] _M[] _M[] _M[] W W M V V M E H K H L R T F J L H L R R E H M L P R U V T V R T R R R R P R F P N M M0 M M M M M M M M M M M M M M M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M Q0 M Q M Q M Q M Q M Q M Q M Q M 0 M M M M M M M M M M 0 M M M M M M_LK_R M_LK_R# M_KE M_LK_R M_LK_R# M_KE M_# M_# M_OT M_OT M M[:0] M Q#[:0] M Q[:0] M [:0] OKET OKET UTeK OMPUTER IN. N ustom NJv PU()_R yunfeng_yan ate: Friday, ecember, 00 heet of.0

U00E P RV L RV L RV L RV J RV RV M RV L 0mil trace RV IMM0_VREF_Q J 0mil trace RV IMM_VREF_Q H RV0 RV RV E RV E0 RV F0 M0 T0 F F[0] M T0 F F[] P F F[] L F F[] L0 T0 F F[] M T0 F F[] N F F[] M T0 F F[] K T00 F F[] K T0 F0 F[] K T0 F F[0] J T0 F F[] N0 T0 F F[] N T0 F F[] J T0 F F[] J T00 F F[] J0 T0 F F[] K0 T0 F F[] H F[] RV RV R00 H_RV_R 0 R00 H_RV_R RV 0 RV U RV T RV0 RV RV T0 T00 RV RV J RV J RV T0 T0 RV RV T0 T0 RV0 RV REERVE RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV RV RV RV RV0 RV RV RV RV RV RV J J H K L R J J P T T R L L P0 P L T T P R T T P R R E F J RV_R H RV_R R R E V V N W W N E P T00 T00 T00 T00 T00 T00 T00 T00 T00 R00 R00 U00H T0 V T V R V R V R V R V R V R0 V R V R V0 R V R V R V R V P0 V P V P V P0 V P V P V0 P V N V N V N V N0 V N V M V M V M V M0 V0 M V M V M V M V M V M V L V L V L V L0 V0 L V L V L V L V L V K V K V K V K0 V K V0 J V J V J0 V J V J V J V J V J V J V H V0 H V H V H V H V H0 V H V H V H V H V H0 V0 H V H V H V H V H V 0 V F V F V F V E V0 V V V V V V V V V V V0 V V V V V V V V V V00 V0 V0 V0 V0 V0 V0 V0 V0 V0 V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 V V V V V V V V V V0 E E E E E0 E E E E E 0 0 0 Y Y Y W W W W W W0 W W W W W V0 U U U T T T T T T0 T T T T T R0 P P P N N N N N N0 N N N N N M0 L L L L L L K K K0 U00I K V K V K V K V J V J0 V J V J V H V H V0 H V H V H V H V H V H V H V H V H V H V0 H V V V 0 V V V V F0 V F V F V0 F V F V F V E V E V E V E V E V E V E V00 E V0 E V0 E V0 E V0 V0 0 V0 V0 V0 V0 V0 V V V V V V 0 V V V V0 V V V V V V V V V V0 V V V V NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF T T R Main oard T0 T0 T0 T0 OKET OKET OKET F strapping information: F[:0]: PI Express Port ifurcation (larksfield Only) : x PE (efault) 0 : x PE F[]: PIE tatic Numbering Lane Reversal (uburndale Only) : Normal Operation (efault) 0 : Lane Numbers Reversed F[]: Embedded isplayport etection (uburndale Only) : isabled No Physical isplay Port attached to ep 0 : Enabled n external isplay Port device is connected to ep F[]: Fixed for PI Express.0 jitter specifications (larksfield) only for early samples pree : onnect to with.0k Ohm % resistor F0 F F F R0 R0 R0 R0.0KOHM %.0KOHM %.0KOHM %.0KOHM % * Note: uburndale Hardware traps are sampled on asserting edge of VPWROO_0 and VPWROO_ and latched inside the processor. larksfield Hardware traps are sampled after RTIN# deassertion. UTeK OMPUTER IN. N ustom NJv F,RV, yunfeng_yan Friday, ecember, 00 ate: heet of.0

dd Jumper to measure power? +VFX_ORE U00 Main oard +VORE U00F V V V V V 0 V V V V V0 F V F V F V F V F V F0 V F V F V F V F V0 V V V V V 0 V V V V V0 V V V V V 0 V V V V V0 V V V V V 0 V V V V V0 Y V Y V Y V Y V Y V Y0 V Y V Y V Y V Y V0 V V V V V V V V V V V0 V V V V V V V V V0 U V U V U V U V U V U0 V U V U V U V U V0 R V R V R V R V R V R0 V R V R V R V R V0 P V P V P V P V P V P0 V P V P V P V P V00 PU ORE UPPLY POWER ENE LINE PU VI.V RIL POWER VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT PI# VI[0] VI[] VI[] VI[] VI[] VI[] VI[] PRO_PRLPVR VTT_ELET IENE V_ENE V_ENE VTT_ENE V_ENE_VTT H H H H0 J J H H F F F F E E F0 E0 0 0 Y0 W0 U0 T0 J J J J N K K K L L M M M N J J PM_PRLPVR_R T0 T0 0UF/.V 00 0UF/.V 00 0UF/.V 00 0UF/.V 00 0UF/.V 00 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 +VTT_PU 0UF/.V 0 0UF/.V 0 0UF/.V 0 UF/.V 0 L00 00 0 UF/.V Intel use u VR_VI0 VR_VI VR_VI VR_VI VR_VI VR_VI VR_VI L00 00 R00 R00 I_MON VENE 0 0 VENE +VTT_PU PM_PI# +VTT_PU PRLPVR H_VTTVI +VORE E0 00UF/.V ER=mOhm/Ir=. + UF/.V 00 UF/.V 0 +VTT_PU R0.,P +VTT_PU UF/.V 0 UF/.V 0 0UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 Intel use u Processor ecoupling +VORE UF/.V 0 UF/.V 0 UF/.V 0 0UF/.V 00 ecoupling guide from Intel WW0: T T T T R R R R P P P P N N N N M M M M L L L L K K K K J J J J H H H H J J H K J J J H F E E VORE uf * pcs 0 UF/.V 0uF* pcs( no stuff). 0 UF/.V VX VX VX VX VX VX VX VX VX VX0 VX VX VX VX VX VX VX VX VX VX0 VX VX VX VX VX VX VX VX VX VX0 VX VX VX VX VX VX VTT VTT VTT VTT VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT OKET 0 UF/.V FI PE & MI RPHI 0 UF/.V POWER ENE LINE RPHI VIs R.V RIL.V.V VX_ENE VX_ENE FX_VI[0] FX_VI[] FX_VI[] FX_VI[] FX_VI[] FX_VI[] FX_VI[] FX_VR_EN FX_PRLPVR FX_IMON VQ VQ VQ VQ VQ VQ VQ VQ VQ VQ0 VQ VQ VQ VQ VQ VQ VQ VQ VTT VTT0 VTT VTT VTT VTT VTT VTT VTT VTT VPLL VPLL VPLL chematic hecklist R0.: R T VORE uf * pcs 0uF * pcs 0uF* pcs( no stuff). 0 UF/.V 0 UF/.V V_X_ENE V_X_ENE VR_VI[0:] M VR_VI0 P VR_VI N VR_VI R00@: R has.k pulldown. P VR_VI M VR_VI R00.KOhm R0 P VR_VI N VR_VI R0 R0 R FX_VRON_EN T FXVR_PRLPVR_R R00 M VR_PWR_MON R00.KOhm J F E E Y W W U T T P N N L H P0 N0 L0 K0 J J0 J H H0 H L L M 0 UF/.V 0 UF/.V R0 UF/0V 0 UF/0V 0 UF/0V 0 UF/0V 0 UF/0V 0 0 0UF/.V UF/.V 0 VR_PWR_MON KOhm +VTT_PU +VTT_PU Intel use u 0 0UF/.V UF/.V 0 UF/0V 0 UF/0V 0.UF/0V 0.UF/.V 0 UF/.V 0 UF/.V 0 UF/.V 0 +.V +.V R0.,P xbuck tuffing option UF/.V 0 R0 R0 0UF/V E00 PNONI/EEFX0XE ER=mOhm/Ir= + +VTT_PU 0KOhm FX_VR_ON, FX_VR 0 FXVR_PRLPVR Intel.V P. u: /.u: /.u: / 0u:/ 0 0 0 UF/.V UF/.V UF/.V OKET / delete 0 (UF,.V) for layout placement. (+.V,VPLL) 0 00 0 0 0 0 0 0 UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V 0 0 00 0 0 0 0 UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UF/.V UTeK OMPUTER IN. N PU()_PWR yunfeng_yan NJv Tuesday, ecember, 00 ate: heet of.0

+VTT_PU, H_PUPWR PM_PWRTN#_R H_PWR_XP XP_PREQ# XP_PRY# XP_O0 XP_O XP_O XP_O T0 T0 XP_O XP_O XP_O XP_O XP_O XP_O0 KOhm /ITP R00 PUPWR_XP /ITP R0 PM_PWRTN#_XP /ITP R00 PIE_LK_XP_P PIE_LK_XP_N T00,,,,, M_T_,,,,, M_LK_ XP_TLK J00 0 0 0 0 0 0 0 0 0 0 0 0 NP_N NP_N to_on_0p XP_O XP_O XP_O XP_O XP_O0 XP_O XP_O XP_O XP_O XP_O XP_O XP_O LK_ITP_LK_XP R00 /ITP LK_ITP_LK#_XP R0 /ITP XP_RT#_R T00 T0 T00 T00 T00 T00 T0 T0 T00 T00 T00 T00 KOhm /ITP R00 XP_TRT# XP_TI XP_TM LK_ITP_LK LK_ITP_LK# H_PURT# +VTT_PU R0 /ITP Ohm XP_REET#, XP_TO /ITP XP_RT#_R R0 UF_PLT_RT#,,0,,,0,,,,,0 PU XP connector UTeK OMPUTER IN. N ustom PU()_XP Yunfeng_yan NJv ate: Friday, ecember, 00 heet of.0

UTeK OMPUTER IN. N N_**** H_Lin ustom NJ ate: Wednesday, November, 00 heet of.0

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Main oard UTeK OMPUTER IN. N N_**** H_Lin ustom NJ ate: Wednesday, November, 00 heet of.0

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UTeK OMPUTER IN. N NJ H_Lin ate: Wednesday, November, 00 heet of.0

UTeK OMPUTER IN. N NJ H_Lin ate: Wednesday, November, 00 heet of.0

M M M M M M M M M M M M M M M M0 M Q M Q# M Q M Q M Q M Q# M Q M Q# M Q# M Q M Q# M Q#0 M Q M Q# M Q0 M Q# M M M M M M M 0 M M M M M 0 M M M M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q0 M M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q0 M Q M Q M [:0] M Q[:0] M_LK_R0 M_KE0 M_LK_R# M_LK_R M_KE M # M_LK_R#0 M M 0 M M M[:0] M Q#[:0] M Q[:0] M_T_,,,,, M_LK_,,,,, M WE# PM_EXTT#0, M_# M R# M_#0 M_OT0 M_OT M_RMRT#, +V +.V +0.V M_VREF_IMM0 M_VREFQ_IMM0 +0.V +.V +.V ate: heet of ustom Friday, ecember, 00 UTeK OMPUTER IN. N R OIMM_0.0 NJv yunfeng_yan ate: heet of ustom Friday, ecember, 00 UTeK OMPUTER IN. N R OIMM_0.0 NJv yunfeng_yan ate: heet of ustom Friday, ecember, 00 UTeK OMPUTER IN. N R OIMM_0.0 NJv yunfeng_yan REV.mm Mus lave ddress: 0H Layout Note: Place these caps near O IMM 0 Layout Note: Place these caps near O IMM 0 R. R. 0 000.UF/0V.UF/0V 0 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V R0 0KOhm R0 0KOhm.UF/0V.UF/0V 0 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V UF/0V UF/0V 0 0/P 0 /# 0 0 0 0 0 # K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q Q#0 0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q J0 R_IMM_0P J0 R_IMM_0P 0UF/.V 0UF/.V UF/0V UF/0V 0.UF/V 0.UF/V 0 0UF/.V 0 0UF/.V R0 0KOhm R0 0KOhm.UF/0V.UF/0V 0 0.UF/V 0 0.UF/V R0 R0 0 0UF/.V 0 0UF/.V 0UF/.V 0UF/.V UF/0V UF/0V 0 0.UF/V 0 0.UF/V 0UF/.V 0UF/.V UF/0V UF/0V EVENT# 0 0 N N NP_N 0 NP_N 0 OT0 OT 0 R# 0 REET# 0 #0 # 0 0 L 0 00 TET V V0 00 V 0 V 0 V V V V V V V V V V V V V V VP VREF VREFQ V V 0 V V V V V0 0 V V V V V V V V V V V0 V V V V V V 0 V V V V V0 V V V V V V V V V V 0 V0 V V V V V V V V V V V0 V VTT 0 VTT 0 WE# J0 R_IMM_0P J0 R_IMM_0P + E0 0UF/V ER=0mOhm/Ir=. + E0 0UF/V ER=0mOhm/Ir=. 0 0UF/.V 0 0UF/.V

M M M M M M M M M M M M0 M Q# M Q M Q M Q M Q M Q# M Q# M Q#0 M Q M Q# M Q0 M Q# M M M M M M M 0 M M M M M 0 M M M M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M M M M M Q M Q M Q# M Q# M Q M Q M Q M Q M Q0 M Q M Q M Q M WE# M_# M_LK_R M_KE M_LK_R# M_LK_R M_KE M # M R# M_LK_R# M_# M_OT M_OT M_T_,,,,, M_LK_,,,,, M M[:0] M Q#[:0] M Q[:0] M M 0 M M_RMRT#, M [:0] M Q[:0] PM_EXTT#0, +0.V +0.V +.V +.V M_VREF_IMM M_VREFQ_IMM +.V +V +V ate: heet of ustom Friday, ecember, 00 UTeK OMPUTER IN. N R OIMM_.0 NJv yunfeng_yan ate: heet of ustom Friday, ecember, 00 UTeK OMPUTER IN. N R OIMM_.0 NJv yunfeng_yan ate: heet of ustom Friday, ecember, 00 UTeK OMPUTER IN. N R OIMM_.0 NJv yunfeng_yan Mus lave ddress: H Layout Note: Place these caps near O IMM Layout Note: Place these caps near O IMM T.mm R. R. WP 00.UF/0V.UF/0V 0.UF/V 0.UF/V R0 0KOhm R0 0KOhm 0 0.UF/V 0 0.UF/V UF/0V UF/0V 0 0/P 0 /# 0 0 0 0 0 # K#0 0 K# 0 K0 0 K 0 KE0 KE M0 M M M M M M 0 M Q0 Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q 0 Q Q Q Q Q Q Q Q Q0 Q 0 Q Q Q Q Q 0 Q Q 0 Q Q Q0 Q Q Q Q Q Q Q 0 Q Q Q Q0 Q Q Q Q Q Q Q Q Q Q Q0 0 Q Q Q Q Q Q Q#0 0 Q# Q# Q# Q# Q# Q# Q# Q0 Q Q Q Q Q Q Q J0 R_IMM_0P J0 R_IMM_0P 0 0UF/.V 0 0UF/.V EVENT# 0 0 N N NP_N 0 NP_N 0 OT0 OT 0 R# 0 REET# 0 #0 # 0 0 L 0 00 TET V V0 00 V 0 V 0 V V V V V V V V V V V V V V VP VREF VREFQ V V 0 V V V V V0 0 V V V V V V V V V V V0 V V V V V V 0 V V V V V0 V V V V V V V V V V 0 V0 V V V V V V V V V V V0 V VTT 0 VTT 0 WE# J0 R_IMM_0P J0 R_IMM_0P + E0 0UF/V ER=0mOhm/Ir=. + E0 0UF/V ER=0mOhm/Ir=. UF/0V UF/0V 0 0.UF/V 0 0.UF/V RX0 RX0 R0 0KOhm R0 0KOhm UF/0V UF/0V.UF/0V.UF/0V.UF/0V.UF/0V 0UF/.V 0UF/.V 0 0UF/.V 0 0UF/.V 0UF/.V 0UF/.V 0.UF/V 0.UF/V 0 0.UF/V 0 0.UF/V UF/0V UF/0V 0.UF/V 0.UF/V 0UF/.V 0UF/.V 0 0.UF/V 0 0.UF/V 0UF/.V 0UF/.V

alpella larksfield R OIMM VREFQ Platform esign uide hange etails R Vref Intel ocument Number: 00 +.V M_VREF_R efault M R0 KOhm For R_VREF command & address. M_VREF_IMM0 R0 R0 R0 KOhm Near J0<000 mil M_VREF_IMM +.V R0 M_VREFQ_IMM0 M_VREFQ_IMM R0 0.UF/0V R KOhm R0 R0 Near J0<000 mil 0 0.UF/0V R KOhm IMM0_VREF_Q R0 IMM_VREF_Q R0 +.V R 0KOhm r00_h 0 R 0.UF/0V 0KOhm +V U0 V+ + V LMVIVR 0 0.UF/0V c00 M M: Processor enerated OIMM VREFQ New Requirement Option: Mount=R0,R0,R0,R0 Unmount=R0,R0,R0,M block UTeK OMPUTER IN. N _Q VOLTE yunfeng_yan ustom NJv ate: Friday, ecember, 00 heet of.0

<Enginner H_Lin Name> UTeK OMPUTER IN. N VI ustom NJv ate: Wednesday, November, 00 heet of.0

J00 RT battery +RTT R00 TT_HOLER_P +V_RT +V +V_RT JP00 00 MM_OPEN_MIL KOhm +RT_T T RTRT# +V_RT 00 UF/0V 00 PF/0V R.,item 00 PF/0V X00.Khz XRT L00 00 R00: For Xtal measurement T0 +V_RT R00 R00 T0 R00 0MOhm MOhm 0KOhm T0 X_RT X_RT RTRT# RTRT# M_INTRUER# U00 RTX RTX RTRT# RTRT# INTRUER# INTVRMEN RT LP FWH0/L0 FWH/L FWH/L FWH/L FWH/LFRME# LRQ0# LRQ#/PIO ERIRQ PH_RQ#0 F LP_RQ# T00 T00 LP_0 0, LP_ 0, LP_ 0, LP_ 0, LP_FRME# 0, INT_ERIRQ 0 R00 0KOhm % 00 UF/0V JRT00 L_JUMP _PKR R00 +V KOhm _PKR Z_LK Z_YN _PKR 0 P H_LK H_YN PKR T0RXN T0RXP T0TXN T0TXP K K K K T_RXN0 T_RXP0 T_TXN0 T_TXP0 RTRT# R00 0KOhm % 00 UF/0V JRT00 L_JUMP Z_LK_U RN0 Z_LK OHM Z_YN_U RN0 Z_YN OHM, Z_RT#_U RN0 Z_RT# OHM Z_OUT_U RN0 Z_OUT OHM +VM_PI PI_I R0 KOhm PI_O 0 PF/V INT_ERIRQ T0P TP R0 0KOhm Z_IN0_U R0 0KOhm +V R0 0KOhm Q00 HN00 0 PH_PI_OV R00 0KOhm R0 H_OK_EN# KOhm PI_LK R0 PI_#0 PI_I PI_O T00 T00 T00 T00 T00 T00 T00 Ohm T0 Z_RT# 0 0 Z_IN_M F0 E F Z_OUT H_OK_EN# H H_OK_RT# J0 PH_JT_TK M PH_JT_TM K PH_JT_TI K PH_JT_TO J PH_JT_RT# J _PI0# V _PI# Y Y V H_RT# H_IN0 H_IN H_IN H_IN H_O H_OK_EN#/PIO H_OK_RT#/PIO JT_TK JT_TM JT_TI JT_TO JT_RT# PI_LK PI_0# PI_# PI_MOI PI_MIO IH PI JT T TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TRXN TRXP TTXN TTXP TIOMPO TIOMPI TLE# T0P/PIO TP/PIO H H H H F F F F H H F F F F T Y V ET_TXN_N 0 ET_TXN_P 0 T0P TP T_OMP T_RXN T_RXP T_TXN T_TXP T,: E.0: T port,port may not be available in all PH KUs. R0 0.0UF/V 0.0UF/V R00 % 0KOhm +VTT_PH_VIO.Ohm +V ET_RXN ET_RXP ET_TXN ET_TXP T_LE# PI_I 0 PF/V IEXPEKM PI_#0 0 PF/V PI_LK 0 PF/V Z_LK 0 PF/V RF 預留 0 esign uide R. Update: page PIO: This signal should be only asserted low through an external pulldown in manufacturing or debug environments ONLY. Without connecting PIO, customers may not be able to override PI flash contents. R.,item L MoW IbexPeak JT requirements: E Enable:Mount R0,R0,R0,R0,R00,R0,R0. NI R0,R0. (TO) E isable:mount R00,R0,R0. NI: others. MoW0 IbexPeak JT requirements: tuff for preproduction trap information: +VU_OR R.,item L H_PKR: No reboot strap Low: isable. High:Enable H_OK_EN#:.Flash descriptor security: ampled low: override ampled high: in effect..pio low on the rising edge of PWROK, Will also disable Intel ME. R0 0 % R0 0 % R0 0 % R0 0 % R0 0 % +VU_OR R00 0KOhm % PH_JT_TO PH_JT_TM PH_JT_RT# PH_JT_TI R0 0 % R0 0KOhm % PH_JT_TK R0 Ohm PI_MOI: itpm strap. Mount R0: Enable Unmount R0: isable(default) E Mount :R0,R0,R0,R0,R0,R0,R00,R0,R0. UTeK OMPUTER IN. N T,IH,RT,LP yunfeng_yan NJv Friday, ecember, 00 ate: heet of 0.0

PIE PIE PIE PIE PIE PIE PIE PIE TV Tuner WLN Neward U.0 LN U00 PIE_RXN_TV 0 PERN PIE_RXP_TV J0 PIE_TXN_ 0.UF/V PIE_TXN_TV PERP F PIE_TXP_ 0.UF/V PIE_TXP_TV PETN H PETP PIE_RXN_WLN W0 PERN PIE_RXP_WLN 0 PIE_TXN_ 0.UF/V PIE_TXN_WLN PERP 0 0 PIE_TXP_ 0.UF/V PIE_TXP_WLN PETN 0 0 PETP PIE_RXN_NEWR U0 PERN PIE_RXP_NEWR T0 PIE_TXN_ 0.UF/V PIE_TXN_NEWR PERP 0 U PIE_TXP_ 0.UF/V PIE_TXP_NEWR PETN 0 V PETP PIE_RXN_U PERN PIE_RXP_U PIE_TXN_ 0.UF/V PIE_TXN_U PERP X0 PIE_TXP_ 0.UF/V X0 PIE_TXP_U PETN E PETP F PERN H PERP PETN J PETP PIE_RXN_LN PERN PIE_RXP_LN W PIE_TXN_ 0.UF/V PIE_TXN_LN PERP PIE_TXP_ 0.UF/V PIE_TXP_LN PETN PETP T PERN U PERP PIE,: U PETN V PETP E.0: port,port may not be available in all PH KUs. PERN J PERP PETN J PETP K LKOUT_PIE0N K LKOUT_PIE0P LK_REQ0# P PIELKRQ0#/PIO LK_PH_R_N LK_PIE_TV#_PH M LK_PIE_TV_PH L0 00 LK_PH_R_P LKOUT_PIEN M L0 00 LKOUT_PIEP LKREQ_TV# U L0 00 PIELKRQ#/PIO LK_PH_R_N LK_PIE_WLN#_PH M LK_PIE_WLN_PH L0 00 LK_PH_R_P LKOUT_PIEN M L0 00 LKOUT_PIEP LKREQ_WLN# N L0 00 PIELKRQ#/PIO0 PIE* Mus From LK UFFER ontroller PE Link MLERT#/PIO MLK MT ML0LERT#/PIO0 ML0LK ML0T MLLERT#/PIO MLLK/PIO MLT/PIO L_LK L_T L_RT# PE LKRQ#/PIO LKOUT_PE N LKOUT_PE P LKOUT_MI_N LKOUT_MI_P LKOUT_P_N/LKOUT_LK_N LKOUT_P_P/LKOUT_LK_P LKIN_MI_N LKIN_MI_P LKIN_LK_N LKIN_LK_P LKIN_OT_N LKIN_OT_P LKIN_T_N/K_N LKIN_T_P/K_P H J M E0 T T T H N N T T W P P F E H H EXT_I# 0 L ML0LERT# ML0_LK ML0_T MLLERT# ML_LK ML_LK ML_T ML_T L_LK L_T L_RT# LKREQ_PE# R LK_PIE_PE#_PH_L L LK_PIE_PE_PH_L L 00 00 LK_REF#_L L LK_REF_L L 00 00 LK_MI#_PH LK_MI_PH LK_REF# LK_REF LK_MI# LK_MI LK_PH_LK# LK_PH_LK LK_OT# LK_OT LK_T# LK_T PU_LKREQ_PE# 0 LK_PIE_PE#_PH 0 LK_PIE_PE_PH 0 EXT_I# 0KOhm R0 ML0LERT# 0KOhm R L_.KOhm R _.KOhm R ML0_LK.KOhm R ML0_T.KOhm R ML_LK.KOhm R ML_T.KOhm R MLLERT# 0KOhm R +VU_OR LK_REQ0# LK_REQ# LKREQ_TV# LKREQ_WLN# LKREQ_NEWR# LKREQ_LN# LK_REQ#_U LKREQ_TV# LKREQ_WLN# LKREQ_NEWR# LKREQ_LN# LK_REQ#_U LKREQ_PE# X_IN PH LKREQ etting: Not connected to device. R0 X_OUT XOUT R0: For Xtal measurement R R onnected to device. efault : lock free run. (P 0K). Reserver 0K PU for power saving purpose. R R R R R R.,item L R R R R R R MOhm R X0 Mhz 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm R0 +VU_OR +V 0 +VU_OR 0 PF/0V PF/0V LK_PIE_NEWR#_PH LK_PIE_NEWR_PH, LKREQ_NEWR# LK_PIE_U#_PH LK_PIE_U_PH L0 00 L0 00 L0 00 RX0 RX0 LK_PH_R_N H LK_PH_R_P H LK_PH_R_N M LK_PH_R_P M LKOUT_PIEN LKOUT_PIEP PIELKRQ#/PIO LKOUT_PIEN LKOUT_PIEP REFLKIN LKIN_PILOOPK XTL_IN XTL_OUT P J H H X_IN X_OUT T +VTT_PH_OR LK_IH LK_PI_F +VU LKREQ_U# RX0 LK_REQ#_U M PIELKRQ#/PIO XLK_ROMP F XLK_OMP R 0.Ohm % J0 J LKOUT_PIEN LKOUT_PIEP LKOUTFLEX0/PIO T LK_OUT0 T R.,item R KOhm LK_PIE_LN_N_PH LK_PIE_LN_P_PH LKREQ_LN# L0 L 00 00 L 00 Note: Place these resisters near to PIe lots T0 LK_REQ# H PIELKRQ#/PIO LK_PH_PE_N K LK_PH_PE_P LKOUT_PE N K LKOUT_PE P P PE LKRQ#/PIO IEXPEKM lock Flex LKOUTFLEX/PIO LKOUTFLEX/PIO LKOUTFLEX/PIO P T N0 LK_OUT LK_OUT LK_OUT R T R R 0PF/0V 0PF/0V Ohm Ohm EI_ELET# LK_U_U0 LK_U_R 0 PU_PWROK R Q0 N00 LKREQ_PE# UTeK OMPUTER IN. N PIE,LK,M,PE yunfeng_yan ustom NJv Friday, ecember, 00 ate: heet of.0

pree not support Reversal Feature MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP U00 MI0RXN J MIRXN W0 MIRXN J0 MIRXN MI0RXP MIRXP 0 MIRXP 0 MIRXP E MI0TXN F MITXN 0 MITXN E MITXN MI0TXP H MITXP 0 MITXP MITXP FI_RXN0 FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXN FI_RXP0 FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_RXP FI_INT H J E F W J FI_TXN0 FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXN FI_TXP0 FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_TXP FI_INT PM_LKRUN# R PM_RI# R PM_TLOW# R PIE_WKE# R ME_usPwrnck R0 UXPWROK_R R +V.KOhm +VU_OR 0KOhm.KOhm KOhm 0KOhm 0KOhm +VTT_PH_OR R0 +V % MI_OMP.Ohm H F MI_ZOMP MI_IROMP MI FI FI_FYN0 FI_FYN FI_LYN0 F H J FI_FYN0 FI_FYN FI_LYN0 FI_LYN FI_LYN 0,, XP_REET# LL_YTEM_PWR 0,, VRM_PWR 0 PM_PWROK_PH H_RM_PWR ME_usPwrnck PM_PWRTN#_R 0 PM_PWRTN# PM_RMRT#_PH R KOhm R R R R T R R T0 R T0 R T R 0KOhm Y_REET# MPWROK_R UXPWROK_R 0 PM_RMRT#_R T ME PREENT_PH T M K M P P Y_REET# Y_PWROK PWROK MEPWROK LN_RT# RMPWROK RMRT# U_PWR_K/PIO0 PWRTN# PREENT/PIO ystem Power Management WKE# LKRUN#/PIO U_TT#/PIO ULK/PIO LP_#/PIO LP_# LP_# LP_M# TP J Y P F E H P K N PM_U_TT# U_LK LP_# LP_#_R LP_#_R 00 LP_M#_R T0 T0 T0 00 T0 PM_LP_W# T0 L0 L0 PIE_WKE#,,, PM_LKRUN# 0 PM_U# 0 PM_U# 0 0'MoW0: Optional if ME FW is Ignition FW PM_PWROK_PH PM_RMRT#_PH 0KOhm R ME PREENT_PH R 0KOhm +VU_OR R 0KOhm Power failure solution (0>,>): PM_PWROK,PM_RMRT#: previous platform solution. ME_PWROK,ME PREENT: reserved for test. R R 0KOhm 0 R0 0KOhm 0 R 0KOhm 0 PT 0 0: Prevent E drive hign, U_PWR sink low in >. 0KOhm PM_PWROK 0, PM_RMRT#,,0 ME PREENT 0 T0 T0 PM_TLOW# PM_RI# F TLOW#/PIO RI# PMYNH LP_LN# J0 F ME_PM_LP_LN#_PH T0 PM_YN# 0 T U_PWR 0,, IEXPEKM T UTeK OMPUTER IN. N FI,MI,Y PWR yunfeng_yan ustom NJv Tuesday, ecember, 00 ate: heet of.0

U00 L_KEN_PH L_VEN_PH T T L_KLTEN L_V_EN VO_TVLKINN VO_TVLKINP J +V 0KOhm 0KOhm R L_TRL_LK R L_TRL_T L_KLTTL_PH EI_LK_PH EI_T_PH LV_LLKN_PH LV_LLKP_PH LV_L0N_PH LV_LN_PH LV_LN_PH LV_L0P_PH LV_LP_PH LV_LP_PH R0 R0 R0 L_TRL_LK L_TRL_T.KOHM Y Y V P P T T V V Y V 0 Y V L_KLTTL L LK L T L_TRL_LK L_TRL_T LV_I LV_V LV_VREFH LV_VREFL LV_LK# LV_LK LV_T#0 LV_T# LV_T# LV_T# LV_T0 LV_T LV_T LV_T LV igital isplay Interface VO_TLLN VO_TLLP VO_INTN VO_INTP VO_TRLLK VO_TRLT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P P_TRLLK P_TRLT TM_TRLLK TM_TRLT LV_ULKN_PH P LV_LK# LV_ULKP_PH P T0 LV_LK P_UXN E T0 P_UXP LV_U0N_PH Y LV_T#0 P_HP V0 TM_HP LV_UN_PH T LV_T# LV_UN_PH U 0.UF/V 0 LV_T# P_0N E0 TM_TXN_PH T 0.UF/V 0 LV_T# P_0P 0 TM_TXP_PH 0.UF/V 0 P_N F TM_TXN_PH LV_U0P_PH Y 0.UF/V 0 LV_T0 P_P H TM_TXP_PH 0.UF/V LV_UP_PH T 0 LV_T P_N TM_TXN0_PH 0.UF/V LV_UP_PH U0 0 LV_T P_P TM_TXP0_PH T 0.UF/V 0 LV_T P_N TM_LKN_PH 0.UF/V 0 P_P TM_LKP_PH J F H T T J U J 0 0 W Y RT PH RT PH RT_R_PH RT_LUE RT_REEN RT_RE P_TRLLK P_TRLT U0 U R % % % R R _LK_PH _T_PH RT_HYN_PH RT_VYN_PH R 0.% R R0., R0.: K+/0.% Intel checklist recommand:.0k P resistor to 0.% KOHM V V Y Y RT LK RT T RT_HYN RT_VYN _IREF RT_IRTN IEXPEKM RT P_UXN P_UXP P_HP P_0N P_0P P_N P_P P_N P_P P_N P_P T J0 0 J F H E UTeK OMPUTER IN. N P,LV,RT ustom NJv yunfeng_yan ate: Friday, ecember, 00 heet of.0

NT0#,NT#: oot IO trap. oot IO trap PI_NT# PI_NT0# oot IO Location 0 0 LP 0 PI 0 Reserved PI (PH) ampled on rising edge of PWROK. PI_NT0# PI_NT# PI_NT# +V NT#: swap override trap/ Toplock swap override jumper Low=Enabled swap override/ Toplock swap override High=efault R R0 0KOhm R KOhm KOhm LK_PI_F LK_PI LK_KPI_PH PU_ELET# PU_PWM_ELET#_PIO 0 0 PI_RT# /EMI /EMI /EMI 0PF/0V 0PF/0V R T0 PI_INT# PI_INT# PI_INT# PI_INT# PI_REQ0# PI_REQ# PI_REQ# PI_NT0# PI_NT# PI_NT# PI_INTE# PI_INTF# PI_INT# PI_INTH# PI_ERR# PI_PERR# PI_IRY# PI_PR PI_EVEL# PI_FRME# H0 N J 0 E H E0 0 M M F M0 M J K F0 K M J K L F J0 F M H J0 H H F M F K F H K K E E0 H F U00E 0 0 0 0 /E0# /E# /E# /E# PIRQ# PIRQ# PIRQ# PIRQ# REQ0# REQ#/PIO0 REQ#/PIO REQ#/PIO NT0# NT#/PIO NT#/PIO NT#/PIO PIRQE#/PIO PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO PIRT# ERR# PERR# IRY# PR EVEL# FRME# NV_E#0 NV_E# NV_E# NV_E# NV_Q0 NV_Q NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q0/NV_IO0 NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_Q/NV_IO NV_LE NV_LE NV_ROMP NV_R# NV_WR#0_RE# NV_WR#_RE# NV_WE#_K0 NV_WE#_K UP0N UP0P UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UPN UPP UP0N UP0P UPN UPP UPN UPP UPN UPP Y P V P P T T V E J J Y U V Y Y V F H J N0 P0 J0 L0 F0 0 0 0 M N H J E F H L M NV_LE NV_LE 0 0 NJv U port (IO/) U port(io/) U port ard Reader(.0) TV turner Newcard annot use annot use WiFi/WiMax amera T (.) NV_LE NV_LE U_PN0 U_PP0 U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN U_PP U_PN 0 U_PP 0 U_PN U_PP R0 R0 Recommand settings LM(.0) or UW(./.0) U port (th) or ocking FP (.) KOhm KOhm +V_NVRM_VQ 0, Follow esign Ip swap U port and Port +V PI_INT# RP0 0KOhm 0 PI_INT# RP0 0KOhm 0 PI_TOP# RP0 0KOhm 0 PI_INTE# RP0 0KOhm 0 PI_INT# RP0E 0KOhm 0 PI_IRY# RP0F 0KOhm 0 PI_ERR# RP0 0KOhm 0 PI_INT# RP0H 0KOhm 0 PI_PERR# RP0 0KOhm 0 PI_LOK# RP0 0KOhm 0 PI_EVEL# RP0 0KOhm 0 PI_INTH# RP0 0KOhm 0 RP0E 0KOhm 0 PI_REQ# RP0F 0KOhm 0 PI_FRME# RP0 0KOhm 0 PI_TRY# RP0H 0KOhm 0 PI_REQ0# RP0 0KOhm 0 PI_INT# RP0 0KOhm 0 PI_INTF# RP0 0KOhm 0 PI_REQ# RP0 0KOhm 0 RP0E 0KOhm 0 RP0F 0KOhm 0 RP0 0KOhm 0 RP0H 0KOhm 0 R.,item L +V PU_ELET#: 0=dPU, =ipu 0 LK_PI_F LK_KPI_PH LK_EU LK_PI PI_LOK# PI_TOP# PI_TRY# PLOK# TOP# TRY# URI# URI URI_PN R.Ohm T0 PI_PME# M PME# PLT_RT# O0#/PIO N 0KOHM RN0 PLTRT# O#/PIO0 J 0KOHM RN0 LK_PI0_R O#/PIO F 0KOHM RN0 T N Ohm R LK_PI_F_R LKOUT_PI0 O#/PIO L 0KOHM RN0 P 0KOHM RN0 LK_KPI_PH_R LKOUT_PI O#/PIO E Ohm R0 P LK_EU_R LKOUT_PI O#/PIO 0KOHM RN0 Ohm R0 P LK_PI_R LKOUT_PI O#/PIO0 F 0KOHM RN0 Ohm R0 P LKOUT_PI O#/PIO T 0KOHM RN0 Place within 00 mils of IH +VU_OR PLT_RT# UF_PLT_RT#,,0,,,0,,,,,0 R 0KOhm R0 KOhm 0 0PF/0V PI NVRM U U0 V Y NZ0PX_NL R IEXPEKM 0.UF/V UTeK OMPUTER IN. N PI,NVRM,U yunfeng_yan ustom NJv Tuesday, ecember, 00 ate: heet of.0

U00F +V +V R 0KOhm R 0KOhm 0 U_MI# EXT_MI# T_LE PU_HP_INTR#_R T0 T0 PIO0 PIO PU_HP_INTR#_R U_MI# T Y J F0 K T MUY#/PIO0 TH/PIO TH/PIO TH/PIO PIO LN_PHY_PWR_TRL/PIO PIO MI LKOUT_PIEN LKOUT_PIEP LKOUT_PIEN LKOUT_PIEP 0TE H H F F U 0TE 0 EXT_MI# LK_REQ# LK_REQ# PH_TEMP_LERT# R PU_HP_INTR#_R R PIO0 PIO PIO PIO U_MI# R 0KOhm PU_PRNT# PU_PWROK T_LK_REQ#, V_ORE_PWR U0_EL R R R0 +V R 0KOhm P_I0 P_I R 0KOhm R 0KOhm R 0KOhm R 0KOhm R 0KOhm R0 0KOhm R 00KOhm R 0KOhm R R0 0KOhm 0KOhm 0KOhm 0KOhm 0KOhm R KOhm PIO :Enable VVRM,Low=disable. efault internal pull up. +VU_OR +V PU_PWROK R0 % 0KOhm 0KOhm +VU_OR,0 PU_HOL_RT# PU_PWROK WLN_LE U0_EL WLN_ON# PU_PWR_EN#_PIO 0 PH_TEMP_LERT# T_ON T T T T T T T T T T0 T T T T T T T T T0 T T T T T T T T T T0 T T TP/PIO PU_PWROK F TH0/PIO Y LOK/PIO H0 MEM_LE/PIO VRM_EN PIO V PIO PIO M TP_PI#/PIO T_LK_REQ# V TLKREQ#/PIO TP/PIO PU_PRNT# TP/PIO P_I0 V LO/PIO P_I P TOUT0/PIO LK_REQ# H PIELKRQ#/PIO LK_REQ# F PIELKRQ#/PIO PIO TOUT/PIO TP/PIO F PIO T T T0 T T T TP_V_NTF TP_V_NTF V_NTF_ TP_V_NTF V_NTF_ TP_V_NTF V_NTF_ 0 TP_V_NTF V_NTF_ TP_V_NTF V_NTF_ TP_V_NTF V_NTF_ TP_V_NTF V_NTF_ TP_V_NTF V_NTF_ TP_V_NTF0 V_NTF_ TP_V_NTF V_NTF_0 E TP_V_NTF V_NTF_ E TP_V_NTF V_NTF_ F TP_V_NTF V_NTF_ F TP_V_NTF V_NTF_ H TP_V_NTF V_NTF_ H TP_V_NTF V_NTF_ H TP_V_NTF V_NTF_ H TP_V_NTF V_NTF_ J TP_V_NTF0 V_NTF_ J TP_V_NTF V_NTF_0 J TP_V_NTF V_NTF_ J TP_V_NTF V_NTF_ J TP_V_NTF V_NTF_ J0 TP_V_NTF V_NTF_ J TP_V_NTF V_NTF_ J TP_V_NTF V_NTF_ TP_V_NTF V_NTF_ TP_V_NTF V_NTF_ TP_V_NTF0 V_NTF_ E TP_V_NTF V_NTF_0 E V_NTF_ IEXPEKM PIO NTF RV PU LKOUT_LK0_N/LKOUT_PIEN LKOUT_LK0_P/LKOUT_PIEP PEI RIN# PROPWR THRMTRIP# TP TP TP TP TP TP TP TP TP TP0 TP TP TP TP TP TP TP TP TP N_ N_ N_ N_ N_ INIT_V# TP M M 0 T E0 0 W Y Y V V F M N J K K M N M0 N0 H T P 0 R PM_THRMTRIP# R0 TP_PH TP0_PH TP_PH TP_PH TP_PH TP_PH TP_PH TP_PH TP_PH TP_PH_N T TP_PH_N T TP_PH_N T TP_PH_N T TP_PH_N T INT_V# T T T T T T T T T T T T0 T T T T T T0 T T TP_PH_T T LK_PU_N_PH LK_PU_P_PH H_PEI RIN# 0 H_PUPWR, OHM R OHM H_THRMTRIP# +VTT_PU UTeK OMPUTER IN. N PU,PIO,MI ustom NJv yunfeng_yan ate: Friday, ecember, 00 heet of.0

PM_RMRT#,,0 +VTT_PH_VPLL_EXP +VTT_PH_VPLL_FI +VTT_PH_VPLL_EXP +VTT_PH_V +VTT_PH_VPLL_FI +VTT_PH_VIO +VTT_PH_VIO +VTT_PH_VIO +VTT_PH_OR +VTT_PH_OR +VFI_VRM +.V +VTT_PH_.V_.V +.V +VTT_PH_OR +V_V_IO +V +VTT_PU +V +VM_VPEP +VM +VTT_PU_V_MI +VTT_PH_OR +V_NVRM_VQ +.V +.V_VMI_VRM +V +V +VTT_PH +VTT_PH_V +VTT_PH_OR +VTT_PH_OR +VTT_PH_VIO +V +VFI_VRM +.V_VMI_VRM +.V_VT_LV +V_V_LV +.V +.V +V +V_NVRM_VQ +VU +VU ate: heet of Friday, ecember, 00 UTeK OMPUTER IN. N.0 NJv yunfeng_yan POWER, ate: heet of Friday, ecember, 00 UTeK OMPUTER IN. N.0 NJv yunfeng_yan POWER, ate: heet of Friday, ecember, 00 UTeK OMPUTER IN. N.0 NJv yunfeng_yan POWER,. 0 max m 0 idle 00m 0 max m 0 max m 0 max m 0 max m 0 max m 0 max m 0 max +VTT_PH_VPLL_EXP.. 0 max +VTT_PH_V_EXP.0 0 max U Item R.,item Resered for IT 0 0UF/.V 0 0UF/.V 0UF/.V 0UF/.V R0 R0 R R 0.UF/V 0.UF/V R0 R0 UF/.V UF/.V 0 UF/.V 0 UF/.V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0.UF/V 0.UF/V L0 KOhm/00Mhz L0 KOhm/00Mhz R R L0 KOhm/00Mhz L0 KOhm/00Mhz R0 R0 0 0UF/.V 0 0UF/.V VORE[] VORE[] VORE[] VORE[] VORE[] VORE[] F VORE[] F VORE[] F0 VORE[] F VORE[0] H VORE[] H VORE[] H0 VORE[] H VORE[] J0 VORE[] J VPNN[] K VPNN[] K0 VIO[] N VIO[] N VIO[] N VIO[0] N VIO[] N0 VIO[] N VIO[] T VIO[] T VIO[] U VIO[] U VIO[] V VIO[] V VIO[] W VIO[0] W VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] VIO[] E VIO[0] E VIO[] VIO[] VIO[] H VIO[] J VIO[] J V[] E0 V[] E VTX_LV[] P VTX_LV[] P VLV H VVRM[] T VVRM[] T VPLLEXP J VFIPLL J VPNN[] K VPNN[] K VPNN[] M VPNN[] M VIO[] K VTX_LV[] T VTX_LV[] T V_[] F V_LV H V_[] F VIO[] M V_[] V_[] V_[] V_[] N VME_[] M VME_[] M VME_[] P VME_[] P VPNN[] K VPNN[] M VPNN[] M VMI[] T VMI[] U VIO[] N0 VIO[] N POWER V ORE MI PI E* RT LV FI NN / PI HVMO U00 IEXPEKM POWER V ORE MI PI E* RT LV FI NN / PI HVMO U00 IEXPEKM 0.UF/V 0.UF/V R R R R R R R R 0 UF/.V 0 UF/.V R /IT0 R /IT0 R0 R0 0 UF/.V 0 UF/.V R 0KOhm R 0KOhm L0 KOhm/00Mhz L0 KOhm/00Mhz JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL Q0 N00 Q0 N00 0 0UF/.V 0 0UF/.V 0 0.0UF/V 0 0.0UF/V R R R R 0.UF/V 0.UF/V UF/.V UF/.V R R 0.UF/V 0.UF/V R0 R0 R R L0 KOhm/00Mhz L0 KOhm/00Mhz R R 0 T 0 T 0 UF/.V 0 UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V 0 0UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz R R 0 UF/.V 0 UF/.V Q N00 Q N00 0.0UF/V 0.0UF/V V[] V[] 0 V[] V[] V[] V[] V[] 0 V[] V[0] V[] V[] V[] V[] 0 V[] V[] V[] V[] V[] V[0] V[] V[] V[] V[] V[] V[] V[] V[] 0 V[] V[0] V[] V[] V[] V[] V[] V[] E V[] E V[] F V[] F V[] P V[] F V[] F V[] F V[] F V[0] F V[] V[] V[] H V[] H V[] H V[] H V[] H V[] H V[0] H V[] H V[] J V[] J V[] J0 V[] J V[] J V[] J V[] J V[] J V[0] J V[] T V[] J V[] K V[] K V[] K V[] K V[] K V[0] K0 V[] K V[] K V[] K V[] K V[] K V[] K V[] K V[] K V[] K V[0] K V[] L V[] L V[] M V[] M0 V[] M V[] M V[] M V[00] M V[0] M0 V[0] M V[0] M V[0] M V[0] M V[0] M V[0] M V[0] M V[0] U0 V[] M V[] V V[] M V[] M V[] 0 V[] N V[] N0 V[] N V[0] P V[] P V[] P V[] P V[] P V[] P V[] R V[] R V[] T V[] T V[] T V[] T V[] T V[] T V[] V V[] V V[] V0 V[] V V[0] V0 V[] V V[] V V[] V V[] V V[] V V[] V V[] V V[] W V[] W V[0] W V[] F V[] W V[] W V[] W0 V[] W V[] Y V[] Y V[] Y V[0] Y V[] U V[] N V[] 0 V[0] V[] V V[] U V[] M V[] M V[] N V[] H V[] V[0] H V[0] V[] V[] U00H IEXPEKM U00H IEXPEKM R0 R0 0.0UF/V 0.0UF/V

TP_PH_VW +V.0_INT_VU +VT PRT +.0VM_OR_R +.0VM_OR_R +.0VM_OR_R +.0VM_OR_R +VTT_PH_V PL +VTT_PH_V PL +VTT_PH_V PL +V_VPU +.0VM_OR +VTT_PH_V_LK +.0VM_VUX +VTT_PU_VPPU +V_RT +VTT_PH_VIO +V_V_ +.0VM_OR +VTT_PU +VTT_PH_.V_.V +VU_OR +VTT_PH_V PL +VTT_PH_V PL +VTT_PH_VPLL +V_PH_VREF +VU_VPU +VTT_PH_VIO +VTT_PH_VIO +VTT_PH_OR +V +VU_OR +.0VM_OR +VU_OR +V_V_ +VU_OR +VTT_PH_VIO +V_V_ +V +VPLLVRM +VU_PH_VREFU +VTT_PH_OR +VTT_PH_V PL +VTT_PH_V PL +VTT_PH_OR +VTT_PH_.V_.V +VPLLVRM +VTT_PH +.0VM_OR +V +V_V_ +VU_H +VU_OR +VU +VU_OR +VU +VU_OR +VM ate: heet of Wednesday, November, 00 UTeK OMPUTER IN. N.0 NJv yunfeng_yan POWER, ate: heet of Wednesday, November, 00 UTeK OMPUTER IN. N.0 NJv yunfeng_yan POWER, ate: heet of Wednesday, November, 00 UTeK OMPUTER IN. N.0 NJv yunfeng_yan POWER, m 0 max m 0 max 0 max m 0 max m 0 max +.VM_VEPW >m 0 max m 0 max +VTT_PH_V.+m 0 max m 0 max +VTT_PH_VUORE m 0 max +VTT_PH_V_T +V_VPPI +V_VPORE 0mil trace R.,item L R.,item L R.,item L R.,item L R.,item L + E0 0UF/V ER=0mOhm/Ir=. + E0 0UF/V ER=0mOhm/Ir=. 0.UF/V 0.UF/V.UF/.V.UF/.V R R UF/.V UF/.V R R 0.UF/V 0.UF/V 0UF/.V 0UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz UF/.V UF/.V R R R R 0 T 0 T UF/.V UF/.V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL 0.UF/V 0.UF/V R R 0.UF/V 0.UF/V 0.UF/V 0.UF/V R R R 0 R 0 0.UF/V 0.UF/V 0.UF/V 0.UF/V R R R0 R0 0 UF/.V 0 UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz 0.UF/V 0.UF/V 0.UF/V 0.UF/V R R UF/.V UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0 UF/.V 0 UF/.V UF/.V UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz 0.UF/V 0.UF/V UF/.V UF/.V 0 UF/.V 0 UF/.V L0 KOhm/00Mhz L0 KOhm/00Mhz 0 0.UF/V 0 0.UF/V R R 0 0.UF/V 0 0.UF/V UF/.V UF/.V 0.UF/V 0.UF/V 0.UF/V 0.UF/V JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL UF/.V UF/.V 0UF/.V 0UF/.V UF/.V UF/.V 0 T 0 T JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL UF/.V UF/.V R R 0UF/.V 0UF/.V R R UF/.V UF/.V 0.UF/V 0.UF/V R 0 R 0 JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL UF/.V UF/.V V[] Y V[0] V[] V[] V[] V[] V[] V[] V[] V[] V[] V[0] V[] V[] V[] 0 V[] V[] 0 V[] V[] V[] V[] V[0] V[] 0 V[] V[] V[] V[] V[] V[] V[] 0 V[] V[0] V[] H V[] V[] V[] V[] E V[] E V[] E0 V[] E V[] E0 V[00] E V[0] E V[0] E V[0] E V[0] E V[0] E0 V[0] E V[0] E V[0] F V[0] F V[0] F V[] V[] V[] V[] 0 V[] H V[] H V[] H V[] H V[] H V[0] H V[] H V[] H V[] H V[] H V[] V[] 0 V[] V[] E V[] E V[0] E0 V[] E V[] E0 V[] E V[] E V[] E V[] E V[] E V[] K V[] K V[] L V[] L V[] L V[] L V[0] L V[] L V[] L0 V[] L V[] M V[] M V[] M0 V[] N V[] M V[] M V[0] M V[] M V[] M V[] M V[] M V[] N V[] P V[] P V[] P0 V[0] P V[] P V[] P V[] P V[] P V[] R V[] R V[] T V[] T V[] T V[00] T V[0] T V[0] T V[0] U0 V[0] U V[0] U V[0] U V[0] P V[0] V V[0] P V[0] V V[] V0 V[] V V[] V0 V[] V V[] V V[] V V[] E V[] E V[0] F V[] F V[] 0 V[] V[] V[] V[] V[] V[] V[] 0 V[0] V[] V[] V V[] V V[] V V[0] V V[] V V[] V V[] V V[] V V[] V V[] V V[] W V[] W V[] Y V[0] Y V[] Y V[] Y V[] Y V[] Y V[] Y0 V[] Y V[] Y V[] Y V[] Y V[0] Y V[] Y V[] Y V[] Y V[] P V[] P V[] V[] F V[] H V[] H0 V[] H0 V[] H V[] H V[] H V[] T V[] V[] T V[] V[0] Y V[] T V[] M V[] T V[] M V[] K V[] K V[] V V[] K V[] K V[] H V[0] H V[] J U00I IEXPEKM U00I IEXPEKM JP0 MM_OPEN_MIL JP0 MM_OPEN_MIL + E0 0UF/V ER=0mOhm/Ir=. + E0 0UF/V ER=0mOhm/Ir=. PUYP Y0 VME[] VME[] VME[] VME[] F VME[] F VUH L0 VU_[] U VIO[] V VIO[] VIO[] F0 VIO[] F VME[] V VME[] V VME[] V VME[0] Y VME[] Y VME[] Y VREF K V_[] J V_[] L V_[0] M V_[] N V_[] P V_[] U VRT VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] E VU_[] E VU_[0] F VU_[] F VU_[] VU_[] VU_[] H VU_[] H VU_[] J VU_[] J VU_[] L VU_[] L VU_[0] M VU_[] M VU_[] N VU_[] N VU_[] P VU_[] P VU_[] U VU_[] U VU_[] U VU_[] V VIO[] 0 VIO[0] VIO[0] H VPLL[] VPLL[] VIO[] J VREF_U F VIO[] H0 VIO[] VIO[] 0 VIO[] VIO[] F V_[] VIO[] H VVRM[] T0 PU Y VIO[] F VIO[] H VLN[] F VLN[] F VPLL[] VPLL[] VVRM[] U VLK[] P VLK[] P PRT V VIO[] F VME[] F VIO[] H VIO[] H PT V VTPLL[] K VTPLL[] K VME[] VME[] Y VME[] Y VME[] V_[] V V_[] V V_[] Y VU_[] P VU_[0] U VU_[] U0 VU_[] U VIO[] V VIO[] V VIO[] Y VIO[] Y V_PU_IO[] T V_PU_IO[] U POWER T U lock and Miscellaneous H PU PI/PIO/LP RT PI/PIO/LP U00J IEXPEKM POWER T U lock and Miscellaneous H PU PI/PIO/LP RT PI/PIO/LP U00J IEXPEKM

+V_E +VU +VM R R R 0 0 E_E#_PH E_O_PH 0 T R PJP0 PJP0 +VM_PI PI FLH TOOL ON Put near U0 L_JUMP L_JUMP Ohm R R PH PI ROM +VM_PI PI_#_ON PI_O_ON 00000K J0 R U0 HEER_XP_K +VM_PI.KOhm PI_LK_ON PI_I_ON R.KOhm 0 0.UF/V R R L_JUMP PJP0 L_JUMP PJP0 E_K_PH 0 E_I_PH 0 L_ PH _ 0 E M_LK MU Link device: [MJ] P, LKEN,EU,WLN, PU XP,PH XP,VI ONTROLLER [0J] FM00,ME LE, Q0 UMKN R +V Q0 UMKN R +V +VU.KOhm R0 M_LK_,,,,, M_T_,,,,, ML_LK 0 0 PI_#0 PI_O Ohm R R PIO0 +VM_PI_WP0# E# V O HOL# WP# K V I +VM_PI_00 PILK0 PII0 Ohm R0 Ohm R PI_LK 0 PI_I 0 PH R R0 R R0 TVF0 (Mb) +V R 0 0.UF/V +V_U0 R /IT0 R /IT0 R R R R 0 M_T Q0 UMKN Q0 UMKN +V.KOhm R0 Q0 UMKN R /IT0 R /IT0 +V.KOhm R0.KOhm R0 ML_T M_LK_ 0, V Thermal,,0 PM_RMRT# 0 E_K_PH 0 E_E#_PH R PI_LK_ PI_LK_ON PI_#0_ PI_#_ON U0 IN V EN# 0 PI_I_ PI_I_ON E_O_PH PI_O_ PI_O_ON E_I_PH 0 E_O_PH 0 Q0 UMKN M_T_ 0, TV0QR UTeK OMPUTER IN. N PI ROM,OTH yunfeng_yan ustom NJv Friday, ecember, 00 ate: heet of.0

+V_. +V_. +V_IO RN0 0KOHM LK_PWR T0 T0 LK_PH_LK LK_PH_LK# +V_. LK FL 0 00 R0 0KOhm R0 0KOhm +V_. LK_PWR# 0 PF/0V R.,item 0 PF/0V LK_IH,,,,, M_T_,,,,, M_LK_ Q0 N00 XLK R0.Mhz X0 R0 Ohm +V_. X_LK X_LK FL 0 VPU_. PUT0_LPR VOTMHz_. OTMHz OTT_LPR OT_LPR V_MHz MHz_non MHz_ MHz PU_TOP# VR_IO R_LPR RT_LPR R T_LPR TT_LPR 0 T +V_IO TP_PU# LK_MI# LK_MI LK_T# LK_T +V_. PU0_LPR PU LKPWR/P#_. REF X X VREF_. REF_L/FL_.** T_. LK_. PUT_LPR 0 PU_LPR VPU_IO VR_. U0 ILRKLFT RN0 0KOHM LK_ LK_FIX RN0 OHM 0PF/0V 0 RN0 OHM 0PF/0V 0 LK_OT# TIM_ TIM_NO LK_OT R.,item Layout note: R +V L0 +V_VPIEX +V_. PF/0V PF/0V RX0 FL /00Mhz 0 0 0 0 0 0 0UF/0V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V R R,R:as close as possible to the net FL of RX0. +VTT_PU L0 /00Mhz +V_IO 0UF/0V 0.UF/V 0.UF/V Layout note: V_.: pin >0.uF to each pin V_IO : pin >0.uF to each pin UTeK OMPUTER IN. N LK_ILR yunfeng_yan ustom NJv Friday, ecember, 00 ate: heet of.0

pin +V_E For IT Power R0 +V R.,item L +V_E +VPLL pin R0 +V +V +V_E IT0 / IT is N on pin JP00 U00 0, LP_0 RNX00 0 P0 MM_OPEN_MIL OHM L0 PWR_LE# 0, LP_ RNX00 OHM L P H_LE# 0, LP_ RNX00 OHM L PWM/P H_FULL_LE# 0, LP_ RNX00 OHM L PWM/P PWR_LE_PWM_ LK_KPI_PH LPLK PWM/P 0 L_L_PWM 0, LP_FRME# LFRME# PWM/P FN_PWM 0,,,0,,,,,0 UF_PLT_RT# LPRT#/WUI/P PWM/K/P K_LE_PWM 0 INT_ERIRQ ERIRQ PWM/P PWR_LE_PWM EXT_MI# EMI#/P EXT_I# EI#/P RX/IN0/P0 0 TEL_0 0TE 0/P TX/OUT0/P 0 TEL_ RIN# E_RT# KRT#/P P R0 ME PREENT For PU / P R.,item E_RT# WRT# RIN#/PWRFIL#/KKOUT /LPRT#/P PM_RMRT#,, ME_usPwrnck_E 0 +V_E E_K K_E E#/P0 P0 R0 Ohm 0 T0 FK 0 R0 T_IN_O# _IN_O#, 00KOhm E_O R0#/P TMRI0/WUI/P 0 0 R0 T_IN_O# E_I I_E FMIO 00KOhm R0 Ohm 0 T_IN_O# 0 E_E# E#_E FMOI TMRI/WUI/P R00 Ohm 0 RFON_W# M0_LK T0 FE# PWUREQ#/O/P RN00.KOHM 00 RN00 M0_T E0#/P.KOHM RI#/WUI0/P0 PWRLIMIT#,0 +VU KI0 KI0/T# RI#/WUI/P PM_U# KI KI/F# INT/T0#/P L_KOFF# M_LK KI 0 KI/INIT# TH0/P RN00 FN0_TH 0.KOHM M_T KI RN00 KI/LIN# TH//P HMI_HP_E.KOHM KI KI VU_ON KI T0 KI L0HLT/O/WUI/PE0 R0 KI KI E/WUI/PE VOLUME_UP# KI KI E#/WUI/PE VOLUME_OWN# ELK_E PM_U# RN00 00KOhm ELK/WUI/PE T0 T0 PM_U# RN00 KO0 PWR_W# 00KOhm KO0/P0 PWRW/PE T_IN_O# RN00 KO 00KOhm KO/P WUI/PE PU_VRON KO KO/P LPP#/WUI/PE RN00 LI_W#, 00KOhm KO KO/P L0LLT/WUI/PE 0 PLY/PUE# KO 0 KO/P KO KO/P KO KO/P UY/P/I 0 PM_U# KO KO/P KO KO/K# VU_ON KO KO/UY R.,item L R0 00KOhm KO0 KO0/PE KO KO/ERR# R.,item L KO KO/LT LKRUN#/WUI/PH0/I0 PM_LKRUN# KO KO WUI/PH/I KO KO WUI/PH/I H_EN KO KO WUI/PH/I U_E#,,, PM_PWRTN# KO/MOI/P PH/I U_E#,,,,,,, OP_# KO/MIO/P PH/I NUM_LE# P_LE# E_XIN PH/I E_XOUT KK NV_OVERT# R0 KKE PI0 V_LERT#, PI U_PWR,, T0 /PF0 PI LL_YTEM_PWR, R0, VU_ON /PF PI VRM_PWR,, MRTHON# PLK/TR0#/PF /WUI/PI 0 R00 PH_TEMP_LERT# R0 MUTE# PT/RT0#/PF /WUI/PI FX_VR TP_LK PLK/WUI0/PF /WUI0/PI Note: TP_T 0 PT/WUI/PF /WUI/PI _#_E 0 EXT_MI#, EXT_I#, PU power plane depend on IH PIO. 0 M0_LK 0 MLK0/P TH/PJ0 PU_VRON, 0 M0_T MT0/P PJ PM_PWROK, M_LK MLK/P /PJ VET_E M_T MT/P /PJ IET_E THRO_PU T0 WUI/PF /0#/PJ 0 For X'tal Note: 0 PH_PI_OV WUI/PF /RI0#/PJ LV_PU_W load=.pf PH_PI_OVL IT0E T0 place close to E H: override PH PI R0 0MOhm E_XIN E_XOUT 0 VTY VTY VTY VTY VTY VTY(PLL) KMX LP FLH ROM P/ Mus N V V PIO V VORE V V V V V V E_ R0 for ITX & ITX 00 00 & 00 for ITX 0.UF/V +VU +V_E +V_E +V +V For E Hardware trap E_ imt E strapping need to check 0 PF/0V X00.Khz R0 0 PF/0V I/O ase ddress Note: It can be programmable by E fireware hare Memory Note: It can be programmable by E fireware. PP Enable 00 0UF/0V RN00 RN00 RN00 RN00 RN00 RN00 RN00 RN00 RN00 RN00 RN00 RN00 Note: efault Int. PullLow R0: For Xtal measurement 00 0.UF/V R00 0KOHM 0KOHM 0KOHM 0KOHM.KOHM.KOHM.KOHM.KOHM 0KOHM 0KOHM 0KOHM 0KOHM 00 0.UF/V LI_W# PWRLIMIT# _IN_O# PWR_W# TP_LK TP_T U_E# U_E# +V_E +V 0TE RIN# PM_PWRTN# PM_RMRT# 00 0UF/0V 00 0.UF/V +V +V_E For imt pin name _PREENT PM TTE# _TTE_ON PM_LP_M# LP_M_ON E_WLN_PWR MP_PWR _PREENT LN_WOL_EN +VM_P +.VM_+VMLK_P UPWR_K R0 R00 +VPLL +V E_ For Instant Key Note: lose to E 00 For +VPLL 0.UF/VPut beside pin 00// modify function key RN00 PLY/PUE# 0KOhm RN00 VOLUME_UP# 0KOhm RN00 VOLUME_OWN# 0KOhm RN00 MUTE# 0KOhm R0 R0 00 0.UF/V 0KOhm 0KOhm MRTHON# RFON_W# +V_E R00 0KOhm ME_usPwrnck_E ME_usPwrnck ME_usPwrnck Q00 N00 R0 Mount R00,Q00,NI R0 for IT00 E_E#_PH E_O_PH +V_E +V_E_PI /IT00 R00 R00 /IT0 E_E# R00 /IT0 Ohm E_O R0 Ohm O_ROM /IT00 ROM_WP# R0.KOhm /IT00 U00 /IT00 E# V O HOL# WP# K V I R0.KOhm /IT00 +V_E_PI 0 0.UF/V /IT00 ROM_H# E_K /IT0 R00 E_I /IT0 R00 E_K_PH E_I_PH TVF UTeK OMPUTER IN. N K_IT0 yunfeng_yan NJv Friday, ecember, 00 ate: heet of 0.00

For Keyboard K LE Main oard J0 KO KO0 KI KI KO 0 0 KI IE KI KO KI KI KO KI KI0 KO KO 0 0 KO KO KO KO KO KO0 IE KO KO KO FP_ON_P 000 modify KO 0 KO0 0 KI 0 KI 0 KO 0 KI 0 KI 0 KO 0 KI 0 KI 0 KO 0 KI 0 KI0 0 KO 0 KO 0 KO 0 KO 0 KO 0 KO 0 KO 0 KO0 0 KO 0 KO 0 KO 0 KO PF/0V N KO0 PF/0V N KI PF/0V /EMI N KI /EMI N PF/0V /EMI KO /EMI PF/0V N KI PF/0V N KI PF/0V /EMI N KO N PF/0V /EMI /EMI KI /EMI PF/0V N0 KI N0 PF/0V KO PF/0V /EMI N0 KI /EMI N0 PF/0V /EMI KI0 /EMI PF/0V N0 KO PF/0V N0 KO PF/0V /EMI N0 KO /EMI N0 PF/0V /EMI KO /EMI PF/0V N0 KO PF/0V N0 KO PF/0V /EMI N0 KO /EMI N0 PF/0V /EMI KO0 /EMI PF/0V N0 KO PF/0V N0 KO /EMI PF/0V N0 KO N0 PF/0V /EMI /EMI /EMI Reserve for EMI J0 IE IE FP_P 000 0 K_LE_PWM +V_KLE +V L0 00 +V R LE_TR Q0 N00 Max m Q0 N00 K_LE_PWM +V L 00 0.UF/V +V_TP J0 T0 J0_ IE 0 0 0 TP_T 0 TP_LK LEFT_TN# T0 J0_ T0 J0_ RIHT_TN# IE ZIF_ON_P TP_T TP_LK 0 PN0Y /E modify 00 LEFT_TN# R0 Ohm LEFT_TN_L# W0 RIHT_TN# R Ohm RIHT_TN_L# W0 0 0.UF/V TP_WITH_P 0000P 0 0.UF/V TP_WITH_P 0000P UTeK OMPUTER IN. N ustom NJv IT_K, TP yunfeng_yan ate: Tuesday, ecember, 00 heet of.0

Main oard +V 0, V_LERT# R 0KOhm R 0 PU_THERM# R0 PU_V_THERM#,,,0,,0,,,,,0,0 UF_PLT_RT# PM_PWROK R R 0 0.UF/V N00ET Q0 +V_E R 00KOhm IT has builtin level detection for poweron reset circuit 0 FORE_OFF# R E_RT# 0 0.UF/.V Output ignal UTeK OMPUTER IN. N RT_Reset ircuit yunfeng_yan ustom NJv ate: Tuesday, ecember, 00 heet of.0

R:Remove R0, R:Remove L0,,R0 R with overclock: Remove R R:Remove L0 R:=0.uF, Remove.UH L0 F F close to Pin R:Remove R LK_PIE_LN_P_PH LK_PIE_LN_N_PH /RF 0.UF/V 0.UF/V +V_EN 0.UF/V L 00 00// change 0UF/.V PIN_ PIN_ R:=0.uF 0.UF/V R:=uF R.KOHM LE_TN_L VL VL V_VO VL PIE_TXN_ PIE_TXP_ LK_PIE_LN_P_PH LK_PIE_LN_N_PH PIE_RXP_ 0.UF/V PIE_RXP_LN PIE_RXN_ PIE_RXN_LN 0.UF/V RF 預留 /RF R:L0=0ohm VL L0 00 V_VO 0.UF/V With overclock:remove R Not overclock:remove R0,,,0,,0,,,,,0 UF_PLT_RT#,,, PIE_WKE# R:Remove R0 R/MHz:Remove R0 R/MHz:Remove UF/0V +V_LN T 0.UF/V PIN_ PIN_ PIN_ EL_M VL X_LN X_LN V_VO RI VL R: Remove R VL R: Remove R VL LK_REQ LKREQ_LN# V_+.V ground pad 要打散熱孔 For R: Remove R0,R0,,,,Q0 For R: Remove R0 Q0 close to Pin PIN_ L0 V_+.V 00 V_+.V VL V_+.V VL +V_LN V_+.V L_TP L_TN L_RP L_RN L_TRP L_TRM L_TRP L_TRM RN0.OHM RN0.OHM RN0.OHM RN0.OHM RN0.OHM RN0.OHM RN0.OHM RN0.OHM TR_NET TR_NET TR_NET TR_NET 0 0 0 0 close to pin 0 close to pin X_LN VL VL For R : Remove R0 X_LN PF/0V 0 UF/0V 0 0.UF/V 0.UF/V R.KOHM % 0 U0 LX VV_ PERTn WKEn VV_ V EL_MHz V_RE XTLO XTLI V_RE RI RLE LE_0_00n LE_Tn V_RE_ V_RE_ RX_N RX_P VL REFLKP REFLKN 0 VL_ TX_P TX_N TRXP0 TRXN0 VHO VL_ TRXP TRXN VH_ TRXP TRXN VL_ TRXP TRXN 0 VL_ N TETMOE MT VL_ MLK TWI_T TWI_LK VL_ LKREQn LE_LINK000n VH_ 0 0.UF/V +VU L0 /00Mhz 0 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0 0UF/.V c00 0 0UF/.V c00 0 0.UF/V 0 UF/0V 0 0.UF/V X0 Mhz 0 PF/0V R:Remove R/MHz: Remove R/MHz: Remove 0 X0 0 UF/0V 0 0.UF/V 0 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V 0.UF/V /0 限高問題, 換料為 00000 0 close to pin/ UTeK OMPUTER IN. N LN R yunfeng_yan ustom NJv Friday, ecember, 00 ate: heet of.0

+V_EN U0 0.UF/V 0.UF/V 0.UF/V UF/0V L_TP L_TN L_RP L_RN L_TRP L_TRM L_TRP L_TRM T+ TT T T+ TT T T+ TT T T+ 0 TT T LFE_R MX+ MT MX MX+ MT MX MX+ MT MX MX+ MT MX 0 L_TRLP0 L_MT0 L_TRLM0 L_TRLP L_MT L_TRLM L_TRLP L_MT L_TRLM L_TRLP L_MT L_TRLM L_TRLM L_TRLP L_TRLM0 L_TRLP0 L_TRLP L_TRLM L_TRLP L_TRLM L0 00 L0 00 L0 00 L0 00 L0 00 L0 00 L0 00 L0 00 LTRLM LTRLP LTRLM0 LTRLP0 LTRLP LTRLM LTRLP LTRLM LTRLM LTRLP LTRLM LTRLM LTRLP LTRLP LTRLM0 LTRLP0 J0 P_ 0 NP_N NP_N P_ MOULR_JK_P LN_ +V_LN +V_LN L_TP L_RP L_TRP L_TRP 0 IPZ L_TN VI/O VI/O N/ VU VI/O VI/O L_RN 0 IPZ L_TRM VI/O VI/O N/ VU VI/O VI/O L_TRM 0.UF/V 0 0.UF/V 0 0.UF/V 0 LN_ Place near chassis L_MT0 L_MT L_MT L_MT RN0 Ohm /EMI RN0 Ohm /EMI RN0 Ohm /EMI RN0 Ohm /EMI LN T /EMI 0 000PF/KV M0 P P0 P M M M P LN close to transformer LN_ 000000 э ノ 00000 (/0) 0, change 0 and 0 stuff by default. UTeK OMPUTER IN. N RJ yunfeng_yan ustom NJv ate: Monday, ecember, 00 heet of.0

+V +V LV witch LV_L0P LV_L0N LV_LP LV_LN LV_LP LV_LN LV_LLKP LV_LLKN LV_L0P_V LV_L0N_V LV_LP_V LV_LN_V LV_LP_V LV_LN_V LV_LLKP_V LV_LLKN_V L_KLTEN_V L_V_EN L_KEN_PH L_VEN_PH +V PU_W_EN Q0 Q0 UMKN UMKN /Hybrid /Hybrid /Hybrid PU_W_EN PU_W_EN# Q0 Q0 UMKN UMKN /Hybrid /Hybrid /Hybrid PU_W_EN# L_KEN_PH L_VEN_PH U0 0 UMKN Q0 UMKN Q0 0 0 V V M R V V 0 0+ 0 V 0+ 0 V EL 0+ 0 V 0+ 0 + + + + V + + + + 0+ 0 V 0+ 0 V EL 0+ 0 V 0+ 0 /Hybrid 0 +V /Hybrid /Hybrid 00KOhm UMKN Q0 UMKN Q0 R 00KOhm PU_ELET#_W LV_L0P_PH LV_L0N_PH LV_LP_PH LV_LN_PH LV_LP_PH LV_LN_PH LV_LLKP_PH LV_LLKN_PH L_KEN L_VEN LV_U0P LV_U0N LV_UP LV_UN LV_UP LV_UN LV_ULKP LV_ULKN LV_U0P_V LV_U0N_V LV_UP_V LV_UN_V LV_UP_V LV_UN_V LV_ULKP_V LV_ULKN_V +V LV_L0P_PH LV_L0N_PH LV_LP_PH LV_LN_PH LV_LP_PH LV_LN_PH LV_LLKP_PH LV_LLKN_PH LV_U0P_PH LV_U0N_PH LV_UP_PH LV_UN_PH LV_UP_PH LV_UN_PH U0 0 LV_ULKP_PH LV_ULKN_PH M L_KEN_PH L_VEN_PH 0 0 V V V V 0 EL = 0 +/ TO 0+/ EL = +/ TO +/ + + + + V + + + + R /Hybrid 0 +V R0 /Optimus R0 /Optimus R0 /Optimus R0 /Optimus R0 /Optimus R0 /Optimus R0 /Optimus R0 /Optimus R /Optimus R /Optimus R /Optimus R /Optimus R /Optimus R0 /Optimus R0 R R /Optimus /Optimus /Optimus /Optimus PU_ELET#_W L_KEN L_VEN LV_U0P_PH LV_U0N_PH LV_UP_PH LV_UN_PH LV_UP_PH LV_UN_PH LV_ULKP_PH LV_ULKN_PH Optimus LV_L0P LV_L0N LV_LP LV_LN LV_LP LV_LN LV_LLKP LV_LLKN LV_U0P LV_U0N LV_UP LV_UN LV_UP LV_UN LV_ULKP LV_ULKN RT_R_PH RT_R_V RT_RE RT PH RT V RT_REEN RT_VYN_V RT_HYN_V RT_VYN_PH RT_HYN_PH +V U0 /Hybrid PU_ELET#_W IN V EN# 0 TV0QR PU_W_EN Q UMKN UMKN Q PU_W_EN PU_W_EN# Q UMKN Q UMKN /Hybrid /Hybrid /Hybrid /Hybrid Q UMKN /Hybrid /Hybrid /Hybrid /Hybrid UMKN Q PU_W_EN# Optimus UMKN Q UMKN Q 0 0.UF/V RT PH RT V RT_LUE RT_VYN RT_HYN RT_R_PH R /Optimus RT_RE RT PH R0 /Optimus RT_REEN RT PH R /Optimus RT_LUE RT_HYN_PH R /Optimus RT_HYN RT_VYN_PH R /Optimus RT_VYN UM to PU wtich PU_PWR_EN#_PIO PU_PWROK This ignals from M to PH. PU_HOL_RT# PU_ELET# EI_ELET# PU_PWM_ELET#_PIO PU to UM wtich PU_ELET#_W PU_M_EN ontrol ignal from PH R 0KOhm R 0KOhm /Hybrid +V +V Q N00 /Hybrid 0 0.0UF/V R 00KOhm /Hybrid PU_W_EN# Q UMKN /Hybrid PU_W_EN Q0 UMKN +V Q UMKN /Hybrid 0.0UF/V +V R 00KOhm /Hybrid +V +V /Hybrid R R R R 00KOhm Q N00 R 00KOhm R 0KOhm /Hybrid PU_ELET#: Low : dpu High : ipu R PU_ELET# LV_PU_W 0 Q0 R UMKN 0KOhm PU_HOL_RT#,0 PU_EI_ELET Q0 Q0 UMKN UMKN /Hybrid EI LK_V /Hybrid /Hybrid EI_LK_V EI T_V EI_T_V /Hybrid EI_LK_PH /Hybrid RN0.KOHM EI_T_PH /Hybrid RN0.KOHM +V _T_V _LK_V PU_EI_ELET Q UMKN /Hybrid /Hybrid /Hybrid /Hybrid UMKN Q PU_EI_ELET PU_EI_ELET# Q UMKN UMKN Q RT T RT LK PU_EI_ELET TM_TRLLK HMI LK HMI_LK TM_TRLT HMI T HMI_T U0 I0 I Y I0 I Y /Hybrid PIQE V E# I0 I Y I0 I 0 Y +V TM_HP HMI_HP_V HMI_HP EI_ELET# Low : dpu High : ipu EI_LK_PH EI_T_PH UMKN Q0 PU_EI_ELET PU_EI_ELET# Q0 UMKN UMKN Q0 PU_EI_ELET# Q0 UMKN /Hybrid /Hybrid /Hybrid /Hybrid UMKN Q0 UMKN Q0 EI_LK_V.KOHM RN0 EI_T_V.KOHM RN0 Optimus EI_LK_PH R /Optimus EI_LK_V EI_T_PH R /Optimus EI_T_V _T_PH _LK_PH Q UMKN /Hybrid /Hybrid /Hybrid /Hybrid UMKN Q PU_EI_ELET# Q UMKN UMKN Q Optimus _T_PH _LK_PH +V _T_PH /Hybrid RN0.KOHM _LK_PH /Hybrid RN0.KOHM RT T 0KOHM RN0 RT LK 0KOHM RN0 R0 /Optimus RT T R /Optimus RT LK TM_TRLLK /Hybrid RN.KOHM TM_TRLT /Hybrid RN.KOHM HMI_LK /Hybrid RN.KOHM HMI_T /Hybrid RN.KOHM TM_TRLLK R /Optimus TM_TRLT R /Optimus TM_HP R /Optimus +V HMI_LK_L HMI_T_L HMI_HP_L Q N00 PU_HP_INTR#_R +V +V R0 R 00KOhm 00KOhm /Hybrid /Hybrid PU_EI_ELET# Q0 UMKN /Hybrid PU_EI_ELET Q0 UMKN /Hybrid +V R 0KOhm EI_ELET# R 0KOhm EI_ELET# TM_HP R HMI_HP 0 L_L_PWM L_KLTTL_PH L_KLTTL_PH PU_PWM_ELET Q0 Q0 UMKN UMKN /Hybrid /Hybrid /Hybrid /Hybrid UMKN UMKN Q0 Q0 PU_PWM_ELET# L_L_PWM_ON R L_KLTTL_PH /Optimus L_L_PWM_ON 該部分零件放置于 V onnector J0 附近, V_ORE_PWR +V R 0KOhm +V R 00KOhm /Hybrid PU_PWM_ELET# +V R 00KOhm /Hybrid PU_PWM_ELET#_R Low : E High : ipu +V R 0KOhm PU_PWM_ELET#_PIO R0 0KOhm R 00KOhm 該部分零件放置于 LV onnector J0 附近 Q0 UMKN Q0 UMKN 0 NW +V 0 R 00KOhm 0.UF/0V Q UMKN /Hybrid PU_PWM_ELET Q UMKN /Hybrid PU_PWM_ELET#_PIO PU_PWM_ELET UTeK OMPUTER IN. N Hybrid witch yunfeng_yan ustom NJv.0 Tuesday, ecember, 00 ate: heet of

IITL MOT UIO POWER +V +V_UIO R /_V 0 U LQVR THERML P 0 0UF/0V 0 0 LY_OP_# Z_OUT_U Z_LK_U 0 +V Z_IN0_U 0 Z_YN_U 0, Z_RT#_U +V +.V R0.0 L /00Mhz 0.UF/V L 00 L L_JUMP jump_0mm_open_mil +V_MP R0 UF/0V +V V_IO 0UF/0V EP PIF_OUT Internal pull high.k igital 0UF/0V R Ohm 0.UF/V Z_LK_U_I V_IO P_EEP U 0 R.,item ENE_ MI_INT_L MI_INT_R +V_MP V PIO0/MI_T PIO/MI_LK P# T_OUT LK V T_IN V_IO YN REET# PEEP LQVR H_PKR H_PKR+ H_PKL+ H_PKL H_PKL+ H_PKL H_PKR H_PKR+ PIFO EP/PIFO PV PK_OUT_R+ PK_OUT_R PV PV PK_OUT_L PK_OUT_L+ 0 PV V V ense LINE_L LINE_R MI_L MI_R ense JREF MONO_OUT MI_L MI_R LINE_L LINE_R 0 0.UF/V +V_UIO P N PVEE HPOUT_R HPOUT_L PVREF MI_VREFO_R 0 MI_VREFO MI_VREFO_L VREF V V 0UF/0V TO PK MP _UIO NLO MOT _HP_R _HP_L MI_VREFOUT_L 0 MI_VREFOUT LO_P VREF_OE 0.UF/V.UF/0V _UIO 0UF/0V +V_UIO T R0.0.UF/0V.UF/0V UF/0V _UIO _UIO _UIO MI_VREFOUT HOOE ONE MI_VREFOUT_L LO_P _HP_R _HP_L UF/0V +V /_V /_V L 00 R U_PWR_F 00KOhm % /_V _UIO MT (P/N:0000) MX (P/N:000000) Vout=.*(+(00K/.K))=.V Vdrop about 0mV@00m R0 R0 R0 U HN# IN 0TUF /_V /_V /_V /_V ET OUT 0UF/0V MI_VREFOUT_L _HP_R _HP_L R.KOhm % _UIO /_V R0.0 /_V MI_VREFOUT_L +V_UIO.UF/0V /_V _UIO R0.0 _UIO FOR NORML FUNTION. TO HP 0UF/0V 0.UF/V R 0KOhm % MI_EXT_R MI_EXT_L T MI_INT_R MI_INT_L UF/0V UF/0V MI_IN I MI_IN I TO INTERNL MI _UIO R0.0 MI_VREFOUT_L R0 MI_EXT_R.KOhm.UF/0V MI_IN E MI_IN E MI_EXT_L.UF/0V TO EXTERNL MI /RF Z_LK_U_I 0 0PF/0V RF 預留 R0 R0 L 00 L 00 L 00 For EMI _UIO ETETION ENE_ 0 _PKR FROM IH R 0KOhm % R % R0.0 KOHM LINEIN ETET. MI_J EXT MI ETET. LINE_J FOR HP ETET. R _PKR P_EEP_ P_EEP KOhm 0.UF/V R.KOhm P EEP <Variant Name> UTeK OMPUTER IN. N OE L yunfeng_yan ustom NJv Friday, ecember, 00 ate: heet of.0

MUTE ONTROL EP 0, Z_RT#_U 0 OP_# FROM E 0 NW 0 TW LY_OP_# LY_OP_# H_PKR+ H_PKR H_PKL+ H_PKL H_PKR+ H_PKR FOR EMI E H_PKL+ H_PKL L 00 L 00 L 00 L 00 UF/0V UF/0V H_PKR+_ON H_PKR_ON FOR EMI H_PKL+_ON H_PKL_ON Wto_ON_P IE IE J0 0000F 0 K 0 K 0 K 0 K UTeK OMPUTER IN. N ustom NJv UIO MP yunfeng_yan ate: Friday, ecember, 00 heet of.0

INTERNL MIROPHONE MI_VREFOUT R0.KOhm INT_MI_P INT_MI_P R0 % MI_IN I MI_IN I INT_MI_N INT_MI_N L0 00 EMI E 0, add change L0 to Ohm Resistor for E _UIO <Variant Name> UTeK OMPUTER IN. N ustom NJv MI yunfeng_yan ate: Friday, ecember, 00 heet of.0

modify 00 J0 0 0 0 0 ET_RXN_ ET_RXP_ +V U_PN_ON U_PP_ON +V 0 0.0UF/V 0 0.0UF/V L0 RP L0 RP _HP_R LINE_J _HP_L MI_IN E MI_J ET_TXP 0 ET_TXN 0 ET_RXN 0 ET_RXP 0 U_PN0 U_PP0 0 00PF/0V 00// for EMI +V +V 0 0.UF/V 00// swap _UIO L0 00 PIF_OUT 0 0.UF/V WTO_ON_0P _UIO _UIO pin define Follow U0 IO cable UTeK OMPUTER IN. N **** H_Lin NJ Friday, ecember, 00 ate: heet of.0

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