CHARACTERIZATION OF DEEP REACTIVE ION ETCHING (DRIE) PROCESS FOR ELECTRICAL THROUGH-WAFER INTERCONNECTS FOR PIEZORESISTIVE INERTIAL SENSORS Maria Suggs, Physics Major, Southern Polytechnic State University P.I.: Prof. Beth Pruitt, Mentors: Alvin Barlian & Nahid Harjee Dept. of Mechanical Engineering, Stanford University Summer 2007
MOTIVATION: PROBLEM: Currently, metal interconnects of piezoresistive inertial sensors are exposed to harsh environments (liquid) SOLUTION: Place metal on the unexposed side of the device s chip. This method requires etching through the wafer. Electrical Through Wafer Interconnects from Chow, 2001
PROCEDURE: Optimize the existing recipe on STS-HRM (Surface Technology Systems) Based on the results develop a reliable method to etch through wafer
ETCH PROCESS AND GOALS Bosch Method Etch SF 6 (chemical and physical process) and Dep C 4 F 8 (to protect the side walls) Anisotropic etching, straight walls (90 < with photoresist) No grass Small scallops
ETCH PROCESS AND GOALS Bosch Method Etch SF 6 (chemical and physical process) and Dep C 4 F 8 (to protect the side walls) Anisotropic etching, straight walls (90 < with photoresist) No grass Small scallops
ETCH PROCESS AND GOALS Bosch Method Etch SF 6 (chemical and physical process) and Dep C 4 F 8 (to protect the side walls) Anisotropic etching, straight walls (90 < with photoresist) No grass Small scallops
ETCH PROCESS AND GOALS Bosch Method Etch SF 6 (chemical and physical process) and Dep C 4 F 8 (to protect the side walls) Anisotropic etching, straight walls (90 < with photoresist) No grass Small scallops
STS-HRM: Surface Technology Systems Bosch Method
SI WAFER PROCESS silicon photoresist SUPPLY ROOM SVGCOAT KARLSUSS 4 Silicon Wafer Thickness: ~500 microns Spin 3 microns of positive photoresist (SPR220-3) Expose (and pattern) using a mask with 15% etch area SVGDEVELOP Develop the resist (and hard bake for 30 minutes in 110C oven) STS-HRM: Surface Technology Systems Etch the wafer using a recipe based on the Smooth Shallow Template SEM: Scanning electron microscope Examine the samples and take manual measurements
REPRESENTATIVE SEM IMAGES Optimized Recipe SF 6 was maximized No grass Straight wall Negligible scallops
SI WAFER RECIPE RESULTS Etch Response 5 4.5 Etch Rate (micron/min) 4 3.5 3 2.5 2 1.5 55 45 Platen Power (W) 35 5 3 Etch Cycle Time (sec) 4.5-5 4-4.5 3.5-4 3-3.5 2.5-3 2-2.5 1.5-2 Etch Response 6 5.5 5.5-6 Etch Rate (micron/min) 5 4.5 4 3.5 3 2.5 Gate Position (%) [inv. press] 2 14 12.5 11 5 5-5.5 4.5-5 4-4.5 3.5-4 3-3.5 2.5-3 2-2.5 etch cycle 3 time (s)
THROUGH WAFER ETCHING STS-HRM Challenge: Thermal Conductivity He release and photoresist (PR mask) 40 mt Wafer Platen P (50W) RF Coil P (2500 W) (1500 W) Polymer Bonding 10um He 10 T Chuck (Al) Bonding resist 2um Oxide 0.5um Backing wafer PR mask Coolant at 0 C 20 C
POLYMER BONDING PROCESS Place wafers on 90 C hot plate for 7 min Test the bond with the vacuum for 5 min STS-HRM: Smooth Shallow Template Coil P (1500 W) Separate wafers by soaking in Acetone for 1 hour
THROUGH WAFER RESULTS
CONCLUSION AND FUTURE WORK CONCLUSION Based on the optimization experiment in STS-HRM, reducing the thermal load by decreasing the source power was the key to bonded wafer through etching A wafer-to-wafer polymer bonding technique and a release method were developed for successful through wafer etching in the high rate STS-HRM machine. FUTURE WORK Explore other methods for through wafer (Aluminum as an etch stop) Work on setting up the interconnects through the etched wafer and test the device in harsh environments.
WHAT I LEARNED Trained in various equipment in the clean room such as SVGcoat, Karlsuss, STS-HRM, SEM, wetbenches, YesOven, SVGDev, Nanospec, etc Fabrication process in MEMS The experience of graduate work with students and professors How to conduct my own research
ACKNOWLEDGEMENTS I would like to thank the following people & institutions: Mike Deal and Maureen Baran Prof. Beth Pruitt, Alvin Barlian, Nahid Harjee, Ed Myers, Laura Robeck REU staff at SNF and NNIN National Science Foundation (NSF) Stanford Center for Integrated Systems (CIS) Lab members and staff Special thank you to Eric Perozziello Dr. Patrick & Dr. Pace