- Fall 2002 Lecture 25 Interconnect Effects I/O, Power Distribution Announcements Homework 9 due next Tuesday Hardware lab this week Project phase 2 due in two weeks 1
Today s Lecture Impact of interconnects» I/O» Power distribution Interconnect Issues 2
Impact of Interconnect Parasitics Reduce Robustness Affect Performance Classes of Parasitics Capacitive Resistive Inductive INTERCONNECT Dealing with Capacitance 3
Capacitive Crosstalk Dynamic Node V DD CLK C XY Y In 1 In 2 In 3 PDN C Y X 2.5 V CLK 0 V 3 x 1 µm overlap: 0.19 V disturbance Capacitive Crosstalk Driven Node X 0.5 0.45 0.4 0.35 R C τ Y XY = R Y (C XY +C Y ) XY V 0.3 X Y t r C 0.25 Y V (Volt) 0.2 0.15 0.1 0.05 Keep time-constant smaller than rise time 0 0 0.2 0.4 0.6 0.8 1 t(sec) x 10-9 4
Delay Degradation C c - Impact of neighboring signal activity on switching delay - When neighboring lines switch in opposite direction of victim line, delay increases Miller Effect - Both terminals of capacitor are switched in opposite directions (0 V dd, V dd 0) - Effective voltage is doubled and additional charge is needed (from Q=CV) Interconnect Projections Low-k dielectrics Both delay and power are reduced by dropping interconnect capacitance Types of low-k materials include: inorganic (SiO 2 ), organic (Polyimides) and aerogels (ultra low-k) The numbers below are on the conservative side of the NRTS roadmap e Generation 0.25 µm 0.18 µm 0.13 µm 0.1 µm 0.07 µm 0.05 µm Dielectric Constant 3.3 2.7 2.3 2.0 1.8 1.5 5
How to Battle Capacitive Crosstalk Shielding wire GND V DD GND Shielding layer Avoid large crosstalk cap s Avoid floating nodes Isolate sensitive nodes Control rise/fall times Shield! Differential signalling Substrate (GND) Driving Large Capacitances t phl = C L V swing /2 V DD I av V in C L V out Transistor Sizing 6
Using Cascaded Buffers In Out 1 2 N C L = 20 pf 0.25 mm process Cin = 2.5 ff tp0 = 30 ps F = CL/Cin = 8000 fopt = 3.6 N = 7 tp = 0.76 ns Output Driver Design Trade off Performance for Area and Energy» Given t pmax find N and f Area A driver Energy E driver = = N 2 N 1 f 1 F 1 ( 1+ f + f +... + f ) Amin = Amin = Amin f 1 f 1 2 N 1 2 F 1 2 CL 2 ( + f + f +... + f ) C V = C V V 1 i DD i DD DD f 1 f 1 7
Output Driver Design 0.25 mm process, C L = 20 pf Transistor Sizes for optimally-sized cascaded buffer t p = 0.76 ns Transistor Sizes of redesigned cascaded buffer t p = 1.8 ns Reducing the swing t phl = C L V swing /2 I av Reducing the swing potentially yields linear reduction in delay Also results in reduction in power dissipation Delay penalty is paid by the receiver Requires use of sense amplifier to restore signal level Frequently designed differentially (e.g. LVDS) 8
Tristate Buffers V DD V DD En In En Out Out En In En How to Design Large Transistors D(rain) Multiple Contacts Reduces diffusion capacitance S(ource) G(ate) small transistors in parallel 9
Bonding Pad Design Bonding Pad GND 100 µm Out V DD In GND Out ESD Protection V DD PAD R D1 D2 X C Diode 10
ESD Protection When a chip is connected to a board, there is unknown (potentially large) static voltage difference Equalizing potentials requires (large) charge flow through the pads Diodes sink this charge into the substrate need guard rings to pick it up. Chip Packaging L Bonding wire L Chip Lead frame Mounting cavity Bond wires (~25µm) are used to connect the package to the chip Pads are arranged in a frame around the chip Pads are relatively large (~100µm in 0.25µm technology), with large pitch (100µm) Pin Many chips areas are pad limited 11
Pad Frame Layout Die Photo Chip Packaging An alternative is flip-chip :» Pads are distributed around the chip» The soldering balls are placed on pads» The chip is flipped onto the package» Can have many more pads 12
INTERCONNECT Dealing with Resistance Impact of Resistance We have already learned how to drive RC interconnect Impact of resistance is commonly seen in power supply distribution:» IR drop» Voltage variations Power supply is distributed to minimize the IR drop and the change in current due to switching of gates 13
RI Introduced Noise V DD I φ pre R V DD - V X V I R V Power and Ground Distribution V DD GND Logic Logic V DD V DD GND (a) Finger-shaped network GND (b) Network with multiple supply pins 14
Resistance and the Power Distribution Problem Before After Requires fast and accurate peak current prediction Heavily influenced by packaging technology Source: Simplex Power Distribution Low-level distribution is in Metal 1 Power has to be strapped in higher layers of metal. The spacing is set by IR drop, electromigration, inductive effects Always use multiple contacts on straps 15
Electromigration (1) Limits dc-current to 1 ma/µm Electromigration (2) 16
The Impact of Resistivity T r The distributed rc-line R 1 R 2 R N-1 R N C 1 C 2 C N-1 C N V in 2.5 2.5 Diffused signal propagation Delay ~ L 2 voltage (V) voltage (V) 2 2 1.5 1.5 1 1 0.5 0.5 x= L/10 x= L/10 x = L/4 x = L/4 x = L/2 x = L/2 x= L x= L 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.5 1.5 2.5 3.5 4.5 0 1 2 3 4 5 time (nsec) time (nsec) d The Global Wire Problem w w ( R C + R C R C ) T = 0.377R C + 0.693 + Challenges No further improvements to be expected after the introduction of Copper (superconducting, optical?) Design solutions» Use of fat wires» Insert repeaters but might become prohibitive (power, area)» Efficient chip floorplanning Towards communication-based design» How to deal with latency?» Is synchronicity an absolute necessity? d out d w w out 17
Reducing RC-delay Repeater Interconnect: # of Wiring Layers # of metal layers is steadily increasing due to: Tins r = 2.2 mw-cm M6 Increasing die size and device count: we need more wires and longer wires to connect everything W S M5 Rising need for a hierarchical wiring network; local wires with high density and global wires with low RC H M4 3.5 Minimum Widths (Relative) 4.0 Minimum Spacing (Relative) 3.0 3.5 substrate M3 M2 M1 poly 0.25 µm wiring stack 2.5 2.0 1.5 1.0 0.5 0.0 1.0m 0.8m 0.6m 0.35m 0.25m M5 M4 M3 M2 M1 Poly 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0m 0.8m 0.6m 0.35m 0.25m M5 M4 M3 M2 M1 Poly 18
Interconnect Projections: Copper Copper is planned in full sub-0.25 µm process flows and large-scale designs (IBM, Motorola, IEDM97) With cladding and other effects, Cu ~ 2.2 µω-cm vs. 3.5 for Al(Cu) 40% reduction in resistance Electromigration improvement; 100X longer lifetime (IBM, IEDM97)» Electromigration is a limiting factor beyond 0.18 µm if Al is used (HP, IEDM95) Vias INTERCONNECT Dealing with Inductance 19
Common Wire Cross-Sections Coaxial Cable Triplate Strip Line MicroStrip Wire above Ground Plane 2πε c = log r2 r1 µ l = log 2π r2 r1 ε c = h W h l = µ W cl = εµ c - capacitance/length l - inductance/length L di/dt Vin V DD L V DD i(t) V out Impact of inductance on supply voltages: Change in current induces the change in voltage Longer supply lines have larger L C L GND L 20
L di/dt: Simulation 5.0 v out 5V t V out (V) 4.0 3.0 2.0 1.0 0.0 t fall = 4 nsec t fall = 0.5 nsec i L 40mA 20mA t I L (ma) 20 10 v L 0 0.5 0.2V t V L (V) 0.3 0.1-0.1-0.3 2 4 6 8 10 t (nsec) Signals Waveforms for Output Driver connected To Bonding Pads (a) v out ; (b) i L and (c) v L. The Results of an Actual Simulation are Shown on the Right Side. Choosing the Right Pin Bonding wire L Chip Mounting cavity L Lead frame Pin 21
Decoupling Capacitors Board wiring Bonding wire SUPPLY C d CHIP Decoupling capacitor Decoupling capacitors are added: on the board (right under the supply pins) on the chip (under the supply straps, near large buffers) De-coupling Capacitor Ratios EV4» total effective switching capacitance = 12.5nF» 128nF of de-coupling capacitance» de-coupling/switching capacitance ~ 10x EV5» 13.9nF of switching capacitance» 160nF of de-coupling capacitance EV6» 34nF of effective switching capacitance» 320nF of de-coupling capacitance -- not enough! Source: B. Herrick (Compaq) 22
EV6 De-coupling Capacitance Design for Idd= 25 A @ Vdd = 2.2 V, f = 600 MHz» 0.32-µF of on-chip de-coupling capacitance was added Under major busses and around major gridded clock drivers Occupies 15-20% of die area» 1-µF 2-cm 2 Wirebond Attached Chip Capacitor (WACC) significantly increases Near-Chip decoupling 160 Vdd/Vss bondwire pairs on the WACC minimize inductance Source: B. Herrick (Compaq) EV6 WACC 389 Signal - 198 VDD/VSS Pins 389 Signal Bondwires 395 VDD/VSS Bondwires 320 VDD/VSS Bondwires WACC Microprocessor Heat Slug 587 IPGA Source: B. Herrick (Compaq) 23
Design Techniques to address L di/dt Separate power pins for I/O pads and chip core Multiple power and ground pins Position of power and ground pins on package Increase tr and tf Advanced packaging technologies Decoupling capacitances on chip and on board The Transmission Line V in r l r l r l x r l V out g c g c g c g c The Wave Equation 24
Lossless Transmission Line - Parameters speed of light in vacuum Wave Propagation Speed 25
Wave Reflection for Different Terminations Transmission Line Response (R L = ) 5.0 4.0 V 3.0 2.0 V Dest V Source 1.0 0.0 4.0 3.0 R S = 5Z 0 (a) V 2.0 1.0 0.0 8.0 6.0 R S = Z 0 (b) V 4.0 2.0 R S = Z 0 /5 0.0 0.0 5.0 t (in t 10.0 15.0 lightf ) (c) 26
Lattice Diagram V Source V Dest 0.8333 V 2.2222 V + 0.8333 + 0.8333 + 0.5556 1.6666 V + 0.5556 2.7778 V t 3.1482 V + 0.3704 + 0.3704 3.5186 V 3.7655 V + 0.2469 + 0.2469 4.0124 V... L/ν Critical Line Lengths versus Rise Times L crit ~ 1cm 100-200ps today (1990, Bakoglu) 27
Design Rules of Thumb Transmission line effects should be considered when the rise or fall time of the input signal (t r, t f ) is smaller than the time-of-flight of the transmission line (t flight ). t r (t f ) << 2.5 t flight Transmission line effects should only be considered when the total resistance of the wire is limited: R < 5 Z 0 The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance, R < Z 0 /2 Should we be worried? Transmission line effects cause overshooting and nonmonotonic behavior Clock signals in 400 MHz IBM Microprocessor (measured using e-beam prober) [Restle98] 28