Topic 3: Combinational Logic Fundamentals In this note we will study combinational logic, which is the part of digital logic that uses Boolean algebra. All the concepts presented in combinational logic can be implemented using logic gates, which are identified to be basic elements of combinational logic. In topic 4, we will study some aspects of their physical implementation. Objectives: - Understand the theory of Boolean algebra and its application in combinational logic. - Understand the behavior of basic logic gates. - Understand the principle of minimization of combinational functions using Karnaugh Maps. Combinational logic networks only process information. Their output signal values depend entirely on input signal values at each instant of time; we usually think of then as acting instantaneously. Switching theory deals with binary variables {x i } whose two values are represented by bits (binary digits) 0 and 1. A combinational (switching) function is a mapping z: K n K, where K = {0,1} and K n denotes the set of 2 n binary n-tuples. Any combinatory function can, in principle, be defined by a truth table, which specifies for every input combination (x 1, x 2,.x n ) the corresponding z(x 1, x 2,.x n ). Logic diagrams, truth tables, timing diagrams are use to represent functions realize by combinational systems. Figure 3.1gives an example of a truth table that defines two-variable functions z(x 0,y 0, c 0 ) and c 1 (x 0,y 0,c 0 ). Inputs Outputs x 0 y 0 c 0 z 0 c 1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Figure 3.1. Truth table for 3-variable combinational functions: z 0 (sum) and c 1 (carry). Figure 3.2 shows different mode of representation of a logic network. 1
Figure 3.2. An example of logic networks. Combinational functions do not involve time, in this manner; they can be used to represent the behavior of any logical operation or binary numerical operation. 3.1. Boolean Algebra. An alternative approach to truth table of a logic function is to the use of algebraic expressions in which variables represent binary logic signals and the operators of the algebra represent gate functions. The algebra, which models combinational circuits, is a type of Boolean algebra, which originated with the work of George Boole (1815-1864). Boolean algebra, like any algebra, is defined by a set of elements K, a set of operators P over K, and a set of axioms or laws defining the properties of P and K. It is convenient to let P = { and, or, not} and K = {0,1}. 2
AND, OR, NOT are the standard gate operators. The more common and useful laws of Boolean algebra are summarized in figure 3.3. Given a, b of K, a AND b = ab; a OR b = a+b, NOT a = a'. No. Statement of axiom Name 1 There exits elements 0, 1 of K such that Existence of identity elements a + 0 = a a1 = a 2 a +b = b+a Commutative Laws ab = ba 3 a(b+c) = ab + ac Distributive Laws a +(bc) = (a+b)(a+c) 4 For every a K, there exists a' K such that Existence of Inverse aa' = 0 a + a' = 1 5 a + (b +c) = (a + b) + c Associative Laws a(bc) = (ab)c 6 a + a = a Idempotent Laws aa = a 7 (a+b)' = a'b' De Morgan s Laws (ab)' = a' + b' 8 (a')' = a Involution Figure 3.3. The basic laws of Boolean algebra (a, b and c are arbitrary elements of K). Notation: In this note, for a given element x of K complement ( x) = x' = x To enable us to deal with a number of variables, it is useful to define some two- and three-variable algebraic identities. For each identity, its dual version is also given. These identities are often referred to as properties. If a, b, and c are the variables in K, then the following properties hold: Absorption a) a +ab = a b) a(a+b) = a c) a + a'b = a+b d) a(a' + b) = ab Consensus a) ab + a'c + bc = ab + a'c b) (a+b)(a' + c)(b + c) = (a +b)(a' + c) Principle of Duality: Any theorem or identity in Boolean algebra remains true if 0 and 1 are swapped and. and + are swapped throughout. n-variable Theorems (Textbook pp. 200 206) The following table shows several n-variable important theorems: Statement of Theorem Name X + X + X..+X = X Generalized idempotency X.X.X.X = X (X1.X2.Xn) = X1 + X2 +.+ Xn (Demorgan s Theorems (X1+ X2+ +Xn) = X1.X2..Xn [F(X1,X2,,Xn, +,.)] = F(X1, X2,,Xn,., +) (Generalized Demorgan s theorem) F(X1,X2,X3,.Xn) = X1.F(1,X2,.Xn) + X1.F(0,X2,..Xn) Shannon s expansion theorems F(X1,X2, Xn) = [X1+F(0,X2,,Xn)].[X1 + F(1,X2, Xn)] 3
Most of these theorem can be proved using a two-step method called finite induction First proving that the theorem is true for n = 2 ( that basis step) and then proving that if the theorem is true for n = I, then it is also true for n = I +1 ( the induction step). Shannon s expansion theorems are demonstrated by considering the dual concept.: If F(X1, X2,.., Xn, +,., ) is a fully parenthesized logic expression involving the variable X1, X2, Xn and the operators +,., and, then the dual of F, written F D, is the same expression with +, and. swapped: F D (X1,X2,,Xn, +,., ) = F(X1, X2, X3,.,Xn,., +, ) The fundamental design problem for combinational circuits may be expressed as follows. Design a logic circuit to realize a given set of combinational functions using minimum number of gates. These techniques are based on the correspondence between two-level combinational circuits and Boolean equations of the form: N f ( x, x,..., x N = m i And 0 1 ) i= 0 f ( x, x o 1,..., xn ) i N = = i= 0 M i Where Σ and Π denote the logical sum (OR, SOP: sum-of-product) and product (AND, POS: product-of-sum) operations, and m i the minterm and M i the maxterm. For example for N = 2 n -1 and n =3 (x 0, x 1, x 2 ) we have the following expressions for the minterm and maxterm. Msb = x 0, Lsb = x 2 Minterm Maxterm m 0 = x 0 'x 1 'x 2 ' (equivalent code of 0) M 0 = x 0 + x 1 + x 2 m 1 = x 0 'x 1 'x 2 M 1 = x 0 + x 1 + x 2 ' m 2 = x' 0 x 1 x 2 ' M 2 = x 0 + x 1 ' + x 2 ' m 3 = x 0 'x 1 x 2 M 3 = x 0 + x 1 ' + x 2 ' m 4 = x 0 x 1 'x 2 ' M 4 =x 0 ' + x 1 + x 2 m 5 = x 0 x 1 'x 2 M 5 = x 0 ' + x 1 + x 2 ' m 6 = x 0 x 1 x 2 ' M 6 = x 0 ' + x 1 ' + x 2 m 7 = x 0 x 1 x 2 (equivalent code of 7) M 7 = x 0 ' +x 1 ' +x 2 ' A Boolean function F may be represented by a sum (ORed together) of its minterms. They represent the input combinations needed to yield F = 1. So minterms represent the 1 s in the truth table for F. A Boolean function F may be represented by a product (ANDed together) of its maxterms. They represent the input combinations needed to yield F = 0. So maxterms represent the 1 s in the truth table for F. We have m i = M i ' and M i = m i ' Using minterms or maxterms to represent a combinational function represent the canonical form in which the expressions are not minimized. The same function can be represented in a standard form with minimized expressions (sums and products). Some definitions: - A literal is a variable or the complement of a variable. Examples: X, Y, X, Y. - A product term is a single literal or logic product of two or more literals. Examples: Z, WXY, XY Z. - A sum-of-products expression is a logical sum of product terms. Example: Z + WXXY + XY Z. - A sum term is a single literal or logical sum of two or more literals. Examples: Z, W + X + Y, X + Y + Z. - A product-of-sums expression is a logical product of sum terms. Example: Z (W + X + Y)(X+Y +Z). - A normal term is a product or sum term in which no variable appears more than once. 4
- The canonical sum of a logic function is a sum of the minterms corresponding to truth-table rows (input combinations) for which the function produces a 1 output. Example: F = X, Y, Z ( 0,3,4,6,7) = X ' Y ' Z' + X ' YZ + XY ' Z' + XYZ' + XYZ. - The canonical product of a logic function is a product of the maxterms corresponding to input combinations for which the function produces a 0 output. Example: F = ( 1,2,5) = ( X + Y + Z')( X + Y ' + Z)( X ' + Y + Z'). X, Y, Z 3.2. Gates and Circuits. A physical realization of a combinatory function is called a combinatory circuit. Combinational circuits are connected from standard components called gates, which themselves realize very simple combinational functions. The most important gate types are listed in figure 3.4. Figure 3.4 Major logic gate types. 5
The function performed by each gate is defined by a truth table. Gates will be represented in logic diagrams by the special symbols shown in figure 2.4. 3.3. Gate Minimization An SOP expression E for a function f is said to be minimal if it contains the smallest possible number of product terms among all SOP expressions defining f, and if as a secondary condition, no literals can be deleted from any of the product terms without changing the function specified by E. A two-level circuit corresponding to E is also minimal in the sense that it contains the fewest gates among all AND-OR circuits realizing f, and the fan-in of none of the AND gates can be reduced. Minimal POS expressions and OR-AND circuits can be defined analogously. There are three common methods for minimizing combinational expression: a) Boolean algebra The basis for all methods Difficult to see the best path to take and to know which law to be used b) Karnaugh Maps Pictorial approach based on recognition of patterns Fast and easy for 2 6 variables Difficult for large numbers of variables c) Tabulation methods Tedious to perform by hand, but well suited to computer implementation Not limit on the number of variables In this paragraph, we will present K-map as method gate minimization. It was developed by Maurice Karnaugh at AT&T Bell Lab in 1950. The K-map is based on the principle of looping 2 i "1" adjacent. By doing, we eliminate variables that appear in complemented and uncomplemented forms. 3.3.1. Karnaugh Maps (K-maps) Essentially a 2D truth table arrange in a table or map so that adjacent cells in the map differ in only one bit position. Each cell in the map corresponds to a minterm Combining 1 s in the Kmap into groups of 1, 2, 4, 8, etc. can yield a quick minimization of the combinational function Configurations: 6
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a) Minimizing Sums of Products Karnaugh minimization is based on the principle of the groupment of 2 i cells of adjacent 1, which itself lies on the fact that Y.term + Y.term = term, with: - Y = variable for two adjacent 1 cells, - Y = a product of two variables for four adjacent 1 cells, - Y = a product of three variables for eight adjacent 1 cells, - Y = a product of four variables for sixteen adjacent 1 cells. Term is also called a prime implicant as defined below. Different configurations of adjacent 1s will be given in class. 9
Some Definitions (Figure 3.5 = Fig. 4.31 Textbook): A minimal sum of a logic function F(X1,.., Xn) is a sum-of-products expression for F such that no sum-of-products for F such that no sum-of-products expression for F has fewer products terms, and any sum-of-products expression with the same number of product terms has at least as many literals. A logic function P(X1,., Xn) implies a logic functions F(X1, Xn) if for every input combination such that P = 1, then F = 1 also. A prime implicant of a logic function F(X1,.,Xn) is a normal product term P(X1,,Xn) that implies F, such that if any variable is removed from P, then the resulting product term does not imply F. Prime-Implicant theorem: A minimal sum is a sum of prime implicants. Figure 3.5: (a) Karnaugh map; (b) prime implicants. The sum of all prime implicants of a logic function is called the complete sum. Although the complete sum is always a legitimate way to realize a logic function, it s not always minimal (Figure 3.6 = Figure 4.32 Textbook). It s therefore important in the minimization process to know which prime implicants to leave out. This can be done by considering the following definitions : - A distinguished 1-cell of a logic function is an input combination that is covered by only one prime implicant. - An essential prime implicant of a logic function is a prime implicant that covers one or more distinguished 1-cells. The minimal sum is obtained by identifying the distinguished 1-cells and the corresponding prime implicants and include the essential prime implicants in the minimal sum (Figure 4.33 textbook) Figure 3.6: (a) Karnaugh map; (b) prime implicants and distinguished 1-cells. 10
In the example of figure 3.6, all of the 1-cells are covered by essentials prime implicants, so we need go no further. We have a different configuration in figure 3.7, the approach consist of removing the essential prime implicants and the 1-cells they cover, the remaining prime implants will be added to the minimum sum. Figure 3.7: (a) Karnaugh map; (b) prime implicants and distinguished 1-cells; (c) reduced map after removal of essential prime implicants and covered 1-cells. The following example shows a more difficult case: a logic function with no essential prime implicant. 11
Another useful way of describing the Karnaugh algorithms consists of steps that show how to use K-map method for simplifying a Boolean Expression: 1. Construct the K map and place 1s in those squares corresponding to the 1s in the truth table. Place 0s in the other squares. 2. Examine the map for adjacent 1s and loop those 1s, which are not adjacent to any other 1s. They are called isolated 1s. 3. Next, look for those 1s, which are adjacent to only one other 1. Loop any pair containing such a 1. 4. Loop any octet event it contains some 1s that have already been loop 5. Loop any quad that contains one or more 1s that have not already been looped, making sure to use the minimal number of loops. 6. Loop any pairs necessary to include any 1s that have not yet been looped, making sure to use the minimal number of loops. 7. Form the OR sum of all the terms generated by each loop. Examples (figures 3.8 & 3.9) Figure 3.8. Examples of looping pairs of adjacent 1s. 12
Figure 3.9. More K-maps 13
b) Simplifying Products of sums: the principle of duality is applied. We consider the 0s on a Karnaugh map and express F. c) Don t care combination (textbook, page 232). 3.4. Design Example: Three-way Light Control Assume that a large room has tree doors and that a switch near each door controls a light in the room. It has to be possible to turn the light on or off by changing the state of any one of the switches. As a first step, let us turn this word statement into a formal specification using a truth table. Let x 1, x 2 and x 3 be the input variables that denote the state of each switch. Assume that the light is off if all switches are open. Closing any one of the switches will turn the light on. Then turning on a second switch will have to turn off the light. Thus the light will be on if exactly one switch is closed, and it will be off if two (or no) switches are closed. If the light is off when two switches are closed, then it must be possible to turn it on by closing the third switch. If f(x 1, x 2, x 3 ) represents the state of the light, then the required functional behavior can be specified as shown in the truth table in figure 3.10. x 1 x 2 x 3 f 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Figure 3.10: Truth table for the three-way light control. The canonical sum-of-products expression for the specified function is f = m 1 + m 2 + m 4 + m 7 = x 1 'x 2 'x 3 + x 1 'x 2 x 3 ' + x 1 x 2 'x 3 ' + x 1 x 2 x 3 This expression cannot be simplified into a lower-cost sum-of-products expression. The resulting circuit is shown in Figure 3.11a. An alternative realization for this function is in the product-of-sums forms. The canonical expression of this type is f = M 0.M 3.M 5.M 6 = (x 1 + x 2 + x 3 ). (x 1 + x 2 ' + x 3 '). (x 1 ' + x 2 + x 3 '). (x 1 ' + x 2 ' + x 3 ) The resulting circuit is depicted in figure 3.8b. It has the same cost as the circuit in part (a) of the figure 3.11. 14
Figure 3.11. Implementation of the function in figure 3.10. 15