A Universal Memory Model for Design Exploration Ketul Sutaria, Chi-Chao Wang, Yu (Kevin) Cao School of ECEE, ASU
Universal Memory Modeling because there is no universal memory device! Modeling needs in light of scaling A top-down view: Finite-State Machine (FSM) Type I and Type II memories Modeling examples: Flash, PCM, and MRAM Summary -2-
Scaling Trend: Logic Device Bulk/SOI MOSFET Strained MOSFET HKMG MOSFET MG MOSFET Dominated by silicon based CMOS Dedicated compact model, such as BSIM and PSP, to describe the physics underneath Bottom-up modules: electro-static and transport Future abstraction, using I on and I off, for fast design evaluation Common behavior to cover post-si FET devices -3-
Scaling Trend: Memory Device SRAM Flash PCM STT DRAM FRAM RRAM Tremendous variety in memory physics, materials, structures, and devices! SRAM and DRAM used to be the mainstream 3D technology, such as TSV, offers future opportunity of heterogeneous integration -4-
Design Perspective Speed Power Density, Date-Retention, Speed (R/W), Power, Voltage, Compatibility, Reliability Diverse design needs drive the development and selection of different types of memory -5-
Headline News Much more technological choices for memory design Still, there is no universal solution -6-
Modeling of Memory Devices From discrete, bottom-up approaches to a universal model Essential to efficiently bridge technology evaluation and design choice -7-
A Top-Down View General Behavior: A Finite-State Machine (FSM) 1 0 0 1 1 0 The diagram of finite states is the formal and general method to describe a sequential unit The state may be defined as the output data (0 and 1), which can be a electrical signal or other physical values The transition/retention mechanisms distinguish one type of memory from another type -8-
Equivalent Circuit Diagram Input Control Output Control Static, Monotonic A common modeling structure for SPICE simulation Cell: performs the state transition and data retention Input control: translates the input signals for Write Output control: translates the output signals for Read Physical modules to cover various types of memories -9-
Two Types of Memory Type I Type II Two types based on the forces of cell operation Forces for 1 0 or 0 1 can be different Type I: external force only to stabilize/distinguish states Type II: both internal and external forces to control the states self-feedback mechanisms for meta-stability -10-
Modeling Examples DRAM SRAM DRAM: Type I Read and Write through the same resistor, but different capacitances SRAM: Type II Feedback between the cross-coupled inverters for data retention -11-
More Classifications Category Program (t) Erase (t) States Retention DRAM Charging Discharging Q in Cap (VM) Refresh Q Type I Type II Flash Charging (Hot carrier/ Tunneling) Discharging (Hot carrier/ Tunneling) Q in/out FG (NVM) PCM High voltage/current Reverse reaction Resistance (Amorphous/crystal states) (NVM) RRAM Conducting path (low R) Removal of the path Resistance change (NVM) SRAM Charging Discharging Q + positive feedback (VM) MRAM- MTJ FeRAM Spin alignment (currentinduced magnetic field) E-Field to change the polarization Reverse magnetic field Reverse E-Field * Magneto resistance (NVM) Polarizations (NVM) Device structure/material material material positive feedback material material Different operation modes may involve different physical forces -12-
Flash (Type I) V CG V FG C CG C FG V CG V FG C FG I G =f(v FG -V CH ) V FG is changed by carrier injection and regarded as the state value The program/erase is through the tunneling current, I G When V CG is applied, I G is activated Voltage difference between V FG and V CH determines I G -13-
SPICE Simulation vs. TCAD 4.0 DC simulation 1.05 1.04 Transient V FG (V) 3.0 2.0 V FG (V) 1.03 1.02 1.01 1 1.0 0.0 Symbol: TCAD Line: Model 3 5 6 7 8 9 10 11 12 13 14 15 16 0.99 0.98 0.97 Symbol: TCAD Line: Model V CG (V) Time (s) The model is implemented through sub-circuit and/or Verilog-A SPICE simulation converges well and matches TCAD data, with appropriate tuning of model parameters Read and Write in Flash may have different speeds, depending on the specific tunneling mechanism -14-
PCM (Type I) Top electrode R thermal Chalcogenide Resistor (heater) C thermal Bottom electrode R thermal Chalcogenide exhibits reversible transition between the amorphous and crystalline state, controlled by the temperature profile -15-
Phase Change Behavior 1.2 Resistance (a.u.) 1 0.8 0.6 0.4 0.2 0 Symbol: measurement (A. L. Lacaita, et al., IEDM 04) Line: simulation -0.2 0.0 21.5 45.8 61.4 85.7 92.8 138.4 202.0 259.2 299.1 338.9 375.2 413.3 441.1 497.6 542.0 569.3 593.4 612.2 641.6 665.7 684.7 708.9 731.4 759.1 778.2 795.5 Programming current (µa) The success of phase change (state transition) depends on the magnitude and the width of the input current pulse If not successful, the original phase (state) remains -16-
STT MRAM (Type II) θ dm dt dm 0Ms H M K1 uea M M dt s 2 Zeeman (external) Demagnetization (internal) Anisotropic (internal) Write in STT MRAM requires the magnetization change of one ferromagnetic layer, involves three energies d M dt d H cos M dt 0 s K s θ V sin cos -17-
Dynamic Simulation Magnetization Angle (degree) 180 150 120 90 60 30 0 I < I c I (top left to bottom right) 1000 500 100 50 15 10 Pulse width: 10ns 0.0 1.0x10-7 2.0x10-7 Time (s) The dynamic change is well captured by the model The balance between external/internal (feedthrough/feedback) forces are calculated by SPICE, reducing computation risk and cost -18-
Further Abstraction Out DRAM SRAM STT The transfer characteristic is essential to determine noise margin (stability) and drive strength (speed) Finite points to extract key static/dynamic properties Statistical variability and reliability embedded into finite points In -19-
Summary 1 0 0 1 1 0 A universal SPICE model for various memory devices The generic interface between circuit and device research Easy customization to different physical mechanisms Fully compatible with the SPICE engine -20-