Miscellaneous Lecture topics Mary Jane Irwin [dapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.]
MOS Switches MOS transistors can be viewed as simple switches. In an N-Switch, the switch is closed or ON when there is a 1 on the gate. 0 on the gate results in the switch being open or OFF. The reverse conditions hold true for a P-switch. The P and the N switches are ON and OFF for complementary values of the gate signal. schematic view of the N-switch and P-switch is as shown below: N P 2
NMOS Switch Operation of the N-switch: The load capacitor is initially discharged (Vout =Vss). When a value of 1 is applied to the gate and Vin =1 the transistor conducts and the charges the capacitor to Vdd. s the output voltage reaches the value of Vdd-V t the device is turned off. The N-switch thus conducts an imperfect 1. The 1 voltage value is reduced by an amount V t at the output. V_in V_out C_Load 3
NMOS Switch (contd.) When Vin =0 and the gate is at 1 and Vout = V dd V t, the transistor conducts and discharges the load capacitor to Vss. V out falls to V ss ; hence the transmission of logic 0 is not degraded. The N-switch thus passes a perfect 0. V_in V_out C_Load 4
PMOS Switch Operation of the P-switch: The load capacitor is initially discharged(vout =Vss). When a 0 is applied to the gate and Vin = 1, the transistor conducts and charges the load capacitor to Vdd. The P-switch thus conducts a perfect 1 as the transmission of logic one is not degraded. V_in V_out C_Load 5
PMOS Switch (contd.) When Vin =0 and the gate is at 0 and Vout =V dd, the load capacitor discharges through the p device. When Vout =V t the transistor ceases to conduct. The p-switch thus conducts an imperfect 0. The output falls to V t and not completely to V ss. V_in V_out C_Load 6
CMOS Switch y combining the P-switch and N-switch in parallel we get the Complementary switch or the C switch. This is termed as a Transmission gate or pass gate. This can pass both 0 and 1 perfectly. The schematic for the C switch is as shown: C 7
CMOS Logic Gates The CMOS logic gate consists of a - Pull Up network(pun) of PMOS transistors and - Pull Down network(pdn) of NMOS transistors. Vdd PUN Input Output PDN GND 8
CMOS Logic Gates The PDN is activated when the inputs are high since it is composed of NMOS transistors. The PUN is activated when the input signal at the gate are low since PUN comprises of PMOS transistors. In steady state, either the P-block or the N-block conducts The PUN block acts as a switch that connects the output to Vdd (1). The PDN block switches the output node to GND(0). 9
NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high X Y Y = X if and X Y Y = X if OR NMOS Transistors pass a strong 0 but a weak 1 10
PMOS Transistors in Series/Parallel Connection PMOS switch closes when switch control input is low X Y Y = X if ND = + X Y Y = X if OR = 11 PMOS Transistors pass a strong 1 but a weak 0
Complementary CMOS Logic Style Construction (cont.) 12
13 Example Gate: NND
14 Example Gate: NOR
Example Gate: COMPLEX CMOS GTE V DD C D D C OUT = D + (+C) 15
4-input NND Gate Vdd Out GND 16 In1 In2 In3 In4
Standard Cell Layout Methodology metal1 V DD Well V SS signals Routing Channel polysilicon 17
Two Versions of (a+b).c V DD V DD x x GND GND a c b a b c (a) Input order {a c b} (b) Input order {a b c} 18
VLSI Design flows are taken from http://www.vlsi.wpi.edu/webcourse/about.html 19
20
Long Channel I-V Plot (NMOS) 6 5 4 3 2 X 10-4 V DS = V GS - V T Linear V GS = 2.5V V GS = 2.0V Saturation V GS = 1.5V cut-off 1 0 V GS = 1.0V 0 0.5 1 1.5 2 2.5 V DS (V) NMOS transistor, 0.25um, L d = 10um, W/L = 1.5, V DD = 2.5V, V T = 0.4V
Short Channel Effects ehavior of short channel device mainly due to 10 5 Velocity saturation the velocity of the carriers saturates due to scattering (collisions suffered by the carriers) 0 ξ c = 0 1.5 3 ξ(v/µm) For an NMOS device with L of.25µm, only a couple of volts difference between D and S are needed to reach velocity saturation
Voltage-Current Relation: Velocity For short channel Saturation devices Linear: When V DS V GS V T I D = κ(v DS ) k n W/L [(V GS V T )V DS V DS2 /2] where κ(v) = 1/(1 + (V/ξ c L)) is a measure of the degree of velocity saturation Saturation: When V DS = V DST V GS V T I DSat = κ(v DST ) k n W/L [(V GS V T )V DST V DST2 /2]
Velocity Saturation Effects 10 For short channel devices and large enough V GS V T 0 V DST < V GS V T so the device enters saturation before V DS reaches V GS V T and operates more often in saturation I DST has a linear dependence wrt V GS so a reduced amount of current is delivered for a given control voltage
Short Channel I-V Plot (NMOS) 2.5 2 1.5 X 10-4 Early Velocity Saturation V GS = 2.5V V GS = 2.0V 1 Linear Saturation V GS = 1.5V 0.5 V GS = 1.0V 0 0 0.5 1 1.5 2 2.5 V DS (V) NMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = 0.4V
MOS I D -V GS Characteristics 6 5 4 3 2 1 0 X 10-4 0 0.5 1 1.5 2 2.5 V GS (V) Linear (short-channel) versus quadratic (longchannel) dependence of I D on V GS in saturation Velocity-saturation causes the short-channel device to saturate at substantially smaller values of V DS resulting in a substantial drop in current drive (for V DS = 2.5V, W/L = 1.5)
Short Channel I-V Plot (PMOS) ll polarities of all voltages and currents are reversed -2 V DS (V) -1 0 0 V GS = -1.0V -0.2 V GS = -1.5V -0.4 V GS = -2.0V -0.6-0.8 V GS = -2.5V -1 X 10-4 PMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = -0.4V
The MOS Current-Source Model G I D = 0 for V GS V T 0 S I D D I D = k W/L [(V GS V T )V min V min2 /2](1+λV DS ) for V GS V T 0 with V min = min(v GS V T, V DS, V DST ) and V GT = V GS - V T Determined by the voltages at the four terminals and a set of five device parameters V T0 (V) γ(v 0.5 ) V DST (V) k (/V 2 ) λ(v -1 ) NMOS 0.43 0.4 0.63 115 x 10-6 0.06 PMOS -0.4-0.4-1 -30 x 10-6 -0.1
7 6 5 4 3 2 The Transistor Modeled as a Switch x10 5 S V GS V T R on D Modeled as a switch with infinite off resistance and a finite on resistance, R on Resistance inversely proportional to W/L (doubling W halves R on ) 1 0 0.5 1 1.5 2 2.5 (for V GS = V DD, V DS = V DD V DD /2) V DD (V) For V DD >>V T +V DST /2, R on independent of V DD Once V DD approaches V T, R on increases dramatically V DD (V) 1 1.5 2 2.5 NMOS(kΩ) 35 19 15 13 PMOS (kω) 115 55 38 31 R on (for W/L = 1) For larger devices divide R eq by W/L
Other (Submicon) MOS Transistor Velocity saturation Concerns Subthreshold conduction Transistor is already partially conducting for voltages below V T Threshold variations In long-channel devices, the threshold is a function of the length (for low V DS ) In short-channel devices, there is a drain-induced threshold barrier lowering at the upper end of the V DS range (for low L) Parasitic resistances resistances associated with the source and drain contacts G Latch-up S D R S R D
Subthreshold Conductance 10-2 10-12 Subthreshold exponential region V T Linear region Quadratic region Transition from ON to OFF is gradual (decays exponentially) Current roll-off (slope factor) is also affected by increase in temperature S = n (kt/q) ln (10) (typical values 60 to 100 mv/decade) 0 0.5 1 1.5 2 2.5 V GS (V) I D ~ I S e (qv GS /nkt) where n 1 Has repercussions in dynamic circuits and for power consumption
Subthreshold I D vs V GS I D = I S e (qv GS /nkt) (1 - e (qv DS /kt) )(1 + λv DS ) V DS from 0 to 0.5V
Subthreshold I D vs V DS I D = I S e (qv GS /nkt) (1 - e (qv DS /kt) )(1 + λv DS ) V GS from 0 to 0.3V
CMOS Circuit Styles Static complementary CMOS - except during switching, output connected to either V DD or GND via a lowresistance path high noise margins full rail to rail swing V OH and V OL are at V DD and GND, respectively low output impedance, high input impedance no steady state path between V DD and GND (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes simpler, faster gates increased sensitivity to noise
Static Complementary CMOS Pull-up network (PUN) and pull-down network (PDN) In 1 In 2 In N In 1 In 2 In N V DD PUN PDN PMOS transistors only pull-up: make a connection from V DD to F when F(In 1,In 2, In N ) = 1 F(In 1,In 2, In N ) pull-down: make a connection from F to GND when F(In 1,In 2, In N ) = 0 NMOS transistors only PUN and PDN are dual logic networks
Threshold Drops PUN S V DD V DD D V DD D 0 V DD V GS S 0 V DD - V Tn C L C L PDN V DD 0 V DD V Tp V DD D C L V GS S C L S D
Construction of PDN NMOS devices in series implement a NND function NMOS devices in parallel implement a NOR function +
Dual PUN and PDN PUN and PDN are dual networks DeMorgan s theorems + = = + [!( + ) =!! or!( ) =! &!] [!( ) =! +! or!( & ) =!!] a parallel connection of transistors in the PUN corresponds to a series connection of the PDN Complementary gate is naturally inverting (NND, NOR, OI, OI) Number of transistors for an N-input logic gate is 2N
CMOS Properties Full rail-to-rail swing high noise margins Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless lways a path to V dd or GND in steady state low output impedance (output resistance in kω range) large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors
CMOS Inverter VTC 2.5 2 NMOS off PMOS res NMOS sat PMOS res V out (V) 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 V in (V) NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off
CMOS Inverter: Switch Model of Dynamic ehavior V DD V DD R p V out V out C L R n C L V in = 0 V in = V DD Gate response time is determined by the time to charge C L through R p (discharge C L through R n )
Relative Transistor Sizing When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to maximize the noise margins and obtain symmetrical characteristics
Noise Margins Determining V IH and V IL 3 y definition, V IH and V IL are where dv out /dv in = -1 (= gain) V OH = V DD 2 1 V M NM H = V DD - V IH NM L = V IL - GND pproximating: V IH = V M - V M /g V IL = V M + (V DD - V M )/g V OL = GND 0 VIL V in piece-wise linear approximation of VTC VIH So high gain in the transition region is very desirable
2.5 CMOS Inverter VTC from Simulation 0.25um, (W/L) p /(W/L) n = 3.4 (W/L) n = 1.5 (min size) V DD = 2.5V V out (V) 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 V in (V) V M 1.25V, g = -27.5 V IL = 1.2V, V IH = 1.3V NM L = NM H = 1.2 (actual values are V IL = 1.03V, V IH = 1.45V NM L = 1.03V & NM H = 1.05V) low- Output resistance output = 2.4kΩ high-output = 3.3kΩ
Impact of Process Variation on VTC 2.5 Curve 2 Good PMOS ad NMOS V out (V) 1.5 1 0.5 ad PMOS Good NMOS Nominal 0 0 0.5 1 1.5 2 2.5 V in (V) Process variations (mostly) cause a shift in the switching threshold
Scaling the Supply Voltage V out (V) 2.5 2 1.5 1 V out (V) 0.2 0.15 0.1 0.5 0 0.05 0 0.5 1 1.5 2 2.5 V in (V) Gain=-1 0 0 0.05 0.1 0.15 0.2 V in (V) Device threshold voltages are kept (virtually) constant Device threshold voltages are kept (virtually) constant
CSE497/597 Pass Transistor Logic
NMOS Transistors in Series/Parallel Primary inputs drive both gate and source/drain terminals NMOS switch closes when the gate input is high X X Remember - NMOS transistors pass a strong 0 but a weak 1 Y Y X = Y if and X = Y if or
PMOS Transistors in Series/Parallel Primary inputs drive both gate and source/drain terminals PMOS switch closes when the gate input is low X Y X = Y if and = + X Remember - PMOS transistors pass a strong 1 but a weak 0 Y X = Y if or =
0 Pass Transistor (PT) Logic F = 0 F = Gate is static a low-impedance path exists to both supply rails under all circumstances N transistors instead of 2N No static power consumption Ratioless idirectional (versus undirectional)
VTC of PT ND Gate 1.5/0.25 2 0 0.5/0.25 0.5/0.25 0.5/0.25 F = V out, V 1 0 =V DD, =0 V DD =V DD, =0 V DD ==0 V DD 0 1 2 Pure PT logic is not regenerative - the signal gradually degrades after passing through a number of PTs (can fix with static CMOS inverter insertion)
Differential PT Logic (CPL) PT Network F F Inverse PT Network F F F= F=+ F= ND/NND F= OR/NOR F=+ XOR/XNOR F=
CPL Properties Differential so complementary data inputs and outputs are always available (so don t need extra inverters) Still static, since the output defining nodes are always tied to V DD or GND through a low resistance path Design is modular; all gates use the same topology, only the inputs are permuted. Simple XOR makes it attractive for structures like adders Fast (assuming number of transistors in series is small) dditional routing overhead for complementary signals Still have static power dissipation problems
CPL Full dder C in C in!sum Sum C in C in!c out C in C out C in
NMOS Only PT Driving an Inverter In = V DD V x = V DD - V GS = V V DD Tn D S M 2 M 1 V x does not pull up to V DD, but V DD V Tn Threshold voltage drop causes static power consumption (M 2 may be weakly conducting forming a path from V DD to GND) Notice V Tn increases of pass transistor due to body effect (V S )
Voltage Swing of PT Driving an Inverter 3 In V DD In = 0 V DD D 0.5/0.25 S x 1.5/0.25 0.5/0.25 Out Voltage, V 2 1 x = 1.8V Out 0 0 0.5 1 1.5 2 Time, ns ody effect large V S at x - when pulling high ( is tied to GND and S charged up close to V DD ) So the voltage drop is even worse V x = V DD - (V Tn0 + γ( ( 2φ f + V x ) - 2φ f ))
Cascaded NMOS Only PTs = V DD = V DD M 1 C = V DD G S M 2 x = V DD - V Tn1 G S y = V DD Out = V DD M 1 x C = V DD M 2 y Out Swing on y = V DD - V Tn1 - V Tn2 Swing on y = V DD - V Tn1 Pass transistor gates should never be cascaded as on the left Logic on the right suffers from static power dissipation and reduced noise margins
Solution 1: Level Restorer Level Restorer =1 M 2 Out=0 =0 M n M r on off x = 0 1 M 1 Out =1 Full swing on x (due to Level Restorer) so no static power consumption by inverter No static backward current path through Level Restorer and PT since Restorer is only active when is high For correct operation M r must be sized correctly (ratioed)
3 Transient Level Restorer Circuit W/L n =0.50/0.25 Response W/L 2 =1.50/0.25 W/L 1 =0.50/0.25 2 W/L r =1.75/0.25 node x never goes below V M of inverter so output never switches Voltage, V 1 W/L r =1.50/0.25 0 W/L r =1.0/0.25 0 100 200 300 400 500 Time, ps W/L r =1.25/0.25 Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases t r (but decreases t f )
Solution Technology solution: 2: Multiple Use (near) zero V T VTransistors T devices for the NMOS PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to V DD ) low V T transistors In 2 = 0V = 2.5V on Out In 1 = 2.5V sneak path = 0V off but leaking Impacts static power consumption due to subthreshold currents flowing through the PTs (even if V GS is below V T )
Solution 3: Transmission Gates (TGs) Most widely used solution C C C C C = GND C = GND = V DD = GND C = V DD C = V DD Full swing bidirectional switch controlled by the gate signal C, = if C = 1
Resistance of TG 30 25 R n W/L p =0.50/0.25 0V R p 20 2.5V V out Resistance, kω 15 10 5 R p 2.5V R eq W/L n =0.50/0.25 R n 0 0 1 2
S TG Multiplexer V DD S S F In 2 S F In 1 S F =!(In 1 S + In 2 S) GND In 1 S S In 2
Transmission Gate XOR weak 0 if! 0 1 off on off on!! weak 1 if an inverter
TG Full dder C in Sum C out
Differential TG Logic (DPL) GND F= F= GND V DD F= F= V DD ND/NND XOR/XNOR