The MC14175B quad type D flip flop is cotructed with MOS P channel and N channel enhancement mode devices in a single monolithic structure. Each of the four flip flops is positive edge triggered by a common clock input (C). An active low reset input (R) asynchronously resets all flip flops. Each flip flop has independent Data (D) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flip flops for counter and toggle applicatio. Complementary Outputs Static Operation All Inputs and Outputs Buffered Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Output Compatible with Two Low Power TTL Loads or One Low Power Schottky TTL Load Functional Equivalent to TTL 74175 MAXIMUM RATINGS (Voltages Referenced to V SS ) (Note 2.) Symbol Parameter Value Unit V DD DC Supply Voltage Range 0.5 to +18.0 V V in, V out Input or Output Voltage Range (DC or Traient) 0.5 to V DD + 0.5 V I in, I out P D Input or Output Current (DC or Traient) per Pin Power Dissipation, per Package (Note 3.) ±10 ma 500 mw T A Ambient Temperature Range 55 to +125 C T stg Storage Temperature Range 65 to +150 C T L Lead Temperature (8 Second Soldering) 260 C 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/c From 65C To 125C This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be cotrained to the range V SS (V in or V out ) V DD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either V SS or V DD ). Unused outputs must be left open. A WL, L YY, Y WW, W PDIP 16 P SUFFIX CASE 648 SOIC 16 D SUFFIX CASE 751B SOEIAJ 16 F SUFFIX CASE 966 = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION MARKING DIAGRAMS Device Package Shipping MC14175BCP PDIP 16 2000/Box MC14175BD SOIC 16 48/Rail MC14175BDR2 SOIC 16 2500/Tape & Reel 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. 16 1 16 1 16 1 MC14175BCP AWLYYWW 14175B AWLYWW MC14175B ALYW MC14175BF SOEIAJ 16 See Note 1. MC14175BFEL SOEIAJ 16 See Note 1. Semiconductor Components Industries, LLC, 2000 August, 2000 Rev. 4 1 Publication Order Number: MC14175B/D
PIN ASSIGNMENT BLOCK DIAGRAM TRUTH TABLE Inputs Outputs Clock Data Reset Q Q 0 1 0 1 1 1 1 0 X 1 Q Q X X 0 0 1 X = Don t Care No Change 2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V SS ) ÎÎ 55C 25C ÎÎ 125C V DD Î Characteristic Î Symbol Vdc Min MaxÎ Min Typ (4.) Î Max Min Max Unit Î Output Voltage 0 Level Î V OL 5.0 0.05Î 0 Î 0.05 0.05 Vdc V Î in = V DD or 0 10 0.05 0 0.05 0.05 15 0.05 0 0.05 0.05 Î 1 Level V OH ÎÎ 5.0 Î V in = 0 or V DD 10 4.95 9.95 4.95 Î 9.95 5.0 4.95 10 Î 9.95 Vdc 15 14.95 14.95 15 14.95 Input Voltage 0 Level V Î (V O = 4.5 or 0.5 Vdc) Î IL Vdc 5.0 Î (V O = 9.0 or 1.0 Vdc) 10 1.5 3.0Î 2.25 1.5 4.50Î 3.0 1.5 3.0 (V O = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0 1 Level V Î (V O = 0.5 or 4.5 Vdc) Î IH Vdc 5.0 Î (V O = 1.0 or 9.0 Vdc) 10 3.5 7.0 3.5 Î 7.0 2.75 3.5 5.50Î 7.0 (V O = 1.5 or 13.5 Vdc) 15 11 11 8.25 11 Output Drive Current I Î (V OH = 2.5 Vdc) Source Î OH madc 5.0 3.0 Î 2.4 4.2Î 1.7 Î (V OH = 4.6 Vdc) 5.0 0.64 Î 0.51 0.88Î 0.36 (V Î OH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9 (V OH = 13.5 Vdc) 15 4.2 Î 3.4 8.8Î 2.4 Î (V OL = 0.4 Vdc) Sink Î I OL 5.0 Î (V OL = 0.5 Vdc) 10 0.64 1.6 0.51 Î 1.3 0.88 0.36 2.25Î 0.9 madc (V OL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4 ÎÎ Î Input Current I in 15 ± 0.1 ±0.00001 ± 0.1 ± 1.0 µadc Input Capacitance C Î (V in = 0) Î in Î Î 5.0Î 7.5 Î pf Î Quiescent Current Î I DD 5.0 Î (Per Package) 10 5.0 0.005Î 5.0 10Î 0.010Î 150 300 µadc 15 20 0.015 20 600 Total Supply Current (5.) (6.) I Î (Dynamic plus Quiescent, Î T 5.0 I 10 ÎÎ T = (1.7 µa/khz) f + I DD µadc I T = (3.4 µa/khz) f + I DD Per Package) 15 I Î (C L Î T = (5.0 µa/khz) f + I DD = 50 pf on all outputs, all Î buffers switching) 4. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 5. The formulas given are for the typical characteristics only at 25C. 6. To calculate total supply current at loads other than 50 pf: I T (C L ) = I T (50 pf) + (C L 50) Vfk where: I T is in µa (per package), C L in pf, V = (V DD V SS ) in volts, f in khz is input frequency, and k = 0.004. 3
SWITCHING CHARACTERISTICS (7.) (C L = 50 pf, T A = 25C) Î V Î All Types DD Characteristic ÎÎ Symbol Î Vdc Î Min Î Typ (8.) Î Max Unit Output Rise and Fall Time t t TLH, t THL = (1.35 /pf) C L ÎÎ TLH, t THL Î Î Î + 32 5.0 100 200 t TLH, t THL = (0.6 /pf) C L + 20 ÎÎ 10 Î Î 50 Î 100 t TLH, t THL = (0.4 /pf) C L + 20 15 40 80 Propagation Delay Time Clock to Q, Q t t PLH, t PHL = (0.9 /pf) C L + 175 ÎÎ PLH, t PHL Î 5.0 Î Î 220 Î 400 t PLH, t PHL = (0.36 /pf) C L + 72 ÎÎ 10 Î Î 90 Î 160 t PLH, t PHL = (0.26 /pf) C L + 57 15 70 120 Î Propagation Delay Time Reset to Q, Q t PHL, t PLH Î Î Î t PHL = (0.9 /pf) C L + 280 ÎÎ 5.0 Î Î 325 Î 500 t PHL = (0.36 /pf) C L + 112 10 130 200 t PHL = (0.26 /pf) C L + 87 ÎÎ 15 Î Î 100 Î 150 Clock Pulse Width ÎÎ t WH Î 5.0 Î 250 Î 110 Î Î 10 Î 100 Î 45 Î 15 75 35 Î Reset Pulse Width t WL Î Î Î 5.0 200 100 Î 10 Î 80 Î 40 Î 15 60 30 Clock Pulse Frequency f Î cl 5.0 4.5 2.0 mhz Î 10 Î Î 11 Î 5.0 Î 15 Î Î 14 Î 6.5 Clock Pulse Rise and Fall Time t Î TLH, t THL 5.0 15 s Î Î Î 10 5.0 Î 15 Î Î Î 4.0 Data Setup Time ÎÎ t su Î 5.0 Î 120 Î 60 Î 10 50 25 Î 15 Î 40 Î 20 Î Data Hold Time ÎÎ t h Î 5.0 Î 80 Î 40 Î 10 40 20 15 30 15 Reset Removal Time ÎÎ t rem Î 5.0 Î 250 Î 125 Î Î 10 Î 100 Î 50 Î 7. The formulas given are for the typical characteristics only at 25C. 8. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance. 15 80 40 4
TIMING DIAGRAM FUNCTIONAL BLOCK DIAGRAM 5
PACKAGE DIMENSIONS H A G B F C S K D 16 PL PDIP 16 P SUFFIX PLASTIC DIP PACKAGE CASE 648 08 ISSUE R T J L M T G A D 16 PL K B C SOIC 16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B 05 ISSUE J P 8 PL M R X 45 J F 6
PACKAGE DIMENSIONS e Z D b E A H E A 1 SOEIAJ 16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966 01 ISSUE O VIEW P M L E Q 1 L DETAIL P c 7
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