CprE 281: Digital Logic

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CprE 281: Digital Logic

CprE 281: Digital Logic

CprE 281: Digital Logic

CprE 281: Digital Logic

CprE 281: Digital Logic

CprE 281: Digital Logic

CprE 281: Digital Logic

CprE 281: Digital Logic

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CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/

Design Examples CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev

Administrative Stuff HW3 is out It is due on Monday Sep 11 @ 4pm. Please write clearly on the first page (in BLOCK CAPITAL letters) the following three things: Your First and Last Name Your Student ID Number Your Lab Section Letter Also, please Staple your pages

Administrative Stuff TA Office Hours: 5:00 pm - 6:00 pm on Tuesdays (Vahid Sanei-Mehri) Location: 3125 Coover Hall 11:10 am-1:10 pm on Wednesdays (Siyuan Lu) Location: TLA (Coover Hall - first floor) 5:00 pm - 6:00 pm on Thursdays (Vahid Sanei-Mehri) Location: 3125 Coover Hall 10:00 am-12:00 pm on Fridays (Krishna Teja) Location: 3214 Coover Hall

Administrative Stuff Homework Solutions will be posted on BlackBoard

Quick Review

The Three Basic Logic Gates x x x 2 x + 2 NOT gate AND gate OR gate You can build any circuit using only these three gates [ Figure 2.8 from the textbook ]

(a) Dual-inline package V DD Gnd (b) Structure of 7404 chip Figure B.21. A 7400-series chip.

V DD 7404 7408 7432 x 3 Figure B.22. An implementation of f = + x 3. f

NAND Gate f 0 0 1 0 1 1 1 0 1 1 1 0

NOR Gate f 0 0 1 0 1 0 1 0 0 1 1 0

Why do we need two more gates? They can be implemented with fewer transistors. (more about this later)

Building a NOT Gate with NAND x x x x x 0 1 x 1 0 x x f 0 0 1 0 1 1 1 0 1 1 1 0 impossible combinations Thus, the two truth tables are equal!

Building an AND gate with NAND gates [http://en.wikipedia.org/wiki/nand_logic]

Building an OR gate with NAND gates [http://en.wikipedia.org/wiki/nand_logic]

Implications Any Boolean function can be implemented with only NAND gates!

Implications Any Boolean function can be implemented with only NAND gates! The same is also true for NOR gates!

NAND-NAND Implementation of Sum-of-Products Expressions

Sum-Of-Products x 3 x 4 x 5 x 3 x 4 x 5 This circuit uses ANDs & OR x 3 x 4 x 5 [ Figure 2.27 from the textbook ] This circuit uses only NANDs

NAND followed by NOT = AND f 0 0 1 0 1 1 1 0 1 1 1 0 f 0 0 0 1 f 0 0 0 0 1 0 1 0 0 1 1 1

DeMorgan s Theorem

DeMorgan s Theorem x y x y = x y x y x + y

Sum-Of-Products x 3 x 4

Sum-Of-Products x 3 x 4 x 2 x 2 + x x 3 4 x 3 x 4 x x 3 4 x x 3 4

Sum-Of-Products AND OR x 3 x 4 AND x 2 x 2 + x x 3 4 x 3 x 4 x x 3 4 x x 3 4

Sum-Of-Products AND OR x 3 x 4 AND AND x 2 x 2 + OR x x 3 4 x 3 x x 3 4 x x 3 4 x 4 AND

Sum-Of-Products AND OR x 3 x 4 AND x 2 x 2 + x x 3 4 x 3 x 4 x x 3 4 x x 3 4

Sum-Of-Products AND OR x 3 x 4 AND x 2 x 2 NAND + x x 3 4 x 3 x x 3 4 x x 3 4 x 4

Sum-Of-Products AND OR x 3 x 4 AND x 2 + x x 3 4 x 3 x x 3 4 x 4

Sum-Of-Products AND OR x 3 x 4 AND NAND x 2 + NAND x x 3 4 x 3 x x 3 4 x 4 NAND This circuit uses only NANDs

Sum-Of-Products x 3 x 4 x 2 + x x 3 4 x 3 x x 3 4 x 4 This circuit uses only NANDs

NOR-NOR Implementation of Product-of-Sums Expressions

Product-Of-Sums x 3 x 4 x 5 x 3 x 4 x 5 This circuit uses ORs & AND x 3 x 4 x 5 This circuit uses only NORs [ Figure 2.28 from the textbook ]

NOR followed by NOT = OR + + + f 0 0 1 0 1 0 1 0 0 1 1 0 f 0 1 1 1 f 0 0 0 0 1 1 1 0 1 1 1 1

DeMorgan s Theorem

DeMorgan s Theorem x y x + y = x y x y x y

Product-Of-Sums x 3 x 4

Product-Of-Sums x 3 x 4 x + 2 x + 2 ( + ) (x 3 + x 4 ) x 3 x 4 x x 3 + 4 x x 3 + 4

Product-Of-Sums OR AND x 3 x 4 OR x + 2 x + 2 ( + ) (x 3 + x 4 ) x 3 x 4 x x 3 + 4 x x 3 + 4

Product-Of-Sums OR AND x 3 x 4 OR OR x + 2 x + 2 AND ( + ) (x 3 + x 4 ) x 3 x x 3 + 4 x x 3 + 4 x 4 OR

Product-Of-Sums OR AND x 3 x 4 OR x + 2 x + 2 ( + ) (x 3 + x 4 ) x 3 x 4 x x 3 + 4 x x 3 + 4

Product-Of-Sums OR AND x 3 x 4 OR x + 2 x + 2 NOR ( + ) (x 3 + x 4 ) x 3 x x 3 + 4 x x 3 + 4 x 4

Product-Of-Sums OR AND x 3 x 4 OR x + 2 ( + ) (x 3 + x 4 ) x 3 x x 3 + 4 x 4

Product-Of-Sums OR AND x 3 x 4 OR NOR x + 2 NOR ( + ) (x 3 + x 4 ) x 3 x x 3 + 4 x 4 NOR This circuit uses only NORs

Product-Of-Sums AND x 3 x 4 x + 2 ( + ) (x 3 + x 4 ) x 3 x x 3 + 4 x 4 This circuit uses only NORs

Another Synthesis Example

Truth table for a three-way light control [ Figure 2.31 from the textbook ]

Minterms and Maxterms (with three variables) [ Figure 2.22 from the textbook ]

Let s Derive the SOP form

Let s Derive the SOP form

Sum-of-products realization f x 3 [ Figure 2.32a from the textbook ]

Let s Derive the POS form [ Figure 2.31 from the textbook ]

Let s Derive the POS form

Product-of-sums realization x 3 f [ Figure 2.32b from the textbook ]

Multiplexers

2-1 Multiplexer (Definition) Has two inputs: and Also has another input line s If s=0, then the output is equal to If s=1, then the output is equal to

Graphical Symbol for a 2-1 Multiplexer s 0 1 f [ Figure 2.33c from the textbook ]

Analogy: Railroad Switch http://en.wikipedia.org/wiki/railroad_switch]

Analogy: Railroad Switch select f http://en.wikipedia.org/wiki/railroad_switch]

Analogy: Railroad Switch select f This is not a perfect analogy because the trains can go in either direction, while the multiplexer would only allow them to go from top to bottom. http://en.wikipedia.org/wiki/railroad_switch]

Truth Table for a 2-1 Multiplexer [ Figure 2.33a from the textbook ]

Let s Derive the SOP form

Let s Derive the SOP form

Let s Derive the SOP form Where should we put the negation signs? s s s s

Let s Derive the SOP form s s s s

Let s Derive the SOP form s s s s f (s,, ) = s + s + s + s

Let s simplify this expression f (s,, ) = s + s + s + s

Let s simplify this expression f (s,, ) = s + s + s + s f (s,, ) = s ( + ) + s ( + )

Let s simplify this expression f (s,, ) = s + s + s + s f (s,, ) = s ( + ) + s ( + ) f (s,, ) = s + s

Circuit for 2-1 Multiplexer s s f 0 1 f (b) Circuit (c) Graphical symbol f (s,, ) = s + s [ Figure 2.33b-c from the textbook ]

More Compact Truth-Table Representation s f (s,, ) 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 (a) Truth table s 0 1 f (s,, ) [ Figure 2.33 from the textbook ]

4-1 Multiplexer (Definition) Has four inputs: w 0, w 1, w 2, w 3 Also has two select lines: s 1 and s 0 If s 1 =0 and s 0 =0, then the output f is equal to w 0 If s 1 =0 and s 0 =1, then the output f is equal to w 1 If s 1 =1 and s 0 =0, then the output f is equal to w 2 If s 1 =1 and s 0 =1, then the output f is equal to w 3

4-1 Multiplexer (Definition) Has four inputs: w 0, w 1, w 2, w 3 Also has two select lines: s 1 and s 0 If s 1 =0 and s 0 =0, then the output f is equal to w 0 If s 1 =0 and s 0 =1, then the output f is equal to w 1 If s 1 =1 and s 0 =0, then the output f is equal to w 2 If s 1 =1 and s 0 =1, then the output f is equal to w 3 We ll talk more about this when we get to chapter 4, but here is a quick preview.

Graphical Symbol and Truth Table [ Figure 4.2a-b from the textbook ]

The long-form truth table

The long-form truth table [http://www.absoluteastronomy.com/topics/multiplexer]

The long-form truth table [http://www.absoluteastronomy.com/topics/multiplexer]

The long-form truth table [http://www.absoluteastronomy.com/topics/multiplexer]

The long-form truth table [http://www.absoluteastronomy.com/topics/multiplexer]

4-1 Multiplexer (SOP circuit) [ Figure 4.2c from the textbook ]

Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer s 1 s 0 w 0 w 1 0 1 0 1 f w 2 w 3 0 1 [ Figure 4.3 from the textbook ]

Analogy: Railroad Switches http://en.wikipedia.org/wiki/railroad_switch]

Analogy: Railroad Switches w 0 w 1 w 2 w 3 s 1 f http://en.wikipedia.org/wiki/railroad_switch]

Analogy: Railroad Switches w 0 w 1 w 2 w 3 s 0 these two switches are controlled together s 1 f http://en.wikipedia.org/wiki/railroad_switch]

Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer

Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer

Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer

Using three 2-to-1 multiplexers to build one 4-to-1 multiplexer w 0 s 1 s 0 w 1 w 2 f w 3

That is different from the SOP form of the 4-1 multiplexer shown below, which uses fewer gates

16-1 Multiplexer s 0 s 1 w 0 w 3 w 4 s 2 s 3 w 7 f w 8 w 11 w 12 w 15 [ Figure 4.4 from the textbook ]

[http://upload.wikimedia.org/wikipedia/commons/2/26/sunsettrackscrop.jpg]

Questions?

THE END