Sum-of-Generalized Products Epressions Applications and Minimization Tsutomu Sasao Department of Computer Science and Electronics Kyushu Institute of Technology Iizuka 80-850 Japan Abstract This paper defines the sum-of-generalized-products epression (SOGP a generalization of a sum-of-products epression (SOP which is suitable for FPGA implementation k -valued logic is introduced to design circuits with k-input LUTs Minimization methods for SOGPs are developed Eperimental results show that SOGPs require many fewer products than SOPs especially for symmetric functions and adders The method is promising for FPGA design Introduction Previous Approach Most logic synthesis systems use sum-of-products epressions (SOPs to represent logic functions When AND and OR gates are the basic logic elements SOPs are quite useful However for a field programmable gate array (FPGA basic logic elements are look-up tables (LUTs In such a case logic design using LUTs is desirable In the past several logic design methods using LUTs as basic elements have been developed One method is based on multi-valued decision diagrams where each node of a decision diagram is replaced by an LUT that implements multipleers or their etensions [8 9 ] Another method is based on binary decision diagrams (BDDs and uses LUTs to implement cascades [0] It is useful for functions whose BDDs are relatively small New Approach In this paper we consider a generalization of multi-valued SOPs that is suitable for FPGA implementations An SOP is realized by a two-level AND-OR circuit such as shown in Fig By replacing a set of inverters with multivalued literal generators we have a circuit that realizes a product with multi-valued literals shown in Fig By combining products by an OR gate we have a circuit that Figure : AND-OR two-level circuit =( =(5678 =(90 =(56 S S S S S S S S Figure : Product with multi-valued literals realizes a sum-of-products (SOP with multi-valued literals [] In Fig by replacing the AND gate with an LUT we have a circuit that realizes a generalized product (GP g(h ( h ( h ( h ( as shown in Fig The LUT for h i is a literal generator while the LUT for g is a GP generator By combining the generalized products with an OR gate we have a circuit that realizes a sum-ofgeneralized-products (SOGP as shown in Fig Realization of SOGP on an FPGA In this paper we use LUT type FPGAs Such an FPGA consists of many LUTs as well as block RAMs (BRAMs To illustrate the idea we assume that each FPGA has four inputs In this case we introduce 6-valued logic
=( =(5678 =(90 h h h S S S g LUT =(56 h S g g g g g 5 g 6 g 7 g 8 Figure : Generalized product h Figure : Realization of SOGP by LUTs h h g BRAM h h 5 h 6 g g g g g 5 g 6 g 7 g 8 g h 7 h 8 Figure : Sum-of-generalized-products to design -input LUT circuits A -input LUT realizes an arbitrary function of four variables Fig (a shows a map of a -variable function An arbitrary - variable logic function can be represented by a subset of 6 minterms {m 0 m m 5 } For eample the function in Fig (b can be represented by a set of four minterms {m m 6 m 9 m } Instead of using a set of minterms we can use a 6-valued literal Let =( Then the function in Fig (b can be represented by the literal {69} This literal specifies that the function is if and only if the input combination =( represents either 6 9 or In this case four variables are treated m 0 m m m 8 m m 5 m m 9 m m 7 m 5 m m m 6 m m 0 (a (b { 69 } Figure : Map for -variable Function Figure : Realization of SOGP by BRAMs together as =( and is considered as a 6- valued variable Thus Fig implements a product of 6-valued literals of the form S S S S where S i P and P = {05} Fig shows a realization of an SOGP by LUTs Note that each column realizes a generalized product having a form g i (h ( h ( h ( h ( Since each LUT has four inputs Fig implements a logic function with 6 binary inputs Fig shows a realization of an SOGP by BRAMs Note that FPGAs often have BRAMs that can be configured as memories with 7 to 9 inputs and 8 to 6 outputs In these figures the horizontal lines denote bundles of binary lines Each horizontal bundle denotes a multi-valued variable and each column realizes a generalized product of multi-valued literals When the BRAM has k inputs an SOGP with k -valued literals is realized When BRAMs (synchronous RAMs are used as logic elements a clock pulse is necessary We can formulate the optimization problem of an SOGP as follows: Problem Given a function f and a partition of the input variables ( r represent f ( r as _ g j (h j ( h j ( h rj ( r
using the minimum number of g k s Interesting questions include How to partition the variables? How to minimize the SOGP? How many GPs are necessary to represent a function by using an SOGP? When FPGAs with -input LUTs are used each variable i consists of binary variables SOP with Multi-Valued Literals Before showing the design method we present some definitions Optimization of SOPs with multi-valued variables is well known [6 5 9] Definition A mapping f : P n Bisap-valued input two-valued output function where P = {0p } and B = {0} Let be a variable that takes a value in P = {0p } Let S be a subset (S P of P Then S is a literal of When S S = and when / S S = 0 Let S i P(i = n then S S S n n the AND of n literals is a logical product W (S S S n S S S n n is a sum-of-products epression (SOP When S i = P S i i = and the logical product is independent of i In this case literal P i is redundant and can be deleted A logical product is also called a product term When S i = for all i (i = n the product is a minterm When S i = P for all i the logical product corresponds to the constant When p = f is a twovalued logic function When we consider two-valued logic functions only we often represent the literal by and {} by An arbitrary multi-valued input two-valued output function is represented by an SOP Many SOPs eist that represent the same function Among them one with the minimum number of products is a minimum SOP MINI [] and ESPRESSO-MV [5] can minimize SOPs with multi-valued inputs Simplification of SOGPs In this part we consider a method to generate a simple SOGP for a given function The method first generates an SOP with multiple-valued literals Then we simplify it using the properties of SOGPs To show the method consider the following: Eample Consider an SOP of a function f : {0} {0} f = {0} {} {} {} By rewriting the second product we have f = {0} {} {} {0} {} Note that the latter epression requires only one kind of literal generator for each variable Let y = {0} y = {} and y = {} Then the given function can be represented as a single GP: f = y y y ȳ ȳ = g(y y y (End of Eample Definition A traditional implicant of a function f is a product term that implies f A generalized implicant is a function of the form g(h ( h ( h r ( r that implies f A non-traditional implicant is a generalized implicant that cannot be represented by a single product Note that in Eample {0} {} {} is a traditional implicant while g(y y y = {0} {} {} {0} {} is a non-traditional implicant Eample shows that two different prime implicants can be merged into one GP To find such pair of products we need the following: Definition Consider two products of a function: c = S S S r r and c = T T T r r where S i P i and T i P i Then c and c are compatible iff for all i (S i = T i or S i = P i or T i = P i or S i = T i Compatible implicants can be merged to a single generalized implicant Eample Consider the function f : {0} {0} In this case P = P = P = {0} Let f = {} {} {} {} {} {} Note that all the products are compatible each other since f can be written as follows: f = Thus f is represented by a single GP (End of Eample To represent a GP compactly we use the notion of a base product Definition Let g(h ( h ( h r ( r be a generalized product Then a base product is c 0 = S S S r r where h i ( i = S i i Eample Consider the function in Eample Let the base product be one where each literal contains the 0 element Then is the base product (End of Eample
0 0 (a 0 0 Figure : Map for -variable Function Lemma For a given function f and a base product c 0 there eists a unique GP Algorithm (Generation of the GP from a base product Let the base product be c 0 = S S S r r Let c = T T T r r be a product where none or some literals of c 0 are complemented Note that there are r different c s to consider The GP is obtained as the sum of all possible products c that does not intersect f Eample Consider the two-variable function f ( shown in Fig (a Let the base product be c 0 = Consider the products c = c = and c = Since c and c do not intersect f the GP generated by c 0 is c = = From the base product c 5 = {} {} we have the GP: c 6 = {} {} {} {} = {} {} From the base product c 7 = {} {} we have the GP: c 8 = {} {} {} {} = {} {} From the base product c 9 = {} {} we have the GP: c 0 = {} {} {} {} = {} {} From the base product c = {0} {0} we have the GP: c = {0} {0} {0} {0} = {0} {0} From the base product c = {0} {0} we have the GP: c = {0} {0} {0} {0} = {0} {0} From the base product c 5 = {0} {0} we have the GP: c 6 = {0} {0} {0} {0} = {0} {0} In this way we have 7 GPs for f (End of Eample A set of compatible products can be uniquely represented by a base product and f In an SOP of f a product of f corresponds to an implicant of f while in an SOGP a (b base product S S S r r may not be an implicant of f It shows that T T T r r is an implicant of f where T i = S i or S i From the set of prime implicants of a multiple-valued SOP we can generate a GP cover of the function However to obtain a minimum SOGP we need additional GPs The following eample illustrates this: Eample 5 Consider the -valued input -variable function: f = {0} {} {} {} {} {0} {0} {} {} {} {0} {} {} {0} {0} {0} This is the minimum SOP consisting of the essential prime implicants [9] only The following SOP consisting of prime and non-prime implicants also denotes the same function: f = {0} {} {} {} {} {} {0} {} {} {} {0} {} {} {0} {0} {0} Note that the st and nd products are compatible Similarly the rd and the th products are compatible Also the 5rd and 6th products are compatible From this we have the following SOGP consisting of only three GPs: f = ( {} {} {} {} {} ( {} {} {} ( {} {} {} {} {} {} In the first SOP the st and the nd products are not compatible So they cannot be merged However in the second SOP they are compatible and can be merged into one Thus to derive a minimum SOGP we have to consider non-prime implicants as well as prime implicants (End of Eample The above eample shows that the minimization of SOGPs is more complicated than that of SOPs Definition A prime generalized implicant (PGI of a function f is a generalized implicant of f that cannot be covered by other generalized implicant of f As for the number of PGIs we have the following: Theorem Consider a function f ( r of n variables where n = k r and each i consists of k variables Suppose that each literal generator has k binary inputs Then the number of distinct PGIs of the function f is at most r(k
Corollary Consider the cases of k = and The numbers of PGIs of an n-variable function is at most r = n when k = ( r = 8 n =(88 n when k = ( 7 r = 8 n =(50 n when k = ( 5 r = 768 n =(5 n when k = In the case of k = only one base product n is necessary to represent an n-variable function Note that the number of variables for g in Fig is n This corresponds to a single-memory realization of the logic function and is not interesting As for the number of products in an SOGP we have the following: Theorem An arbitrary function of n = kr variables can be represented by a k -valued SOP with at most n k products If we can find the set of all the PGIs then we can find an eact minimum SOGP in a similar way to the case of SOPs Unfortunately too many different PGIs eist for a function So generating all the PGIs is not practical in many cases With this observation we have developed two types of SOGP minimization algorithms Algorithm is similar to the Quine-McCluskey method and obtains good solutions but requires a large amount of memory Algorithm (GQM: Generation of a good SOGP Obtain the set of all the prime implicants of a multiplevalued SOP Merge the compatible products Find the set of base products For each base product generate the GP by Algorithm 5 Append additional GPs (Optional 6 Find a minimum cover of the minterms using GPs Eample 6 Consider the two-variable function with - valued input shown in Fig (a Represent it as an SOP with -valued inputs There eist prime implicants: {} {} ; {} {0} {0} {} ; {} {0} {0} {} ; {} {0} {0} {} ; {0} {} {} {0} ; {0} {} {} {0} ; {0} {} {} {0} A minimum SOP has consists of four products: f ( = {} {} {0} {} {0} {} {0} Represent it as an SOGP with -valued inputs Note that each pair of prime implicants separated by semicolons are compatible So they can be combined into 7 PGIs: {} {} = {} {0} {0} {} = {} {} {} {0} {0} {} = {} {} {} {0} {0} {} = {} {} {0} {} {} {0} = {0} {0} {0} {} {} {0} = {0} {0} {0} {} {} {0} = {0} {0} In this case the base products of them are: {} {} {} {} {} {} {0} {0} {0} {0} and {0} {0} The corresponding GPs are shown above A minimum SOGP consists of two products f ( =( {0} {0} ( {0} {0} Fig (b shows the map of the SOGP (End of Eample Algorithm is a heuristic one and requires less memory than Algorithm : It derives an SOGP quickly Algorithm (GMINI: A fast generation of an SOGP g f sol φ Obtain a near minimum multiple-valued SOP for g For each product c i in the SOP obtain the generalized implicant GI(c i by Algorithm Let vol(gi(c i be the number of minterms of g that is covered by GI(c i Find the GI(c i whose vol(gi(c i is the maimum 5 sol sol c i g g GI(c i DC DC GI(c i and go to Step 5 SOGPs for Symmetric Functions and Adders 5 Symmetric Functions Regarding symmetric functions we have the following: Theorem 5 Consider a function f ( r where i consists of k binary variables Let f ( r be partially symmetric with respect to i for i = r That is f is invariant under the permutation of variables in i Then f can be represented by an SOP with k -valued variables with at most (k + r products
Y Y Y Y Y 0 0 0 0 0 Y=0 Y= Y= Y= Figure 5: Map for -variable function Eample 5 Sym9 is the symmetric function S 9 {56} ( where =( =( 5 6 and =( 7 8 9 [7] The function is iff the weight of the input vector is 5 or 6 From Theorem 5 Sym9 can be represented by an SOGP with at most ( + = = 6 products since k = r = In fact the 8-valued SOGP requires only 6 GPs: f = {56} ( {0} {0} {56} ( {0} {0} {56} ( {0} {0} {56} {56} {56} ( {7} {7} {7} ( In the above epression the weight of {56} is either or ; the weight of {0} is either 0 or ; the weight of is 0; and the weight of {7} is The first three GPs in the above SOGP denote the combinations that the sums of the weights for and are ( or +(0 or + ( or The fourth GP denotes the combination that the sum of the weights is ( or +( or + ( or The last two GPs denote the combinations that the sums of the weighs are (0 +(+ (0 or or Note that a two-valued SOP for Sym9 requires 8 products (End of Eample Eample 5 Consider the function g(y Y Y shown in Fig 5 In this function the value of Y i denotes the number of one s of i in Sym9 in the previous eample So the number of PGIs for g is the same as the number of PGIs for Sym9 The minimum SOGP is f (Y Y Y =Y {} (Y {0} Y {0} Y {} (Y {0} Y {0} Y {} (Y {0} Y {0} Y {} Y {} Y {} Y {0} (Y {} Y {} Y {} (Y {0} Y {0} This also illustrates that Sym 9 can be represented by only 6 PGIs (End of Eample 5 Adders Regarding adders we have the following: Lemma 5 The i-th bit of an n-bit adder s i can be represented by a -valued input SOGP with i products where the least significant output bit is s 0 From the above Lemma we have the following: Theorem 5 An n-bit adder can be represented by a - valued input SOGP with n +n+ products Note that the numbers of products to implement n-bit adders where n = r are as follows [9 ]: -valued SOP : 6 n n 5 -valued SOP: n + 6-valued SOP : r r + 6 Eperimental Results We have developed two types of minimization programs GQM and GMINI and minimized SOGPs for standard PLA benchmarks [] as well as adders randomly generated functions and symmetric functions Benchmark Functions Table 6 shows the results IN denotes the number of inputs; OU denotes the number of outputs; SOP denotes the number of products in a sum-ofproducts epression; SOGP denotes the number of products in a sum-of-generalized products epression -valued denotes the number of products in a -valued epression; -valued denotes the number of products in a -valued epression; 6-valued denotes the number of products in a 6-valued epression P denotes the program used to obtain the result: Q denotes GQM while M denotes GMINI Algorithm 6 in [] was used to generate both -valued and 6-valued epressions In general -valued epressions require fewer products than -valued ones and 6-valued epressions require fewer products than -valued ones Note that the SOGP for the benchmark function t8 require only one product while the minimum -valued SOP requires 8 products Fig 6 shows the gate-level realization of t8 [] Randomly Generated Functions We generated random functions of n variables where the number of true minterms is n For eample 8 8 is an 8 input random function that has 8 = 8 true minterms In this case -valued SOGPs require fewer products than -valued SOPs However for 6-valued cases SOPs and SOGP require the same number of products Symmetric Functions Table 6 shows the number of products to represent symmetric functions These functions are defined in [9] In this case three bits are grouped to
Table 6: Number of products to represent benchmark functions IN OU -valued -valued 6-valued SOP SOP SOGP SOP SOGP P adr 8 5 75 7 8 7 Q adr6 7 55 7 7 Q adr8 6 9 99 65 7 0 5 M alu 8 577 5 8 56 5 Q alupla 5 5 008 56 9 8 M ape 9 9 M ape 9 9 7 8 8 M chkn 9 7 0 06 9 6 59 M cordic 9 67 0 5 0 M e00 0 0 56 5 50 5 M intb 5 7 69 9 85 00 76 M mise 658 6 87 8 Q mlp 8 8 9 8 68 7 7 Q mlp5 0 0 86 5 8 6 Q mlp6 877 9 8 55 58 Q rdm6 6 6 0 8 9 0 9 M t8 6 8 5 Q tial 6 575 80 09 95 69 Q 8 8 8 6 8 Q 08 57 9 7 Q Table 6: Number of products to represent symmetric functions In Out -valued 8-valued SOP SOP SOGP P sym6 6 5 Q sym9 9 8 0 6 Q sym 95 0 Q sym5 5 00 0 0 Q sym8 8 867 6 5 M wgt9 9 5 5 7 Q wgt 095 5 0 Q wgt5 5 767 50 9 Q Table 6: Number of LUTs and depth to implement functions In Out IMap SOGP LUT depth LUT depth alu 8 05 8 09 6 e00 0 0 5 9 56 7 mise 086 8 7 6 redundant inputs of the OR gates are also implemented Thus it may not be a fair comparison For the mapping of SOGP we used ilin Spartan III(SCS000F and a ilin tool 5 6 7 8 9 0 5 6 Figure 6: Gate-level realization of t8 derive 8-valued variables In the case of symmetric functions 8-valued SOGPs required many fewer products than 8-valued SOPs Comparison with Other FPGA Synthesis System To show the potential of the approach we compared the number of LUTs and depth with IMap[] Table 6 compares the number of -input LUTs for IMap and SOGP-base synthesis tool Note that IMap shows a result for a particular function while the SOGP shows a result for a programmable circuits that implements a given function (ie 7 Conclusion and Comments In this paper we defined an SOGP a generalization of an SOP An SOGP can be efficiently realized by a network of LUTs We also showed methods to simplify SOGPs Eperimental results show that SOGPs require many fewer products than corresponding SOPs especially for symmetric functions and adders Note that an SOGP corresponds to a three-level network ie literal generators GP generators and the OR gate In this case the literal generators and GP generators are implemented by LUTs A more general problem is to realize a logic function by a three-level network of LUTs Scalability Let n = k r be the number of the inputs k be the number of inputs for LUTs for literal generators and r be the number of inputs for GP generators When the maimal number of inputs for an LUT in an FPGA is 6 the functions with at most 6 inputs are directly implemented by an SOGP For the functions with more inputs GP generators can be realized by a trees of LUTs instead of the r-input LUTs In this case we have to modify the algorithm Even in such a case the number of products does not eceeds that of the SOP since the architecture implements an SOP as a special
case A function whose SOP has a reasonable size can be implemented by our method Applications Since the circuit has a regular structure an SOGP is suitable for a programmable device Since the interconnections are fied dynamic reconfiguration is easy For functions with many inputs LUTs with more inputs (5 or 6 or BRAMs with more inputs can be used [] We are currently improving an algorithm to group the input variables as well as a mapping system for FPGAs [] T Sasao An application of 6-valued logic to design of reconfigurable logic arrays ISMVL-007 Oslo Norway May -6 007 (to be published [] S Yang Logic Synthesis and Optimization Benchmark User Guide Version 0 MCNC Jan 99 [] S S Yau and C K Tang Universal logic modules and their applications IEEE Trans Computers Vol C-0 pp -9 970 Acknowledgments This research is supported in part by the Grants in Aid for Scientific Research of JSPS Discussion with Prof Jon T Butler improved English presentation Mr Hiroki Nakahara worked for FPGA implementation References [] R K Brayton G D Hachtel C T McMullen and A L Sangiovanni-Vincentelli Logic Minimization Algorithms for VLSI Synthesis Boston MA Kluwer 98 [] S J Hong R G Cain and D L Ostapko MINI: A heuristic approach for logic minimization IBM J Res & Develop pp -58 Sept 97 [] V Manohararajah S D Brown and Z G Vranesic Heuristic for area minimization in LUT-based FPGA technology mapping International Workshop on Logic and Synthesis (IWLS0 Temecula CA June - 00 pp - [] A Mishchenko and T Sasao Large-scale SOP minimization using decomposition and functional properties 0th Design Automation Conference Ahaneim CA USA June -6 00 pp 9-5 [5] R L Rudell and A Sangiovanni-Vincentelli Multiplevalued minimization for PLA optimization IEEE Trans CAD Vol 6(5 pp 77-750 Sep 987 [6] T Sasao Input variable assignment and output phase optimization of PLA s IEEE Trans Comput Vol C- No 0 pp 879-89 Oct 98 [7] T Sasao (ed Logic Synthesis and Optimization Kluwer Academic Publishers 99 [8] T Sasao and J T Butler A design method for look-up table type FPGA by pseudo-kronecker epansion ISMVL-99 Boston MA USA May 99 pp 97-06 [9] T Sasao Switching Theory for Logic Synthesis Kluwer Academic Publishers 999 [0] T Sasao M Matsuura and Y Iguchi A cascade realization of multiple-output function for reconfigurable hardware International Workshop on Logic and Synthesis (IWLS0 Lake Tahoe CA June -5 00 pp 5-0