EE66: Solid State Devices Lecture 24 MOSFET non-idealities Gerhard Klimeck gekco@purdue.edu Outline ) Flat band voltage - What is it and how to measure it? 2) Threshold voltage shift due to trapped charges 3) Physics of interface traps 4) onclusion Ref: Sec. 6.4 of SDF hapter 8, SDF 2
Outline ) Flat band voltage - What is it and how to measure it? 2) Threshold voltage shift due to trapped charges 3) Physics of interface traps 4) onclusion Ref: Sec. 6.4 of SDF hapter 8, SDF I α ( = ) ~ ( ) D D DD G th < α < 2 th γ MQM QF QIT ( φs ) = th, ideal + φms O O O 3 () Idealized MOS apacitor In the idealized MOS capacitor, the Fermi Levels in metal and semiconductor align perfectly so that at zero applied bias, the energy bands are flat acuum level y Substrate (p) χ i χ s Φ m Recall that Q = ( ) i G th, ideal E F th, ideal Q = ψ s B ψ s =2 φ F metal insulator p semiconductor 4
Potential, Field, harges χ i χ s Φ m E bi = ρ No built in potential, fields or charges at zero applied bias in the idealized MOS structure 5 Real MOS apacitor with Φ M < Φ S E A Note the difference Φ M = qφ m χ S Φ S qψ S > E F E F E E In reality, the metal and semiconductor Fermi Levels are never aligned perfectly when you bring them together there is charge transfer from the bulk of the semiconductor to the surface so that we have alignment Do we need to apply less or more G to invert the channel? 6
G = Physical Interpretation of Flatband oltage The Flatband oltage is the voltage applied to the gate that gives zero-band bending in the MOS structure. Applying this voltage nullifies the effect of the built-in potential. This voltage needs to be incorporated into the idealized MOS analysis while calculating threshold voltage = φ = < FB ms bi E F G = FB < E E F E bi = φ ms > + ψ S = flat band 7 How to alculate Built-in or Flat-band oltage The presence of a flatband voltage lowers or raises the threshold voltage of a MOS structure. Engineering question Is it desirable to have a metal having a work function greater or less than the electron affinity+(ec-ef) in the semiconductor? q = q ( χs E ) = + Φ bi g p FB φ MS M q bi acuum level χ s Therefore, Q = ( ) i G th Φ m E F E th Q B = 2φ F FB 8
Measure of Flat-band shift from - haracteristics The transition point between accumulation and depletion in a non-ideal MOS structure is shifted to the left when the metal work function is smaller that the electron affinity +(Ec-Ef). At zero applied bias the semiconductor is already depleted so that a very small positive bias inverts the channel. The flatband voltage is the amount of voltage required to shift the curve such that the transition point is at zero bias. / Ideal th Actual G th 9 Outline ) Flat band voltage - What is it and how to measure it? 2) Threshold voltage shift due to trapped charges 3) Physics of interface traps 4) onclusion Ref: Sec. 6.4 of SDF hapter 8, SDF γ Q Q Q ( φ ) = + φ M M F IT s th th, ideal MS
(2) Idealized MOS apacitor acuum level y Substrate (p) χ i χ s Φ m Recall that Q = ( ) i G th, ideal Q = E F E th, ideal Q = ψ s B ψ s =2 φ F metal insulator p semiconductor Distributed Trapped charge in the Oide O X O QM = ρ( ) In the absence of charges in the ide, the field is constant (d/d = constant). The presence E of a charge distribution inside F the ide changes the field inside the ide and effectively traps field lines comping from the gate. As a result, depending on E the ρ polarity of charges in the ie, the threshold voltage Mis modified. γ M = ρ d ( ) d ( ) d th QF = ψ S γ M Q M m represents the centroid of the charge distribution one can think of this as replacing the entire distribution with a delta charge at this point 2
An Intuitive iew Reduced gate charge Ideal charge-free ide Bulk charge -E -E Interface charge -E 3 Gate oltage and Oide harge G = +ψ s Kirchoff s Law balancing voltages 2 d de ρ( ) = = 2 d d κ ε E ( ) E ( ) de = d d =E ( ) E ( ) =E ( ) ρ ( ')d ' κ ε ρ( ') d' κ ε Known from boundary conditions in semiconductor and continuity of E = κ S κ E S ( ) = κ S κ E S ( ) ρ d ( ')d ' κ ε ρ ( )d κ ε -E 4
Gate oltage and Oide harge S ( ) = κ ρ E S ( ) κ o κε = ψ ( = 2 φ ) + th s F κ S = ψ s = φf ) + E S ( ρ κ κ S = E S κ ( 2 ) ( ) d d ( ) ρ ( ) d = th, ideal ( ) d Q = th, ideal ρo M γ M 5 Interpretation for Bulk harge / th = th, ideal ρ( ) δ ( ) d = th, ideal o QM ( ) o New T Ideal T G 6
Interpretation for Interface harge / * th = th ρ( ) δ ( o ) d o * Q = th F o New T Ideal T G 7 Time-dependent shift of Trapped harge / E = Q ( ) δ ( ( t)) d th th, ideal ( t) Q ( ) = th, ideal Ideal T G Sodium related bias temperature instability (BTI) issue 8
Bias Temperature Instability (Eperiment) M O S - --- - + + + (-) biases + M O S + (+) biases + + - ρ ion ρ ion. o o.9 o o 9 Outline ) Flat band voltage - What is it and how to measure it? 2) Threshold voltage shift due to trapped charges 3) Physics of interface traps 4) onclusion Ref: Sec. 6.4 of SDF hapter 8, SDF γ Q Q = + φ th th, ideal MS M M F QIT ( φs ) 2
SiO and SiH Bonds No long-range order Local ordering tetrahedra 2 Interface States With annealing technology Unpassivated bonds ~ cm -2 Unpassivated bonds ~ 4 22 cm -2
Forming gas anneal Annealing of Interface States surface data BUT: surface has /3 less dangling bonds H H H Good MOSFET requires about /cm 2 23 - Stretch Out Forming gas anneal H H H Good MOSFET requires about /cm 2 24
Nature of Donor and Acceptor Traps Donor level Positive when empty Neutral when full Acceptor level Neutral when empty Negative when full ombination when both are present Now the surprising part: Hydrogen passivation can act as a donor and as an acceptor leve Depends on details of bond configuration 25 Donor like Interface States * th = th α( G ) δ o * α ( G ) Q ( ) Q ( ) ( ) d = th α ( G ) = < α ( ) < α( G ) ~ G / G Assume the charges would NOT be voltage dependent => solid shift BUT: charges change with voltage => smooth shift 26
Acceptor like Interface States α ( G ) = < α ( ) < α( G ) ~ G - - / α ( ) Q ( ) ( ) = + * G th G th G 27 Acceptor and Donor Traps ombined Donor-related stretchout Acceptor-related stretchout / G 28 2
Summary ) Non-ideal threshold characteristics are important consideration of MOSFET design. 2) The non-idealities arise from differences in gate and substrate work function, trapped charges, interface states. 3) Although nonindeal effects often arise from transistor degradation, there are many cases where these effects can be used to enhance desirable characteristics. 29