Tunnel-FET: bridging the gap between prediction and experiment through calibration

Tunnel-FET: bridging the gap between prediction and experiment through calibration Anne Verhulst Quentin Smets, Jasper Bizindavyi, Mazhar Mohammed, Devin Verreck, Salim El Kazzi, Alireza Alian, Yves Mols, Dennis Lin, Bart Sorée, Nadine Collaert, Guido Groeseneken and Marc Heyns 10 th November 2017 PUBLIC

Outline Motivation Calibration of SRH and TAT in homostructure InGaAs diodes Calibration of band-tails current in homostructure InGaAs diodes Quantum-mechanical aspect of traps Experimental TFETs at imec Conclusions 2

Ring oscillator performance comparison MOSFET/TFET GaAsSb p 300CGP 50CGP MOSFET TFETs InGaAs i ~2x 300CGP 50CGP n Circuit-level evaluation of TFETs, including parasitic resistances/capacitances: established BUT: no device-related parasitics yet in TFET device predictions 3

Sources of parasitic device currents Trap-assisted tunneling (TAT) in undoped channel in highly-doped source/drain at semiconductor hetero-interfaces at semiconductor-oxide interface Shockley-Read-Hall (SRH) in undoped channel in highly-doped source/drain Band tails due to structural disorder due to thermal fluctuations Phonon-assisted tunneling or Auger 1 generation/recombination (Random) electrostatic variations due to trap charges at semiconductor-oxide interface 2 Calibration and (correct) theoretical models required [1] J. Teherani et al., J. Appl. Phys. 120, 084507 (2016); [2] P. Asbeck et al., Steep Transistor Workshop, Oct. 2017 4

I ds [A/μm 2 ] E g,eff [ev] I ds [A/μm 2 ] E 1 [ev] Calibration history BTBT calibration with p-i-n diodes 1 10-5 10-10 t i =9nm In 0.53 Ga 0.47 As t i =18nm BTBT calibration t i =46nm with p-i-n diodes 2 experiment calib. simulation 10-15 0 0.2 0.4 0.6 0.8 FIQC proof with MOSCAPs 3 First subband energy level E 1 exp FIQC prediction E g,eff calibration with No FIQC hetero p-i-i-n diodes 4 In x Ga 1-x As and GaAs 1-y Sb y 10 18 10 19 10 20 x Source doping [cm -3 ] y V reverse bias [V] experiment simulation Si 0.75 Ge 0.25 V reverse bias [V] [1] Smets, J. Appl. Phys. 115, 184503 (2014); [2] Kao, J. Appl. Phys. 116, 214506 (2014); [3] Smets, Appl. Phys. Lett. 105, 203507 (2014); [4] Smets, Trans. Electron Dev. 63, 4248 (2016). 5.8 5.85 5.9 lattice constant [Å] 5

Parasitics in forward bias 1 : - bulk SRH recombination - bulk TAT InGaAs p + -n + diode p-i-n diode Forward bias: expected SRH/TAT currents p p i n n SRH in p-doped region dominant TAT increases with increasing forward bias [1] Q. Smets et al., Trans. Electron Dev. 64, 3622 (2017). 7

J [A/μm 2 ] Temperature dependence of parasitics in forward bias 1 InGaAs p + -n + diode p-i-n diode p+/n+ InGaAs diode p n Forward bias V np [V] Reverse bias Temperature-dependent measurements distinguish SRH/TAT/BTBT SRH: temperature-dependent TAT: increases with forward bias and temperature-independent [1] Q. Smets et al., Trans. Electron Dev. 64, 3622 (2017). 8

J [A/μm 2 ] Parasitics calibration in forward (and reverse) bias 1 : bulk-srh and bulk-tat p+/n+ InGaAs diode p simulation experiment p-i-n InGaAs diode simulation experiment E T,SRH τ SRH Calibrated parameters E i ± 0.16 ev 7 ns (1+N dop /10 16 cm -3 ) n E T,TAT E i + 0.16 ev τ TAT 1 μs (1+N dop /10 16 cm -3 ) V np [V] V np [V] o Temperature-dependent measurements allows calibration SRH and TAT o 2 diodes allow doping-dependent calibration [1] Q. Smets et al., Trans. Electron Dev. 64, 3622 (2017). 9

TFET predictions with calibrated SRH/TAT models 1 All-InGaAs p-n-i-n TFET with graded doping source p n-pocket transfer characteristics drain i n gate oxide o Calibrated bulk SRH and TAT applied to TFET: I TAT (and I SRH ) 50 pa/μm not limiting o To be calibrated: interface-trap-based (Dit) and hetero-interface SRH/TAT currents 2 [1] Q. Smets et al., Trans. Electron Dev. 64, 3622 (2017). [2] S. Sant et al., Trans. Electron Dev. 63, 4240 (2016). 10

Developing ballistic band-tails model: the band tails 1 Extended states Very localized states E edge,v E edge,c o Spatial fluctuations of dopant atoms band tails in doped regions o Our model: band tails from conventional band edge to E edge [1] J. Bizindavyi et al., 5 th Berkeley Symposium on E3S and Steep Transistors Workshop (IEEE), Oct. (2017). 12

Developing ballistic band-tails model: approach 1 Assumptions: Valence band-tails: k = k 1,v exp E 1,v E bts 3E 0,v Valence-band tails Conduction band-tails: k = k 1,c exp E bts E 1,c 3E 0,c Ballistic tunneling - conserving k J bts bts = - according to Tsu-Esaki formula: q x p 2π 2 ħ න qe x dx න k dk T E bts,v x, k f n (E bts,c x, k f p (E bts,v x, k x n k o Arbitrary energy dispersion, with correct band-tails DOS profile (Urbach energy E 0 ) o Ballistic tunneling similar to conventional BTBT tunneling [1] J. Bizindavyi et al., 5 th Berkeley Symposium on E3S and Steep Transistors Workshop (IEEE), Oct. (2017). 13

Band-tails contributions in semiconductor device 1 P-i-n diode in forward bias bts-to-cond bts-to-bts val-to-bts 3 current contributions: band-tails-to-band-tails, band-tails-to-cond.band and val.band-to-band-tails current [1] J. Bizindavyi et al., 5 th Berkeley Symposium on E3S and Steep Transistors Workshop (IEEE), Oct. (2017). 14

Experiment-theory discrepancy: band-tails current? p-i-n InGaAs diode Forward Mismatch Reverse Experiment BTBT + diff. Possible mechanisms: Phonon-assisted tunneling Band-tails tunneling Impossible to remove experiment-theory discrepancy with BTBT only What causes mismatch in forward bias? 15

Calibrate band tails model with p-i-n InGaAs diode 1 Experiment vs BTBT + diffusion Forward Reverse Mismatch Data + calibrated band-tails model Experiment BTBT + diff. o Calibration possible! E 0 = 70 mev for E edge of 100meV o Strong band-tails-to-band-tails tunneling current [1] J. Bizindavyi et al., 5 th Berkeley Symposium on E3S and Steep Transistors Workshop (IEEE), Oct. (2017). 16

TFET predictions with calibrated band-tails model 1 TFET architecture TFET prediction Predicted impact on TFET: larger than bulk-srh and bulk-tat Observable contribution at ~ 1nA/μm further investigation needed [1] J. Bizindavyi et al., 5 th Berkeley Symposium on E3S and Steep Transistors Workshop (IEEE), Oct. (2017). 17

E [ev] Level shift [mev] Impact of E-field on trap energy level 1 Trap level near E c Change of trap level with E-field o Trap energy level becomes trap energy range at high E-field o Emission rate from trap increases due to this broadening quantum-mechanical modeling required for TAT-predictions in TFET [1] M. Mohammed et al., J. Appl. Phys. 120, 245704 (2016). 19

SS [mv/dec] I g, I d [A] InGaAs TFET with sub-nanometer EOT and sub-60 mv/dec SS at RT 1 metal TiN SiO 2 Mo n+ InGaAs Mo Gate oxide 3nm InP Zn diffused 90nm i-53% InGaAs Transfer characteristics SS versus I ds Semi-insulating InP substrate Source doping ~ 2x10 19 at/cm 3 EOT = 0.8nm [1] A. Alian et al., Appl. Phys. Lett. 109, 243502 (2016). V gs [V] I ds [μa/μm] Homostructure TFET with 1.5 decades of current at sub-60mv/dec swing Excellent agreement of transfer characteristics up to 10nA/μm with QM predictions 21

Conclusions & outlook Circuit-level evaluation of parasitic-free TFETs: established Need for TFET predictions including parasitics Bulk-SRH and bulk-tat: feasible to reach non-impacting current levels Band-tails due to random doping: potentially impacting TFET performance Further investigation required Need to include relevant quantum-mechanical effects in parasitics modeling 24

Acknowledge The TFET research team Imec s (sub-)10nm CMOS partners including, Samsung, TSMC, GlobalFoundries, Intel, SK-Hynix,Toshiba, Micron, Qualcomm, Sony, Huawei and SanDisk J. Bizindavyi acknowledges the support of the FWO-Vlaanderen for a Strategic Basic Research PhD fellowship. The European Commission and Regional authorities for their support of European collaborative projects 25

Thank you!

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