Lec 10 Combinational CMOS Logic Circuits 1
Combinational vs. Sequential Logic In Combinational Logic circuit Out In Combinational Logic circuit Out State Combinational The output is determined only by Current inputs Sequential The output is determined by Current inputs Previous inputs Output = f(in) Output = f(in, Previous In) 2
Static CMOS Circuit t every point in time (except during the switching transients) each gate output is connected to either or V SS via a low-resistive path The outputs of the gates assume at all times the value of the oolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is contrasted to the dynamic circuit class, which relies on temporary storages of signal values on the capacitance of high impedance circuit nodes. 3
Static CMOS In 1 In 2 In N pmos Network Pull Up Network (PUN) f(in 1,In 2, In N ) In 1 In 2 In N nmos Network Pull own Network (PN) PUN and PN are dual logic networks The complementary operation of a CMOS gate» The nmos network (PN) is on and the pmos network (PUN) is off» The pmos network is on and the nmos network is off. 4
NMOS Transistors Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high X Y Y = X if and = X Y Y = X if OR =+ NMOS Transistors pass a strong 0 but a weak 1 5
PMOS Transistors Series/Parallel Connection PMOS switch closes when switch control input is low X Y Y = X if N = + X Y Y = X if OR = PMOS Transistors pass a strong 1 but a weak 0 6
Threshold rops PUN S 0 V GS S 0 - V Tn C L C L PN C L 0 V GS S C L V Tp S 7
CMOS Logic Style PUN is the UL of PN (can be shown using emorgan s Theorem s) The complementary gate is inverting N = NN + INV 8
Example Gate: NN 9
CMOS NOR2 Two-Input NOR Gate I,p I,p I,n I I,n 10
11 CMOS NOR2 Threshold Calculation (1/3) asic ssumptions» oth input and switch simultaneously (V = V )» The device sizes in each block are identical. (W/L) n, = (W/L) n,, and (W/L) p, = (W/L) p,» The substrate-bias effect for the PMOS is neglected V th Calculation y definition, V = V = V out = V th. The two NMOS transistors are V saturated because V GS = S, I = I,n + I,n = k n (V th -V T,n ) 2 I V th V T, n k n PMOS- operates in the linear region, and PMOS- is in saturation for V in = V out, k p 2 I, p 2V V th V T, p V S, p V S, p 2 I, p k p 2 V V th V T, p V S, p 2 I,n I,p I,p I,n F
12 CMOS NOR2 Threshold Calculation (2/3) Since I,p = I,p = I, we have Combine the above equations, we obtain which is different with the expression of V th (INV) k I V V V p p T th 2, k k V V k k V NOR V n p p T n p n T th 2 1 1 2 1 2) (,, k k V V k k V INV V n p p T n p n T th 1 ) (,,
CMOS NOR2 Threshold Calculation (3/3) If k n = k p and V T,n = V T,p, V th (INV) = /2. However, V T, n V th( NOR 2) 3 Equivalent-Inverter pproach (both inputs are identical)» The parallel connected nmos transistors can be represented by a nmos transistor with 2k n.» The series connected pmos transistors can be represented by a pmos transistor with k p /2. k p /2 V in V out 2k n 13
Therefore CMOS NOR2 Equivalent-Inverter pproach k p V T, n V T, p 4k n V th( NOR 2) k p 1 4k n To obtain a switching threshold voltage of /2 for simultaneous switching, we have to set V T,n = V T,p and k p =4k n Parasitic Capacitances and Simplified Equivalent Circuit: See Fig. 7.12 in Kang and Leblebici.» The total lumped load capacitance is assumed to be equal to the sum of all internal capacitances in the worst case. 14
CMOS NN2 Two-Input NN Gate 15
CMOS NN2 Threshold Calculation ssume the device sizes in each block are identical, (W/L) n, = (W/L) n,, and (W/L) p, = (W/L) p,, and by the similar analysis to the one developed for the NOR2 gate, we have V th V ( NN 2) T, n 2 k p 1 2 k n To obtain a switching threshold voltage of /2 for simultaneous switching, we have to set V T,n = V T,p and k n =4k p k k p n V V T, p 16
Layout of Simple CMOS Logic Gates (1/2) M 2 In Out M 1 In Out Inverter GN 17
Layout of Simple CMOS Logic Gates (2/2) Out 2-input NN gate GN 18
Stick iagram (1/2) oes not contain any information of dimensions. Represent relative positions of transistors asic Elements» Rectangle: iffusion rea» Solid Line: Metal Connection» Circle: Contact» Cross-Hatched Strip: Polysilicon INV NN2 Out Out In GN GN 19
Stick iagram (2/2) INV NN2 Out Out GN In GN 20
Complex CMOS Gates Functional esign (1/3) OR operations are performed by parallel-connected drivers. N operations are performed by series-connected drivers. Inversion is provided by the nature of MOS circuit operation. The realization of pull-down network is based on the same basic design principle examined earlier. The pmos pull-up network must be the dual network of the nmos pull-down network. One method systematically derives the pull-up network directly form the pull-down network. This method constructs the dual graph of the network. The pull-down network graph has nodes for circuit nodes and arcs for nfets with the each arc labeled with the literal on the input to the corresponding nfet. 21
Complex CMOS Gates Functional esign (2/3) 22 To construct a graph and pull-up network from a pull-down network» Insert a node in each of the enclosed areas within the pull-down network graph.» Place two nodes outside of the network separated by arcs from GN and OUT.» Connect pairs of new nodes by drawing an arc through each arc in the pull-down circuit that lies between the corresponding pairs of areas.» raw the resulting pull-up network with a pfet for each of the new arcs labeled with the same literal as on the nfet from which it came. The justification» The complement of a oolean expression can be obtained by taking its dual, replacing Ns with ORs and ORs with Ns and complementing the variables,» The graphical dual corresponds directly to the algebraic dual.» Complementation of the variables takes place automatically because each nfets is replaced with a pfet.
Complex CMOS Gates Functional esign (3/3) This method is illustrated by the generation of the pull-up from the pull-down shown. OUT OUT 1 OUT C 2 C C OUT GN On the dual graph, which of the two side nodes is labeled or OUT is functionally arbitrary. The selection may, however, affect the location of capacitances, and hence, the performance. 23
Complex CMOS Gates evice Sizing in Complex Gates (1/4) Method used for sizing NN and NOR gates also applies to complex gates Most easily transferred by examining all possible paths from OUT to GN (and from to OUT) Suppose that we are dealing with CMOS and the sized inverter devices use minimum channel lengths and widths W n and W p. For the pull-down network: 1. Find the length n max of the longest paths between OUT and through GN the network. Make the width of the nfets on these paths n max W n. In this algorithm, a path is a series of FETs that does not contain any complementary pair of literals such as X and X. 2. For next longest paths through the circuit between OUT and GN consisting of nfets not yet sized, repeat Step 1. 3. Repeat Step 2 until there are no full paths consisting of unsized nfets 24
Complex CMOS Gates evice Sizing in Complex Gates (2/4) 4. For each longest partial path in the circuit consisting of unsized nfets, based on the longest path between OUT and GN on which it lies, find the equivalent W eq required for the partial path. 5. Repeat Step 1 for each longest partial path from Step 4 with OUT and GN replaced the endpoints of the partial path. Make the widths of devices on the path equal to n max W eq where n max is the number of FETs on the partial path. 6. Repeat 4 and 5 for newly generated longest partial paths until all devices are sized. 25
Complex CMOS Gates evice Sizing in Complex Gates (3/4) OUT E H C G F GN This can be illustrated for the example above. L n =0.5μ, W n =5 μ, in the inverter. 1. longest path through the network from OUT to GN is - -C- with n max =4. Thus, the widths W, W, W C, W are 45=20 μ. This is the only longest path we can find from 26
Complex CMOS Gates evice Sizing in Complex Gates (4/4) OUT to GN without passing through a sized device. 2. H and G are partial path. ut it is important that they are considered as part of a longest between OUT and GN for evaluation. Thus, a split partial path consisting of H and G must be considered. ased on the evaluation segments, W eq =2W n =10μ. Thus, W H and W G are 110=10 μ. 3. The longest remaining partial path in the circuit is E-F with n max = 2. Since this path is in series with with width 4W n =20 μ, it needs to have an equivalent width of W eq determined from: 1 W n 1 4W n 1 W eq 1 5 1 20 1 W eq W eq = 20/3 μ and the widths W E and W F are 220/3 μ=40/3 μ. Since all devices are sized, we are finished. 27
Complex CMOS Gates Layout of Complex Gates (1/4) Goal: Given a complex CMOS logic gate, how to find a minimum-area layout. E E C C pmos network OUT E C E C nmos network 28
Complex CMOS Gates Layout of Complex Gates (2/4) rbitrary ordering of the polysilicon columns:» The separation between the polysilicon columns must allow for one diffusion-to-diffusion separation and two metal-to-diffusion contacts in between Consume a considerable amount of extra silicon area S S S S S pmos S Out S S S S nmos E C GN 29
Complex CMOS Gates Layout of Complex Gates (3/4) Euler Path pproach Objective: To order the inputs such that the diffusion breaks between input polysilicon strips is minimized, thereby reducing the width of the layout. efinition: n Euler path is an uninterrupted path that traverses each gate of the graph exactly once. pproach:» raw the graph for the NMOS and PMOS networks.» Find a common Euler path through both of the graphs. Note that nodes with an odd number of attached edges must be at the end points of the Euler path. Some circuits may not have Euler paths o Euler paths for parts of the circuit in such cases. circuit constructed using the dual graph method is more likely to have an Euler path.» Order the transistor pairs in the layout in the order of the path from left to right or right to left. 30
Complex CMOS Gates Layout of Complex Gates (4/4) nmos network Common Euler path E pmos network E C E----C C Euler path successful: Order: E----C o the symbolic layout (stick diagram)» More compact, simple routing of signals, and consequently, less parasitic capacitance S S S S S pmos S Out S S S S nmos GN E C 31
Complex CMOS Gates OI Gates OI (N-OR-INVERT): Enable the sum-of-products realization of a oolean function in one logic gate.» The pull-down network consists of parallel branches of series-connected nmos driver transistors.» The corresponding pull-up network can be found using the dual-graph concept. Example: OUT = 1 2 3 + 1 2 +C 1 C 2 C 3 1 2 3 ual pmos Pull-up network OUT 1 2 1 1 C 1 C 1 C 2 C 3 2 3 2 C 2 C 3 32
Complex CMOS Gates OI Gates OI (OR-N-INVERT): Enable the product-of-sums realization of a oolean function in one logic gate.» The pull-down network consists of series branches of parallel-connected nmos driver transistors.» The corresponding pull-up network can be found using the dual-graph concept. OUT = ( 1 + 2 + 3 )( 1 + 2 ) C 1 ual pmos Pull-up network 1 2 3 OUT 1 2 1 C 1 2 C 1 3 2 3 33
Complex CMOS Gates Pseudo-NMOS In Pseudo-NMOS, the PMOS network is replaced by a single pfet with its gate attached to GN. This provides a fixed load such as on NMOS circuits, hence called pseudo-nmos. dvantage: Eliminate the PMOS network and hence reduce area. isadvantages:» ack to ratioed design and V OL problems as in NMOS since PFET is always ON.» Non-zero static power dissipation. pmos transistor acting as load OUT C 1 1 2 3 2 3 34
Ratioed Logic (1/2) Ratioless Logic: The logic levels are not dependent upon the relative device sizes. Ratioed Logic: The logic levels are determined by the relative dimensions of composing transistors Resistive Load R L epletion Load V T < 0 PMOS Load F F V SS F In 1 In 2 In 3 PN In 1 In 2 In 3 PN In 1 In 2 In 3 PN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudo-nmos Goal: To reduce the number of devices over complementary CMOS 35
Ratioed Logic (2/2) Resistive Load R L N transistors + Load V OH = F V OL = R PN R PN + R L In 1 In 2 In 3 PN ssymetrical response Static power consumption V SS t pl = 0.69 R L C L 36
ctive Loads epletion Load V T < 0 PMOS Load F V SS F In 1 In 2 In 3 PN In 1 In 2 In 3 PN V SS V SS depletion load NMOS pseudo-nmos 37
Pseudo-NMOS C F C L k V n OL V OH = (similar to complementary CMOS) V 2 V V V V V OL p 2 k p V V 1 1 (ssuming V V V ) Tn T OL k n Smaller area and load but Static power dissipation!!! k 2 Tp T 2 Tn Tp 38
CMOS Full-dder Circuit Cin Full adder Cout C in S C out Carry status 0 0 0 0 0 delete 0 0 1 1 0 delete Sum 0 1 0 1 0 propagate 0 1 1 0 1 propagate 1 0 0 1 0 propagate 1 0 1 0 1 propagate 1 1 0 0 1 generate 1 1 1 1 1 generate 39
CMOS Full-dder Circuit The inary dder Cin Full adder Cout Sum Sum = C in = C in + C in + C in + C in = C + (++C)C out C out = + C in + C in at least two of,, and C are zeros 40
CMOS Full-dder Circuit Express Sum and Carry as a Function of P, G, efine three new variable which ONLY depend on, Generate (G) = Propagate (P) = elete ()= C out (G,P) = G+PC in Sum(G,P) = PC in Can also derive expressions for S and C out based on and P. G = 1: Ensure that the carry bit will be generated = 1: Ensure that the carry bit will be deleted P = 1: Guarantee that an incoming carry will be propagated to C out Note that G, P and are only functions of and and are not dependent on C in 41
CMOS Full-dder Circuit The Ripple-Carry dder The N-bit adder is constructed by cascading N full-adder circuits. The carry bit ripples from one stage to the other. The delay through the circuit depends upon the number of logic stages which need to be traversed, and is a function of the applied signals. 0 0 1 1 2 2 3 3 C i,0 C o,0 C o,1 C o,2 C o,3 F F F F ( C i,1 ) S 0 S 1 Worst case delay linear with the number of bits p = O(N) adder (N-1) carry + sum Goal: Make the fastest possible carry path circuit S 2 S 3 42
CMOS Full-dder Circuit Transistor-Level of One-it Full-dder Circuit C i C i X C i C i S C i C i C o 28 transistors 43
CMOS Full-dder Circuit Inversion Property C i F C o C i F C o S S S(,,C i ) = S(,,C i ) C o (,,C i ) = C o (,,C i ) 44
CMOS Full-dder Circuit Minimize Critical Path by Reducing Inverting Stages (1/2) Even cell Odd cell 0 0 1 1 2 2 3 3 C i,0 C o,0 C o,1 C o,2 C o,3 F F F F S 0 S 1 S 2 S 3 0 0 1 1 2 2 3 3 C i,0 C o,0 C o,1 C o,2 C o,3 F F F F S 0 S 1 S 2 S 3 45
CMOS Full-dder Circuit Minimize Critical Path by Reducing Inverting Stages (2/2) Even cell Odd cell 0 0 1 1 2 2 3 3 C i,0 C o,0 C o,1 C o,2 C o,3 F' F' F' F' S 0 S 1 S 2 S 3 *F' is a full adder without the inverter in the carry path. Exploit Inversion Property The number of inverting stages in the carry path is reduced. The only disadvantage is that it need different cells for the even and old slices. 46
CMOS Full-dder Circuit etter Structure: The Mirror dder (1/3) Carry Generation Circuitry» Carry-inverting gate is eliminated» PN and PUN networks are not dual or G is high C 0 is set to or GN C out (G,P) = G+PC in Sum(G,P) = PC in P is high the incoming carry is propagated to C 0 "0"-Propagate C i Kill C o C i C i S "1"-Propagate Generate C i C i 24 transistors 47
CMOS Full-dder Circuit The Mirror dder (2/3) Only need 24 transistors. NMOS and PMOS chains are completely symmetrical. This guarantees identical rising and falling time if the NMOS and PMOS devices are properly sized. maximum of two series transistors can be observed in the carry generation circuitry. The critical issue is to minimize the capacitance at node C 0. Capacitance at node C 0» 4 diffusion capacitances» 2 internal gate capacitances» 6 gate capacitances in the connecting adder cell total 12 gate capacitances (ssume C diffusion C gate ) The transistors connected to C i are placed closest to the output. Only the transistors in the carry stage have to be optimized for speed. ll transistors in the sum gate can be minimum-size. 48
CMOS Full-dder Circuit The Mirror dder (3/3) C i C o C i C i C i C i C o C i C o S GN Stick iagram 49
Pass Transistors The pass transistor is an nfet used as a switch-like element to connect logic and storage. Vin VC Vout VC = 1 VC = 0 Used in NMOS; sometimes used in CMOS to reduce cost. The voltage on the gate, V C, determines whether the pass transistor is open or closed as a switch.» If V C = H, it is closed and connects V out to V in.» If V C = L, it is open and V out is not connected to V in. Consider V in = L and V in = H with V C = H. With V in = L, the pass transistor is much like a pull-down transistor in an inverter or NN gate. So V out, likewise, becomes L. ut, for V in = H, the output becomes the effective source of the FET. When V GS = -V OUT =V Tn, the nfet cuts off. The H level is V OUT = - V Tn. 50
Transmission Gates (Pass Gates) (1/2) With body effect, for = 5V, the value on V out can be around 3.0 to 3.5 V. This reduced level diminishes NM H and the current drive for the gate or gates driven by the pass transistor. For both NMOS and CMOS, the lack of current drive slows circuit operation and NM H can be particularly problematic. s a consequence, in CMOS, a pfet is added to form a transmission gate. Transmission Gates Symbols: C C C Circuit C Popular Usage 51
Transmission Gates (2/2) Operation» C is logic high oth transistors are turned on and provide a low-resistance current path between nodes and.» C is logic low oth transistors will be off, and the path between nodes and will be open circuit. This condition is called the high-impedance state. With the parallel pfet added, it can transfer a full from to (or to ). It can also charge driven capacitance faster. The substrates of NMOS and PMOS are connected to ground and, respectively. Therefore, the substrate-bias effect must be taken into account. 52
Transmission Gates C nalysis (1/3) V in =, V C =, and node is connected to a capacitor, which represents capacitive loading of the subsequent logic stages. 0V V in = I IS,p IS,n V out The nmos transistor, V S,n = V out, and V GS,n = V out. Thus,» Turn off: If V out > V T,n» Saturation: If V out < V T,n The pmos transistor, V S,p =V out, and V GS,p =. Thus,» Saturation: If V out < V T,p» Linear: If V out > V T,p 53
Transmission Gates C nalysis (2/3) Region 1 Region 2 Region 3 nmos: saturation pmos: saturation nmos: saturation pmos: linear reg. nmos: cut-off pmos: linear reg. 0V V T,p ( -V T,n ) V out The current flowing through the transmission gate is equal to I = I S,n + I S,p The equivalent resistance for each transistor can be represented as R eq,n = ( -V out )/I S,n and R eq,p = ( -V out )/ I S,p R eq = R eq,n R eq,p 54
Transmission Gates C nalysis (3/3) The values of R eq,n and R eq,p Region 1 R R eq, n eq, p k k n p 2( V 2( V V V V V out V V out out ) T, p ) V T, n 2 2 55 Region 2 Region 3 R R R eq, p eq, n eq, p k k k p n p 2( V V 2 V V V out V out V 2 T, p ) T, n 2 V V 2 V V 2 T, p V V out out
Resistance of Transmission Gate R R eq,p R eq,n R eq,n R eq,p V out 0 -V T,n The parallel combination of the pfet and the nfet result in an equivalent resistance that is roughly constant. This constant value, R eq, can be used in series with an ideal switch controlled by C and C to model the transmission gate. See p. 311 of the text book. The implementation of CMOS transmission gates in logic circuit design usually results in compact circuit structures which may even require a smaller number of transistors. 56
pplications of Transmission Gate Example: XOR M2 F M1 M3/M4 Only need 6 transistors 57
pplications of Transmission Gate Example: Multiplexer S S S F = S+S S S 58
pplications of Transmission Gate Examples: Transmission Gate Full dder Generate (G) = Propagate (P) = P C i C i P P S C out (G,P) = G+PC in Sum(G,P) = PC in Sum Generation P P P C o Carry Generation C i C i Setup C i P Similar delays for sum and carry 59