igital Integrated Circuits esign Perspective esigning Combinational Logic Circuits 1
Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit Out State Combinational Sequential Output = f(in) Output = f(in, Previous In) 2
Static CMOS Circuit t every point in time (except during the switching transients) each gate output is connected to either V or GN via a low-resistive path. The outputs of the gates assume at all times the value of the oolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. 3
Static Complementary CMOS PUN provides a connection between output and V, when the output of the gate evaluates a 1. The PN provides a connection between output and ground, when the output of the gate evaluates a 0. In1 In2 V PUN PMOS only In steady-state, the output node is lowimpedance InN F(In1,In2, InN) In1 In2 InN PN NMOS only PUN and PN are dual logic networks 4
NMOS Transistors in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high X Y Y = X if and X Y Y = X if OR NMOS Transistors pass a strong 0 but a weak 1 5
PMOS Transistors in Series/Parallel Connection PMOS switch closes when switch control input is low X Y Y = X if N = + X Y Y = X if OR = PMOS Transistors pass a strong 1 but a weak 0 6
Threshold rops PUN V S V V 0 V V GS S 0 V - V Tn PN V 0 V V Tp V V GS S S 7
Complementary CMOS Logic Style 8
Example Gate: NN 9
Example Gate: NOR 10
Complex CMOS Gate C C OUT = + ( + C) 11
Constructing a Complex Gate OUT = + ( + C) V V C F SN1 F SN4 SN2 C C SN3 F (a) pull-down network (b) eriving the pull-up network hierarchically by identifying sub-nets C (c) complete gate 12
Properties of Complementary CMOS Gates Snapshot High noise margins: V OH and V OL are at V and GN, respectively. No static power consumption: There never exists a direct path between V and V SS (GN) in steady-state mode. Comparable rise and fall times: (under appropriate sizing conditions) 13
CMOS Properties Full rail-to-rail swing; high noise margins Logic levels not dependent upon the relative device sizes; ratioless lways a path to Vdd or Gnd in steady state; low output impedance No direct path steady state between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistors 14
Switch elay Model R eq R p R p R p R p R n R n R p C int R n NN2 C int INV R n R n NOR2 15
Input Pattern Effects on elay R p R n R n R p C int elay is dependent on the pattern of inputs Low to high transition both inputs go low delay is 0.69 R p /2 one input goes low delay is 0.69 R p High to low transition both inputs go high delay is 0.69 2R n Series devices should be made wider to avoid performance penalty. When sizing the transistors in a gate with multiple inputs, we should pick the combination of inputs that triggers the worst case condition (be careful of self-loading) 16
Example: elay ependence on Input Patterns In general, the sizing should result in approx. equal worst case rise and fall times. Voltage [V] 3 2.5 2 1.5 1 0.5 0-0.5 ==1 0 =1, =1 0 =1 0, =1 0 100 200 300 400 time [ps] Input ata Pattern ==0 1 =1, =0 1 = 0 1, =1 ==1 0 =1, =1 0 = 1 0, =1 elay (psec) 17 67 64 61 45 80 81 NMOS = 0.75µm/0.25 µm PMOS = 0.75µm/0.25 µm = 100 ff
Transistor Sizing (compared to a CMOS inverter) R p R p R p 2 2 4 2 R n 4 R p C int 2 R n C int 1 R n R n 1 18
Transistor Sizing a Complex CMOS Gate 8 6 4 3 C 8 6 4 6 OUT = + ( + C) 2 1 2 C 2 19
Fan-In Considerations C C C 3 C 2 C 1 istributed RC model (Elmore delay) t PHL = 0.69[ R. C1 + ( R1 + R2 ). C2 + ( R1 + R2 + R3 ). C2 + ( R1 + R2 + R3 + R4). C 1 L t phl = 0.69 R eqn (C 1 +2C 2 +3C 3 +4 ) R 1 appears in all terms, making this device especially important when attempting to minimize delay. ] Internal node capacitances consist of junction capacitances, and gate-to-source and gate-to-drain capacitances (turned into capacitances with ground using Miller equivalent) 20
t p as a Function of Fan-In t p (psec) 1250 1000 750 500 t phl quadratic Gates with a fan-in greater than 4 should be avoided. 250 0 fan-in t plh 2 4 6 8 10 12 14 16 linear 21
Fast Complex Gates: esign Technique 1 Transistor sizing as long as fan-out capacitance dominates Progressive sizing In N MN istributed RC line In 3 M3 C 3 M1 > M2 > M3 > > MN (the fet closest to the output is the smallest) In 2 In 1 M2 M1 C 2 C 1 Can reduce delay by more than 20%. Problem: esign rule considerations force designer to push transistors apart -> internal capacitance grows. 22
Fast Complex Gates: esign Technique 2 Transistor ordering critical path critical path In 3 1 In 2 1 In 1 0 1 M3 M3 M2 C 2 charged In 1 2 M2 C2 M1 charged In 3 1 M1 C 1 charged 0 1 In 1 C 1 charged discharged discharged delay determined by time to discharge, C 1 and C 2 delay determined by time to discharge 23
Fast Complex Gates: esign Technique 3 lternative logic structures F = CEFGH 24