O AM CHAACTESTCS Static p amp limitatins EFEENCE: Chapter 5 textbk
(ESS) EOS CAUSED BY THE NUT BAS CUENT AND THE NUT OFFSET CUENT Op Amp t functin shuld have fr the input terminals a DC path thrugh which current can flw. nput bias current N B = tage, nput ffset vl N OS B = deally OS = 0 but due t mismatch i.e., fr 74C OS 0 00nA 0nA and 500nA 80nA OS B N V V = N V als since V = = N V N V - V O = = N N E - V
Nte that N and can be expressed as B OS = B OS = N Then the utput ffset vltage can be expressed as E O = B Nte that if = Then E E // O = becmes O OS Ntice that ne can keep the rati / cnstant but can reduce the values f and t minimize E O. Let us discuss anther technique t reduce the input ffset errr. OS
Fr any cnfiguratin (inverting r nn-inverting) ne can write v = A V E where s A i s = E = s E E where = β β [ V ( // ) ] The input ffset vltage V s can be mdeled as shwn next. s V s = E = Vs max V 6 mv s = ± i.e. min V = ± mv fr a 74 Fr = 9 Wrst case is ( ± 6mV) = 60mV. E = 0 ±
v // 74 V 6 3 0K 5 v 5V ractical nternal Offset-Errr-Nulling. E is the ttal ffset errr referred t the utput/ Example v E v = v E = E = E β v E ( V ( // ) ) s = t ( t) V ( ξ) = s C V s s [ E ] dξ V ( 0) ntegratr with nternal Offset-Errr Nulling.
Static p amp limitatins Lw input bias current p amps. Super-beta input p amps: β F ~ 000!, LM308 ( B = na). nput bias current cancellatin: Using internal circuitry, O 07 ( B = na, OS =0.4 na) 3. JFET input p amps: G in the rder f tens f ic amps. LF 356 BiFET ( B = 30 pa, OS =3 pa), AD549, OA9: Special JFET slatin techniques ( B < 00 fa) 4. MOSFET input p amps: nput leakage current is arund pa. TLC 79 CMOS ( B = 0.7 pa, OS =0. pa), nput bias current drift Fr Biplar p amps increasing the temperature decreases B Fr p-n junctin (Dide r JFET ): B (T) ~ B (T0). T0 : Ambient temperature ( C) (T T0)/0 At high temperatures, there is n advantage in using FET p amps
Static p amp limitatins )nput ffset vltage V = a. (v v N ); By shrting v and v N : v = 0, Due t inherent mismatches v is nt zer T frce v t zer, a suitable crrectin vltage must be applied between the input prts. v = a. (v V s v N ) = 0; v N= v V s Errrs caused by V s : E = (( / )). V s >> : gd fr measuring V s
Static p amp limitatins Thermal Drift Temperature cefficient: T c (V s ) = d V s / dt (mv/ C) V s (T) ~V s (5 C) Tc (V s ). (T -5 C) Cmmn Mde ejectin ati We mdel this phenmena with a change in the input ffset vltage due t v CM variatin / CM = d V s / d v CM (μv/v), n practice v CM ~v wer Supply ejectin atin We mdel this phenmena with a change in the input ffset vltage due t supply variatin : / S = d V s / d V S (μv/v) Changes f V s with utput swing Δ Vs = Δ v / a
Static p amp limitatins Summary f effects which generate V s : V s = V s0 Tc (V s ). ΔΤ (Δ V p / CM) (Δ V s / S) (Δv / a) 3 ) nput ffset errr cmpensatin nternal ffset nulling: E =( ( / )). [ V s -( ) s ] E = V s -( ) s E can be nulled by using a suitable trimmer, a smart designer tries t minimize E by a cmbinatin f circuit tricks (scaling, p amp selectin, etc). The last chice wuld be trimming.
Static p amp limitatins External ffset nulling: Des nt intrduce any additinal imbalance t the input stage, n degradatin drift CM, S nput Errr: E V x B >> C (Excessive lading f the wiper) A << (Avid perturbing)
Dynamic p amp limitatins ef. Ch 6 textbk )Open-lp respnse Dminant ple respnse: Lw frequencies: Higher frequencies: Lw pass filter actin Expressin fr pen-lp respnse: The pen-lp respnse has higher rder ples and zeres, but the dminant ple frequency is chsen deliberately lw t ensure that gain has drpped well belw unity and the effect f higher rder rts can be ignred
Dynamic p amp limitatins Dminant ple respnse: Fr general purpse type p amps: 500 khz < GB <0 MHz a 0 and df b are ill-defined d because f eq and a due t manufacturing prcess variatins. f t is mre practical parameter. Stable, predictable values f A and C C Graphical visualizatin f lp-gain:
)Clsed-lp respnse Nn- inverting Amplifier: Dynamic p amp limitatins a) T >>, A ~ A ideal b) T =, phase (T) = - 90, A =A ideal / ( j) c) T <<, A ~ A ideal. T=a Negative feedback reduces gain frm a 0 t A 0 (A 0 << a 0 ), but widens the bandwidth frm f b t f B (f b >> f B ). Gain Bandwidth trade ff: GB = A 0. f B = f t
Dynamic p amp limitatins nverting Amplifier: Gain Bandwidth trade ff: GB = A 0. f B = ( / ). f t. ( / ( ) ) = (- β). ft Nn-inverting unity gain amplifier : GB = f t nverting unity gain amplifier : GB = 0.5 f t 3) Output and input impedances z d, z are capacitive r inductive z c, cmmn mde input impednace Data sheets prvide r d, r, r c Sme times C d, C c infrmatin is prvided ~ z ( T ) (series) r ~ z ( T ) - (shunt) By decreasing T at higher frequencies the series impedance is mre capacitive and the shunt mpedance is mre inductive
nput series impedance: Dynamic p amp limitatins Output series impedance: Equivalent Circuit nput Output
nput shunt impedance: Dynamic p amp limitatins Output shunt impedance: Equivalent Circuit Output
4)Transient respnse Dynamic p amp limitatins Examining the transient respnse t a step signal ise Time (t ) t : time fr V t swing frm 0% t 90% f V m : g m Slew ate limiting Abve a certain step amplitude the utput slpe saturates at a cnstant value named slew-rate and the utput wavefrm is a ramp Slew rate limiting is a nnlinear effect that stems frm the limited ability by the internal circuitry t charge r discharge the frequency cmpensatin capacitr C c
Dynamic p amp limitatins Generalizatin fr β < : f t β. f t Full - wer Bandwidth : The maximum frequency at which h the p amp will yield an undistrted t dac utput t With the largest pssible amplitude. Settling time (t s ) The time it takes fr the respnse t a large input signal t settle and remain within Specified errr band (0.% and 0.0%nf 0%nf a 0 V input step). Test Circuit fr t s Fast t s is desirable in high speed, high accuracy D-A cnverters, S & H circuits and multiplexed amplifiers
Dynamic p amp limitatins Slew rate limiting causes and cures V m small; input stage in linear regin: By verdriving input stage i saturates at t A and dc c is current starved. During slew-rate limiting, v N may depart frm v (input stage saturatin). Three different ways f imprving S.. : () ncreasing ft (reducing Cc) () educing gm (3) ncreasing A