MOS Transistors Models

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MOS Transistors Models Andreas G. Andreou Pedro Julian Electrical and Computer Engineering Johns Hopkins University http://andreoulab.net

The MOS transistor Levels of Abstraction- Model Equations If V GS < 0 I DS = 0 Symbol D S G G B B S D G B If V DS > V GS V TO NMOS PMOS S D I DS = W L UO 2 ε 0ε r ( TOX V GS V T ) 2 If V DS < V GS V TO I DS = W L UO ε 0ε r ( TOX V V GS T )V DS V 2 DS 2 V T = V TO + γ ( φ V BS φ ) SEM photograph Layout Ids 55nm SST Flash Cell Model Current-Voltage Characteristics Vds Current Voltage Characteristics MATHEMATICAL PHYSICAL 520.216 2

What is a model? 1. An intuitive and conceptual abstraction of a complex physical process 2. A mathematical abstraction of a complex physical process that is capable of predicting experimental observations. 520.216 3

What is a MODEL? 1. An intuitive and conceptual abstraction of a complex physical process 2. A mathematical abstraction of a complex physical process that is capable of predicting experimental observations. 520.216 4

MOS fluidic analogy: a conceptual model (I) MOS Capacitor From Mead and Conway MOS Transistor Varia Bias MOS Transistor 520.216 5

NMOS as a switch/resistor: a conceptual model (II) not a good one 520.216 6

PMOS as a switch/resistor: a conceptual model (III) not a good zero 520.216 7

What are the physical values for 0 and 1 chip/logic voltages (blue line) 520.216 8

MOS switch model relation to I-V characteristics (I) Ids With digital input on gate the device is either ON or OFF 180nm technology Vds 520.216 9

MOS switch model relation to I-V characteristics (II) Ids With digital input on gate the device is either ON or OFF Approximate ON with the blue line 180nm technology Vds R ON ~ 3.3 V / 0.55 ma = 6K 520.216 10

What is a MODEL? 1. An intuitive and conceptual abstraction of a complex physical process 2. A mathematical abstraction of a complex physical process that is capable of predicting experimental observations. 520.216 11

Conduction ohmic- vs saturation Device operation characterized by the form of the current as a function of the bias voltage between the DRAIN and the source terminals (Vds) Conduction (also known as Ohmic) Saturation 520.216 12

Above threshold vs sub-threshold behaviour Device operation characterized by the form of the current as a function of the bias voltage between the gate and the source terminals (Vgs) 520.216 13

MOS transistor mathematical model 520.216 14

Mathematical model above threshold- If V GS < 0 I DS = 0 If V DS > V GS V TO Saturation I DS = W L UO 2 ε 0ε r ( TOX V V GS T ) 2 If V DS < V GS V TO Ohmic I DS = W L UO ε 0ε r TOX ( V V GS T )V DS V 2 DS 2 V T = V TO + γ ( φ V BS φ ) Model parameters 520.216 15

Above threshold vs sub-threshold behaviour Device operation characterized by the form of the current as a function of the bias voltage between the gate and the source terminals (Vgs) 520.216 16

Mathematical model subthreshold- I D I DS = S I n0 exp κ V n GB V t exp V SB V t exp V DB V t I D I SD = S I p0 exp κ V p GB V t exp V SB V t exp V DB V t V t kt q κ η 1 ox C ox C + C dep S W L I p0 = 0.5 10 18 A I n0 = 0.9 10 18 A Parameters: κ = 0.7 V t = 0.26Volts 520.216 17

Operating current for an NMOS IV Curve of ON device vdd V ds I ds Operates on one of two curves on off Looks like a current source initially (high V ds) Looks like a resistor later (low V ds ) Open circuit always 520.216 18

Operating current for a PMOS IV Curve of ON device vss I ds Same behavior as NMOS Open circuit when off Current source or resistor when on V ds 520.216 19

Computer Aided Design Tools DSCH 3 Schematic Modeling Analog & digital Library models Digital Simulation Verilog Extraction SPICE Extraction SPICE Simulator (3 rd Party) LTSpice WindSpice FPGA Tools Verilog File Synthesis Functional Simulation Verilog Compiler Constraints Floorplanning ModelSim / other nanolambda Layout Editor Technology rule files Place & Route Programming File Place & Route Analysis DRC, ERC Delay Analyzer Crosstalk Analyzer 2D Cross section 3D Analyzer.bit or.jed FPGA / CPLD Boards IO Cards Traffic Light Controller, Key Pad, Display (LCD, 7 segs) Layout Extraction Layout Conversion SPICE, CIF ProTHUMB Advance post layout simulator MICROWIND 3 Tape out to FAB. CIF http://www.microwind.net MICROWIND Tool 3 rd Party Tools 520.216 20

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