ENGG 1203 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR. Parity checking (for interest) Recall : Simplification methods. Recall : Time Delay

Similar documents
Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing

Chapter 7 Logic Circuits

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

Minimization techniques

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions

ENGG 1203 Tutorial _03 Laboratory 3 Build a ball counter. Lab 3. Lab 3 Gate Timing. Lab 3 Steps in designing a State Machine. Timing diagram of a DFF

Gate-Level Minimization

WORKBOOK. Try Yourself Questions. Electrical Engineering Digital Electronics. Detailed Explanations of

Logic Simplification. Boolean Simplification Example. Applying Boolean Identities F = A B C + A B C + A BC + ABC. Karnaugh Maps 2/10/2009 COMP370 1

ENGG 1203 Tutorial_9 - Review. Boolean Algebra. Simplifying Logic Circuits. Combinational Logic. 1. Combinational & Sequential Logic

Chapter 2. Digital Logic Basics

Cs302 Quiz for MID TERM Exam Solved

211: Computer Architecture Summer 2016

ENG2410 Digital Design Combinational Logic Circuits

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University

Unit 2 Session - 6 Combinational Logic Circuits

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata

ELC224C. Karnaugh Maps

EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive

CHAPTER 7. Solutions for Exercises

MC9211 Computer Organization

UNIT 5 KARNAUGH MAPS Spring 2011

Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms

This form sometimes used in logic circuit, example:

CS/COE0447: Computer Organization and Assembly Language

Principles of Computer Architecture. Appendix B: Reduction of Digital Logic. Chapter Contents

Z = F(X) Combinational circuit. A combinational circuit can be specified either by a truth table. Truth Table

Boolean Algebra & Logic Gates. By : Ali Mustafa

Karnaugh Map & Boolean Expression Simplification

CHAPTER 7. Exercises 17/ / /2 2 0

Boolean Algebra and Logic Simplification

Introduction to Karnaugh Maps

Midterm Examination # 1 Wednesday, February 25, Duration of examination: 75 minutes

Digital Logic (2) Boolean Algebra

Karnaugh Maps for Combinatorial Logic CS 64: Computer Organization and Design Logic Lecture #12

EEE130 Digital Electronics I Lecture #4


Computer Organization I. Lecture 13: Design of Combinational Logic Circuits

Digital Logic Appendix A

Ch 2. Combinational Logic. II - Combinational Logic Contemporary Logic Design 1

Reg. No. Question Paper Code : B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER Second Semester. Computer Science and Engineering

Karnaugh Maps (K-Maps)

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps

CPE100: Digital Logic Design I

Spiral 1 / Unit 5. Karnaugh Maps

( c) Give logic symbol, Truth table and circuit diagram for a clocked SR flip-flop. A combinational circuit is defined by the function

1 Boolean Algebra Simplification

CSE 140 Midterm I - Solution

UNIVERSITI TENAGA NASIONAL. College of Information Technology

Sample Test Paper - I

Week-I. Combinational Logic & Circuits

Outcomes. Spiral 1 / Unit 5. Logic Function Synthesis KARNAUGH MAPS. Karnaugh Maps

Ex: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC.

Number System. Decimal to binary Binary to Decimal Binary to octal Binary to hexadecimal Hexadecimal to binary Octal to binary

Philadelphia University Student Name: Student Number:

Boolean Algebra. Digital Logic Appendix A. Postulates, Identities in Boolean Algebra How can I manipulate expressions?

Karnaugh Maps ف ر آ ا د : ا ا ب ا م آ ه ا ن ر ا

Save from: cs. Logic design 1 st Class أستاذ المادة: د. عماد

Midterm1 Review. Jan 24 Armita

Philadelphia University Student Name: Student Number:

Logic Gate Level. Part 2

DIGITAL LOGIC CIRCUITS

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18

Combinational Logic Fundamentals

Chap 2. Combinational Logic Circuits

Boolean Algebra. Digital Logic Appendix A. Boolean Algebra Other operations. Boolean Algebra. Postulates, Identities in Boolean Algebra

Digital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.

Department of Electrical & Electronics EE-333 DIGITAL SYSTEMS

Circuits & Boolean algebra.

Chapter 2 Combinational Logic Circuits

Digital Logic Design ABC. Representing Logic Operations. Dr. Kenneth Wong. Determining output level from a diagram. Laws of Boolean Algebra

COSC 243. Introduction to Logic And Combinatorial Logic. Lecture 4 - Introduction to Logic and Combinatorial Logic. COSC 243 (Computer Architecture)

Combinational Logic Design/Circuits

Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution

UNIT 4 MINTERM AND MAXTERM EXPANSIONS

DHANALAKSHMI COLLEGE OF ENGINEERING, CHENNAI DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN

Final Exam. ECE 25, Spring 2008 Thursday, June 12, Problem Points Score Total 90

Digital Logic Design. Combinational Logic

Part 1: Digital Logic and Gates. Analog vs. Digital waveforms. The digital advantage. In real life...

Logic. Combinational. inputs. outputs. the result. system can

Fundamentals of Boolean Algebra

XI STANDARD [ COMPUTER SCIENCE ] 5 MARKS STUDY MATERIAL.

Chapter 2 Combinational logic

ELCT201: DIGITAL LOGIC DESIGN

Review for Test 1 : Ch1 5

1. Name the person who developed Boolean algebra

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3

Different encodings generate different circuits

In Module 3, we have learned about Exclusive OR (XOR) gate. Boolean Expression AB + A B = Y also A B = Y. Logic Gate. Truth table

The Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals

Synchronous Sequential Logic

DIGITAL ELECTRONICS & it0203 Semester 3

Chapter 4 BOOLEAN ALGEBRA AND THEOREMS, MINI TERMS AND MAX TERMS

Karnaugh Maps Objectives

Advanced Boolean Logic and Applications to Control Systems

Combinational Logic. Course Instructor Mohammed Abdul kader

Fundamentals of Digital Design

Lecture 22 Chapters 3 Logic Circuits Part 1

Digital Fundamentals

Transcription:

ENGG 23 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR Parity checking (for interest) Parity bit Parity checking Error detection, eg. Data can be Corrupted Even parity total number of s is even Odd parity total number of s is odd (total number include Parity bit) XOR (2 input) to compute the parity. e.g. : even parity parity sum is even parity bit = parity sum is odd parity bit = 2 Recall : Simplification methods Add redundant terms Recall : Time Delay multiple by = A + A AB + BC +A C = AB + BC (A+A ) + A C = AB + ABC + A BC + A C = AB (+C) + A C (+B) = AB + A C Add = A A (A+B)(A +C)(B+C) = (A+B)(A +C)((B+C)+ AA ) = (A+B)(A +C)(B+C+A)(B+C+A ) = (A+B)((A+B)+C)(A +C)((A +C)+B) = (A+B)(A +C) 3 3 time delay 2 time delay 5 gates 2 gates 4

Question a) Simplify the circuit shown in the figure using Boolean algebra. b) Change each NAND gate in the circuit of the figure to a NOR gate, M NQ and simplify the circuit using M NQ Boolean algebra. M NQ Solution (a) x MNQ MNQ MNQ MNQ M NQ M NQ MNQ M NQ M NQ M N N QMNQ M Q MNQ M MN M N Q Q M MN M NM NM M N M M M N 5 Less gate (power and resource) Shorter longest path => faster (what make the dalay? ) 6 Solution (b) Change each NAND gate in the circuit of the figure to a NOR gate First, we convert the circuit M NQ M NQ M NQ Then, we simplify the Boolean expression X M N Q M N Q M N Q M N QM N QM N Q (Expand) MM MN MQ NM N N NQ QM QN QQM N Q M MN MQ NM NQ QM QN QM N Q (Simplify) AB AB A B AB AA ABBABB AA A AA A A (DeMorgan's Theorem) (Group, Group) 7 8

Question 2... M MN MQNM NQ QM QN QM N Q M N QN Q QN N M N Q M QM N Q (Expand) MM MN MQ QM QN QQ M M N MN Q Q (Simplify) (Simplify) (Group, Group) (Simplify) MN QQMN Q A A A A A A Describe the function using Boolean expressions Draw the truth table and describe the function using SOP 9 Solution x AB BCC AB B C AB B C ABBC BC ABBC BC AB B C B C AB BBBCCBCC ABBC ABC B ABC Approach : Boolean simplification Find Truth Table Approach 2: Construct TT Find POS (De Morgan) (XOR expansion) (De Morgan) (De Morgan) (expansion) (grouping, expansion) (cancellation) POS: x ABC Gray Code Gray Code ( Reflected binary code RBC ) widely used in digital communications one of the most important codes. a non-weighted code, minimum change codes. https://testbook.com/blog/conversion-from-gray-code-to-binary-code-and-vice-versa/ 2

Karnaugh map grouping Rule of K-map:. No zeros allowed. 2. No diagonals. (group may be horizontal or vertical) 3. Only power of 2 number of cells in each group. 4. Groups should be as large as possible. 5. Every one must be in at least one group. 6. Overlapping allowed. 7. Wrap around allowed. (The leftmost cell in a row may be grouped with the rightmost cell and the top cell in a column may be grouped with the bottom cell. ) 8. Fewest number of groups possible. 3 K-map drawn on a torus, and in a plane. The dot-marked cells are adjacent. https://en.wikipedia.org/wiki/karnaugh_map 4 Examples of Karnaugh map grouping Don t Care Conditions 5 6

Example 3 A Karnaugh map for an output involving four inputs, w, x, y, and z, is given below : Question 4 Find out the simplified f(x) from the given K-map Derive the digital logic expression for this function. 7 8 Question 5 (Question ) Solution 5(a) Simplify the Boolean expression of the circuit Change each NAND gate in the circuit to a NOR gate, and simplify the Boolean expression of the circuit M N Q x From truth table to K-map NQ M M N Q A B x 9 C 2

Solution 5(b) Question 6 M N Q x NQ M Simplify the following Boolean expressions using Karnaugh map. i) AB AB ii) BBC ABC AC x MN Q i) A/B AB AB A 2 22 Solution 6 ii) A/BC Example 7 A K-map for an output for four inputs, A, B, C, and D is given by : Which of the following is a possible expression for the output? Direct using K-map, we have Y CD ABD BCD BCD Ans : A 23 24

Example 8 A K-map for an output for four inputs, A, B, C, and D is given by : Which of the following is a possible expression for the output? Example 8 Re-group and we have Direct using K-map, we have Y AB AD BD Y AD BD AB Ans : A 25 26 Example 9 Which one of the following Boolean expressions correctly represents this truth table? Kmap Example Given that A B, which of the following expressions are equivalent? Given that A B A =, B = or A =, B = Put these value to check the result Y AB BC Ans : A Ans : A 27 28

Sequential Logic Type of Flip Flop : RS, JK, D, T D flip-flop Gate Timing difference timing for difference kind of gate, cost dependence Q(t) Sequential TIME http://www.electronics-tutorials.ws/sequential/seq_4.html http://www.rfcafe.com/references/electrical/flip-flop-table.htm 29 D Q(t+) () Setup Time = t2-t (2) Propagation delay = t3-t2 (3) Hold time = t4-t2 What is the difference between Combinational and Sequential Circuit? Sequential factor - TIME CLK - END - 3