On the Performance of SC-MMSE-FD Equalization for Fixed-Point Implementations

On the Performance of SC-MMSE-FD Equalization for Fixed-Point Implementations ISTC 2014, Bremen, Tamal Bose and Friedrich K. Jondral KIT Universität des Landes Baden-Württemberg und nationales Forschungszentrum in der Helmholtz-Gemeinschaft www.kit.edu

Outline Motivation System Model Fixed-Point Study Basics, Notation Quantization Clipping Implementation and Evaluation Conclusion 2

Motivation Designing the physical layer of a robust, high data rate waveform for mobile use I SC-MMSE-FD Turbo Equalization Target platform: GPP/FPGA-based SDR I PHY implementation on a Xilinx Spartan-6 FPGA How should the signals within the SC-MMSE-FD equalizer be represented in Fixed-Point? I Fixed-Point Study 3

Outline Motivation System Model Fixed-Point Study Basics, Notation Quantization Clipping Implementation and Evaluation Conclusion 4

Transmitter and Receiver Single-carrier block transmission Frequency selective channel BICM transmitter with linear M -ary modulation scheme Due to frequency domain equalization Cyclic Prefix (CP) I Received symbols in vector/matrix notation after CP removal r = Hs + n CNs Transmitted symbols: s S Ns (QPSK, 8-PSK, 16-QAM) Circulant channel matrix: H CNs Ns Noise: n CNs, where nk CN 0, σ02, uncorrelated I SNR = 10 log(σ02 log2 (M )) db, given E{ sk 2 } = 1 5

SC-MMSE-FD Equalization 1/3 Received Symbols Equalized Symbols SoftDemapping To/From SISO Decoder Estimated Symbols SoftMapping Frequency domain (FD) processing MMSE-based equalization approach [Tue02] Soft interference cancellation (SC) [Wan99] 6

SC-MMSE-FD Equalization 2/3 Equalized symbols are given by [Kan07] CNs z = υs + BΨ(Fr ΞFs ) Substitutions: 2π i N lj F(l, j) = e B= s, 0 l, j Ns 1, i = 1 Ns 1 FH Ξ = FHB ϕ = Ns 1 s H s Ψ = ΞH (1 ϕ) ΞΞH + σ02 I 1 υ = Ns 1 trace(ψξ). 7

SC-MMSE-FD Equalization 3/3 Equivalent AWGN channel model zk υsk + wk where wk is CN (0, υ 2 (ϕ 1) + υ) distributed. I Soft-Demapping can be simplified I Equalizer performance can be analyzed quite easily 8

Outline Motivation System Model Fixed-Point Study Basics, Notation Quantization Clipping Implementation and Evaluation Conclusion 9

Basics, Notation 1/2 Due to fixed-point arithmetics, fixed-point representations are required for all symbols within the SC-MMSE-FD equalizer Quantization + Clipping [Rab75] Quantization Clipping (+ Quantization) I How have the fixed-point representations been chosen, to provide a certain equalization performance? Only resource-demanding symbols are analyzed FFT is performed with negligible fixed-point related issues 10

Basics, Notation 2/2 A fixed-point representation has a length of N bits This (word) length consists of n fractional bits, 1 sign bit and m integer bits separated by a virtual point N N =1+m+n z } { ± {z }. {z } m n Notation for signed representation: Fix N n I Resolution: = 2 n I Max/Min value: 2N n 1 2 n, 2N n 1 All operations are performed using Two s complement Dynamic range of the representation DR = 20 log 2N 6.02 N 11

Quantization 1/3 Performance of the fixed-point SC-MMSE-FD equalizer can be simulated I time- and resource-demanding Approach: Using an analytical quantization model [Rab75] [x]q = x + q x R Quantization error q U 0, 2 /12, uncorrelated I Rounding (to nearest neighbor) is assumed I The error variance only depends on the resolution and hence on the number of fractional bits n 12

Quantization 2/3 Idea: If the equalization performance can be evaluated with the equivalent channel model, why shouldn t the quantization error? Applying the quantization model to the equ. AWGN channel model Var {[zk ]Q } =Var {zk } + (α + υ 2 )σs 2 + ασs 2 + σs 20 2 2 2 + β(σr2 + σr + σr 0 + σr00 ) + σz2 0 + σz20 + σz2, Due to quantization where α = Ns 1 trace ΨΞΞH ΨH, β = Ns 1 trace ΨΨH I Quantized AWGN channel model 13

Quantization 3/3 EXIT-Chart [Bri99] Floating-Point (64-bit) Fixed-Point (Simulated) Quantized AWGN channel model 1 2 fractional bits SNR=7 db 0.8 0.6 1 fractional bit SNR=0 db 0.4 1 fractional bit 0.2 0 SNR=-3 db 0 0.2 0.4 0.6 0.8 1 I Quantized AWGN channel model allows a good estimate of the equalizer s performance 14

Clipping 1/3 High amplitudes are mapped to the Min/Max value of the FP rep. Since most symbols are continuously distributed, a clipping probability has to be specified Pcl = P { x c} I Full knowledge of the distribution required to determine c Approach: Using Chebyshev s inequality s c E {x2 } P { x c} I c is treated as an upper bound 15

Clipping 2/3 1 Simulated (Histogram) CCDF 0.8 0.6 Exact clipping value 0.4 Clipping value (Chebyshev) Clipping value (fixed-point) 0.2 0 0 50 100 150 200 Magnitude of real part 250 300 Finally, the required number of integer bits is given by m = dlog2 (c)e I Exact clipping value is (perhaps) overestimated 16

Clipping 3/3 The expectation can be calculated for each symbol in the SC-MMSE-FD equalizer (cf. paper) Assumptions: FFT (approximately) satisfies the central limit theorem; E{ hl 2 } = 1; hl CN (0, 1) Clipping probability of Pcl = 0.1 allows near-optimum performance 1 0.8 Pcl=0.25 Pcl=0.1 0.6 Floating-Point (64-bit) Fixed-Point (Simulated) 0.2 0 17 drop-off Pcl=0.5 0.4 0 0.2 0.4 0.6 0.8 1

Outline Motivation System Model Fixed-Point Study Basics, Notation Quantization Clipping Implementation and Evaluation Conclusion 18

System configuration Modulation scheme: 16-QAM SNR range: -2 db to 12 db Block length: 1024 symbols Channel: hl CN (0, 1), E{ hl 2 } = 1, 10 coefficients The number of fractional bits is chosen uniformly throughout the entire equalizer The clipping probability is set to Pcl = 0.1 19

Fixed-Point representation Representations can be determined without any simulation 20 Symbol n m N DR [db] r 3 2 6 36.12 Fix 6 3 R 3 7 11 66.23 Fix 11 3 Notation s 3 1 5 30.10 Fix 5 3 S 3 7 11 66.23 Fix 11 3 R0 3 7 11 66.23 Fix 11 3 R00 3 7 11 66.23 Fix 11 3 Z0 3 10 14 84.29 Fix 14 3 z0 3 5 9 54.19 Fix 9 3 s 0 3 8 12 72.25 Fix 12 3 z 3 8 12 72.25 Fix 12 3

Evaluation 1/3 The Fixed-Point representations are evaluated with Xilinx s System Generator for DSP Model-based design in Simulink Proprietary FFT IP-core (Pipelined, streaming I/O architecture) Model is synthesized for different SDR-embedded FPGAs Xilinx Kintex-7 (USRP X310) Xilinx Spartan-6 (USRP B210) Xilinx Virtex-6 (Nutaq µsdr420) 21

Evaluation 2/3 Top-level model in Simulink double double double double double double double double double In In In In In In In In In Fix_7_4 Fix_7_4 Fix_6_4 Fix_6_4 Fix_12_4 Fix_12_4 Fix_12_4 Fix_12_4 Fix_32_16 System Generator r_re r_im s_hat_re z_re Fix_13_4 Out double s_hat_im Phi_re Phi_im Xi_re z_im Fix_13_4 Out double Xi_im upsilon SC-MMSE-FD equalizer 22

Evaluation 3/3 Device utilization summary and performance Number of Kintex-7 Spartan-6 Virtex-6 Slice FFs 23299 (4%) 23922 (12%) 23762 (3%) Slice LUTs 21459 (8%) 24834 (26%) 24930 (7%) DSP48s 52 (3%) 61 (33%) 52 (6%) Flip-Flop (FF); Look-up-table (LUT) 1 0.9 0.8 0.7 0.6 0.5 0.45 0.4 0.35 0.3 0.25 23 SNR=12 db Floating-Point (64-bit) Fixed-Point (based on study) Fixed-Point (FPGA IDE) SNR=-2 db 0 0.2 0.4 0.6 0.8 1

Conclusion Fixed-Point Implementation of a SC-MMSE-FD equalizer has been studied Models were derived to determine representations for all symbols within the equalizer I No fixed-point simulations are required The accuracy of the models was verified using simulated Fixed-Point implementations Furthermore, the equalizer was implemented in an FPGA IDE I Device utilization of state-of-the-art FPGAs is less than 8% 24

. Thank you for your attention! Questions? [Tue02] M. Tu chler, R. Koetter, and A. Singer, Turbo equalization: Principles and new results, IEEE Trans. Commun., vol. 50, no. 5, pp. 754-767, May 2002. [Wan99] X. Wang and H.V. Poor, Iterative (turbo) soft interference cancellation and decoding for coded CDMA, IEEE Trans. Commun., vol. 47, no. 7, pp. 1046-1061, July 1999. [Kan07] K. Kansanen and T. Matsumoto, An analytical method for MMSE MIMO turbo equalizer EXIT chart computation, IEEE Trans. Wireless Commun., vol. 6, no. 1, pp. 59-63, Jan. 2007. [Rab75] L.R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing, Prentice Hall, June 1975. [Bri99] 25 S. ten Brink, Convergence of iterative decoding, Electronics Letters, vol. 35, no. 10, pp. 806-808, May 1999.