CMOS Analog Circuit Design Page 3.-1 CHAPTER 3 - CMOS MODELS Chapter Outline 3.1 MOS Structure and Operation 3.2 Large signal MOS models suitable for hand calculations 3.3 Extensions of the large signal MOS model 3.4 Capacitances of the MOSFET 3.5 Small Signal MOS models 3.6 Temperature and noise models for MOS transistors 3.7 BJT models 3.8 SPICE level 2 model 3.9 Models for simulation of MOS circuits 3.1 Extraction of a large signal model for hand calculations from the BSIM3 model 3.11 Summary Perspective CMOS Technology and Fabrication Analog Integrated Circuit Design CMOS Transistor and Passive Component Modeling Fig.3.-1 CMOS Analog Circuit Design Page 3.-2 Philosophy for Models Suitable for Analog Design The model required for analog design with CMOS technology is one that leads to understanding and insight as distinguished from accuracy. Technology Understanding and Usage Updating Model Thinking Model Simple, ±1% to ±5% accuracy Updating Technology Comparison of simulation with expectations Design Decisions- "What can I change to accomplish...?" Expectations "Ballpark" Computer Simulation Extraction of Simple Model Parameters from Computer Models Refined and optimized design Fig.3.-2 This chapter is devoted to the simple model suitable for design not using simulation.
CMOS Analog Circuit Design Page 3.-3 Categorization of Electrical Models Time Dependence Time Independent Time Dependent Linearity Linear Small-signal, midband R in, A v, R out (.TF) Small-signal frequency response - poles and zeros (.AC) Nonlinear DC operating point i D = f(v D,v G,v S,v B ) (.OP) Large-signal transient response - Slew rate (.TRAN) Based on the simulation capabilities of SPICE. CMOS Analog Circuit Design Page 3.1-1 3.1 MOS STRUCTURE AND OPERATION Metal-Oxide-Semiconductor Structure Bulk/Substrate Source Gate Drain Thin Oxide (1-1nm Polysilicon 1Å-1Å) p+ n+ n+ p- substrate Heavily Doped p Lightly Doped p Intrinsic Doping Lightly Doped n Heavily Doped n Fig.3.1-1 Terminals: Bulk - Used to make an ohmic contact to the substrate Gate - The gate voltage is applied in such a manner as to invert the doping of the material directly beneath the gate to form a channel between the source and drain. Source - Source of the carriers flowing in the channel Drain - Collects the carriers flowing in the channel Metal
CMOS Analog Circuit Design Page 3.1-2 Formation of the Channel for an Enhancement MOS Transistor Subthreshold (V G <V T ) V B = p+ p- substrate Threshold (V G =V T ) V B = p+ p- substrate p+ V S = V G < V T V D = ;; n + Polysilicon Depletion Region V S = V G =V T V D = Polysilicon ;; n+ ;;; n+ Inverted Region ;;; Polysilicon ;;; n + Strong Threshold (V G >V T ) V B = V S = V G >V T V D = n+ n+ p- substrate Inverted Region Fig.3.1-2 CMOS Analog Circuit Design Page 3.1-3 Transconductance Characteristics of an Enhancement NMOS Transistor when V DS =.1V V GS V T : V B = p+ p- substrate V GS =2V T : V B = p+ V S = v G =V T V D =.1V i D Polysilicon n+ n+ ;; ;;; Depletion Region VS = V G = 2V T V D =.1V i D i D Polysilicon ;; n+ ;;; n+ ;;;; i D V T 2V T 3V T v GS p- substrate V GS =3V T : V B = Inverted Region ;;; Polysilicon V S = V G = 3V T V D =.1V i D V T 2V T 3V T v GS p+ n+ n+ p- substrate Inverted Region V T 2V T 3V T v GS Fig.3.1-3
CMOS Analog Circuit Design Page 3.1-4 Output Characteristics of the Enhancement NMOS Transistor for V GS = 2V T V DS =: p+ p- substrate V DS =.5V T : V B = V B = V S = p+ v G =2V T Polysilicon VD = V i D n+ n+ ;; ;;; Inverted Region V DS =V T : V B = V S ;;; = V G = 2V T V D =V T i D Polysilicon i D V S = V G = 2V T V D =.5V T i D i D Polysilicon ;; n+ ;;;; ;;; n+ p- substrate Channel current p+ p- substrate n+ n+ A depletion region forms between the drain and channel i D V GS = 2V T v DS.5V T V T V GS = 2V T v DS.5V T V T V GS = 2V T v DS.5V T V T Fig.3.1-4 CMOS Analog Circuit Design Page 3.1-5 Output Characteristics of the Enhanced NMOS when v DS = 2V T V GS =V T : p+ p- substrate V GS =2V T : V B = V B = V S = p+ p- substrate v G =V T Polysilicon V D = 2V T i D n+ n+ ;; ;;; V GS =3V T : V B = V S ;;; = V G = 3V T V D = 2V T i D Polysilicon p+ p- substrate n+ n+ Further increase in V G will cause the FET to become active i D V S = V G = 2V T V D = 2V T i D i D Polysilicon ;;;;; ;;; n+ n+ i D V T V T V T V GS =V T v DS 2V T 3V T V GS =2V T v DS 2V T 3V T V GS =3V T v DS 2V T 3V T Fig.3.1-5
CMOS Analog Circuit Design Page 3.1-6 Output Characteristics of an Enhancement NMOS Transistor 2 VGS = 3. 15 id(µa) 1 VGS = 2.5 SPICE Input File: 5 Output Characteristics for NMOS M1 6 1 MOS1 w=5u l=1.u VGS1 1 1. M2 6 2 MOS1 w=5u l=1.u VGS2 2 1.5 M3 6 3 MOS1 w=5u l=1.u VGS3 3 2. M4 6 4 MOS1 w=5u l=1.u VGS4 4 2.5 VGS = 2. VGS = 1.5 VGS = 1. 1 2 3 4 5 vds (Volts) Fig. 3.1-6 M5 6 5 MOS1 w=5u l=1.u VGS5 5 3. VDS 6 5.model mos1 nmos (vto=.7 kp=11u gamma=.4 +lambda=.4 phi=.7).dc vds 5.2.print dc ID(M1), ID(M2), ID(M3), ID(M4), ID(M5).end CMOS Analog Circuit Design Page 3.1-7 Transconductance Characteristics of an Enhancement NMOS Transistor id(µa) 6 5 4 3 2 1 V DS = 4V V DS = 3V V DS = 5V V DS = 2V V DS = 1V SPICE Input File: Transconductance Characteristics for NMOS M1 1 6 MOS1 w=5u l=1.u VDS1 1 1. M2 2 6 MOS1 w=5u l=1.u VDS2 2 2. M3 3 6 MOS1 w=5u l=1.u VDS3 3 3. M4 4 6 MOS1 w=5u l=1.u VDS4 4 4. 1 2 3 4 5 v GS (Volts) Fig. 3.1-7 M5 5 6 MOS1 w=5u l=1.u VDS5 5 5. VGS 6 5.model mos1 nmos (vto=.7 kp=11u gamma=.4 lambda=.4 phi=.7).dc vgs 5.2.print dc ID(M1), ID(M2), ID(M3), ID(M4), ID(M5).probe.end
CMOS Analog Circuit Design Page 3.2-1 3.2 - LARGE SIGNAL MOSFET MODEL SUITABLE FOR HAND CALCULATION Large Signal Model Derivation Derivation- 1.) Let the charge per unit area in the channel inversion layer be Q I (y) = -C ox [v GS - v(y) - V T ] (coulombs/cm2) 2.) Define sheet conductivity of the inversion layer per square as cm2 coulombs σ S = µ o Q I (y) V s cm 2 = amps volt = 1 Ω/sq. 3.) Ohm's Law for current in a sheet is J S = i D W = -σ dv SE y = -σ S dy dv = -i D σ S W dy = 4.) Integrating along the channel for to L gives L v DS v DS i D dy = - Wµ o Q I (y)dv = Wµ o C ox [v GS -v(y)-v T ] dv 5.) Evaluating the limits gives v DS i D = Wµ oc ox L (v GS -V T )v(y) - v 2(y) 2 n + v(y) n + dy p Source Drain - y y y+dy L -i D dy µ o Q I (y)w i D dy = -Wµ o Q I (y)dv i D = Wµ oc ox L (v GS -V T )v DS - v DS 2 2 + v GS - i D - + vds CMOS Analog Circuit Design Page 3.2-2 Saturation Voltage - V DS (sat) Interpretation of the large signal model: i D v DS = v GS - V T Active Region Saturation Region Increasing values of v GS The saturation voltage for MOSFETs is the value of drain-source voltage at the peak of the inverted parabolas. di D dv = µ o C ox W v DS DS L [(v GS -V T ) - v DS ] = v DS (sat) = v GS - V T Useful definitions: µ o C ox W L = K W L = β v DS Cutoff Saturation Active v DS = v GS - V T v GS V T Fig. 3.2-4
CMOS Analog Circuit Design Page 3.2-3 The Simple Large Signal MOSFET Model Regions of Operation of the MOS Transistor: 1.) Cutoff Region: i D =, v GS - V T < (Ignores subthreshold currents) 2.) Active Region i D = µ o C oxw 2L [ 2(v GS - V T ) - v DS ] v DS, < v DS < v GS - V T 3.) Saturation Region µ o C ox W i D = 2L ( v GS - V T 2 ), < v GS - V T < v DS Normalized Output Characteristics of the MOSFET: i D /I D 1..75.5 Active Region v DS = v GS - V T Saturation Region Channel modulation effects.25 Cutoff Region.5 1. 1.5 2. 2.5 v GS -V T V GS - V T = 1. v GS -V T =.867 V GS - V T v GS -V T =.77 V GS - V T v GS -V T =.5 V GS - V T v GS -V T = V GS - V T v DS V GS - V T CMOS Analog Circuit Design Page 3.2-4 Illustration of the Need to Account for the Influence of v DS on the Simple Sah Model Compare the Simple Sah model to SPICE level 2: 25µA 2µA 15µA i D 1µA 5µA 2 K' = 44.8µA/V k =, v (sat) DS = 1.V 2 K' = 44.8µA/V k=.5, v (sat) DS = 1.V SPICE Level 2 2 K' = 29.6µA/V k =, v (sat) DS = 1.V µa.2.4.6.8 1 v DS (volts) V GS = 2.V, W/L = 1µm/1µm, and no mobility effects.
CMOS Analog Circuit Design Page 3.2-5 Modification of the Previous Model to Include the Effects of v DS on V T From the previous derivation: L v DS v DS i D dy = - Wµ o Q I (y)dv = Wµ o C ox [v GS - v(y) -V T ]dv Assume that the threshold voltage varies across the channel in the following way: V T (y) = V T + kv(y) where V T is the value of the threshold voltage at the source end of the channel and k is a constant. Integrating the above gives, i D = Wµ oc ox L (v GS -V T )v(y) - (1+k) v v 2(y) DS 2 or i D = Wµ oc ox L (v GS -V T )v DS - (1+k) v2 DS 2 To find v DS (sat), set the derivative of i D with respect to v DS equal to zero and solve for v DS = v DS (sat), v DS (sat) = v GS - V T 1 + k Therefore, in the saturation region, the drain current is i D = Wµ oc ox 2(1+k)L (v GS - V T ) 2 Note that on the previous slide that for k =.5 and K = 44.8µA/V 2, excellent correlation is achieved with SPICE 2. CMOS Analog Circuit Design Page 3.2-6 Influence of V DS on the Output Characteristics Channel modulation effect: As the value of v DS increases, it causes the effective L to decrease which causes the current to increase. Illustration: V G > V T VD > V DS (sat) B p+ S Depletion Polysilicon Region ;;;;;;; n+ n+ L eff p- substrate X d Fig.3.2-5 Note that L eff = L - X d Therefore the model in saturation becomes, i D = K W 2L (v eff GS -V T ) 2 di D dv = - K W DS 2L 2 (v GS - V T ) dl 2 eff eff dv = i D dx d DS L eff dv λi DS D Therefore, a good approximation to the influence of v DS on i D is λ = dx d /dv DS L eff i D i D (v DS =) + di D dv DS v DS = i D (v DS =)(1 + λv DS ) = K W 2L (v GS -V T )2 (1+λv DS )
CMOS Analog Circuit Design Page 3.2-7 Channel Length Modulation Parameter, λ Assume the MOS is transistor is saturated- i D = µc oxw 2L (v GS - V T ) 2 (1 + λv DS ) Define i D () = i D when v DS = V. Now, i D () = µc oxw 2L (v GS - V T ) 2 i D = i D ()[1 + λv DS ] = i D () + λi D () v DS Matching with y = mx + b gives Note that the value of λ varies with channel length, L. The data below is from a.25µm CMOS technology. Channel Length Modulation (V-1).6.5.4.3.2.1 NMOS PMOS.5 1 1.5 2 2.5 Channel Length (microns) Fig. 3.2-7A -1 λ i D3 () i D2 () i D1 () i D V GS3 V GS2 V GS1 v DS CMOS Analog Circuit Design Page 3.2-8 Influence of the Bulk Voltage on the Large Signal MOSFET Model Illustration of the influence of the bulk: V SB = V: Bulk V SB =V - + Source Gate V GS >V T Poly Drain V DS > p + n + n + p - Substrate/Bulk V SB1 >V: - V SB1 + Gate V GS >V T Drain V DS > Bulk Source Poly p + n + n + p - Substrate/Bulk V SB2 > V SB1 : - V SB2 + Gate V GS >V T Drain V DS > Bulk Source Poly p + n + n + p - Substrate/Bulk
CMOS Analog Circuit Design Page 3.2-9 i D Decreasing values of bulk-source voltage V BS = v DS v GS - V T V T V T1 V T2 Influence of the Bulk Voltage on the Large Signal MOSFET Model - Continued Bulk-Source (v BS ) influence on the transconductance characteristicsv GS In general, the simple model incorporates the bulk effect into V T by the following empirically developed V T (v BS ) = V T + γ 2 φ f + v BS - γ 2 φ f CMOS Analog Circuit Design Page 3.2-1 Summary of the Simple Large Signal MOSFET Model N-channel reference convention: D i + D G + equation- - -- Non-saturationi D = Wµ oc ox S L (v GS - V T )v DS - v DS 2 2 (1 + λv DS ) Saturationi D = Wµ oc ox L (v GS - V T )v DS (sat) - v DS(sat)2 2 (1 + λv DS ) = Wµ oc ox 2L (v GS - V T ) 2 (1 + λv DS ) where: µ o = zero field mobility (cm 2 /volt sec) C ox = gate oxide capacitance per unit area (F/cm 2 ) λ= channel-length modulation parameter (volts -1 ) V T = V T + γ 2 φ f + v BS - 2 φ f V T = zero bias threshold voltage γ = bulk threshold parameter (volts-.5) 2 φ f = strong inversion surface potential (volts) For p-channel MOSFETs, use n-channel equations with p-channel parameters and invert current. v GS B + v BS v DS
CMOS Analog Circuit Design Page 3.2-11 MOSFET Constants and Parameters Constants for Silicon: Constant Symbol Constant Description Value Units V G k n i ε ε si ε ox Silicon bandgap (27 C) Boltzmann s constant Intrinsic carrier concentration (27 C) Permittivity of free space Permittivity of silicon Permittivity of SiO 2 1.25 1.381x1-23 1.45x1 1 8.854x1-14 11.7 ε 3.9 ε V J/K cm -3 f/cm F/cm F/cm Model Parameters for a Typical CMOS Bulk Process (.8 m CMOS n-well): Parameter Parameter Typical Parameter Value Symbol Description N-Channel P-Channel Units V T Threshold Voltage (V BS = ).7 ±.15.7 ±.15 V K Transconductance Parameter (in saturation) γ Bulk threshold parameter λ Channel length modulation parameter 2 φ F Surface potential at strong inversion 11. ± 1% 5. ± 1% µa/v 2.4.57 (V) 1/2.4 (L=1 µm).1 (L=2 µm).5 (L = 1 µm).1 (L = 2 µm).7.8 V (V) -1 CMOS Analog Circuit Design Page 3.2-12 Large Signal Model of the MOS Transistor Schematic: D All modeling so far has been focused on this dependent current source. G r G C GD i D C GS r D C BD v BD + - i BD v BS + - i BS C BS r B B where, r G, r S, r B, and r D are ohmic and contact resistances and v BD i BD = I s exp V - 1 t and C GB r S v BS i BS = I s exp V - 1 t S Fig. 3.2-1
CMOS Analog Circuit Design Page 3.3-1 3.3 EXTENSIONS OF THE LARGE SIGNAL MODEL TO SHORT-CHANNEL MOSFETS VELOCITY SATURATION MODEL Velocity Saturation The most important short-channel effect in MOSFETs is the velocity saturation of carriers in the channel. A plot of electron drift velocity versus electric field is shown below. Electron Drift Velocity (m/s) 15 5x14 2x14 14 5x13 1 5 1 6 1 7 Electric Field (V/m) Fig. 3.3-1 An expression for the electron drift velocity as a function of the electric field is, µ n E v d 1 + E/E c where v d = electron drift velocity (m/s) µ n = low-field mobility (.7m 2 /V s) E c = critical electrical field at which velocity saturation occurs CMOS Analog Circuit Design Page 3.3-2 Short-Channel Model Derivation As before, J D = J S = i D W = Q I (y)v d (y) i D = W Q I (y)v d (y) = WQ I (y)µ n E 1 + E/E i c D 1 + E E = WQ C I (y)µ n E Replacing E by dv/dy gives, i D 1 dv 1 + E C dy = WQ I (y)µ dv ndy Integrating along the channel gives, L i D 1 + 1 v dv DS E c dy dy = WQ I (y)µ n dv The result of this integration is, µ n C ox W i D = 2 1 + 1 v DS L [2(v GS - V T )v DS - v DS 2 K W ] = 2[1 + θv DS ] L [2(v GS - V T )v DS - v DS 2 ] E c L where θ = 1/LE c with dimensions of V -1. The saturation voltage has not changed so substituting for v DS by v GS -V T gives, K W i D = 2[1 + θ(v GS -V T )] L [ v GS - V T ]2 Note that the transistor will enter the saturation region for v DS <v GS - V T in the presence of velocity saturation but the above equation is still a reasonable estimate of the saturation current.
CMOS Analog Circuit Design Page 3.3-3 The Influence of Velocity Saturation on the Transconductance Characteristics The following plot was made for K = 11µA/V 2 and W/L = 1: id/w (µa/µm) 1 θ = θ =.2 8 θ =.4 6 θ =.6 4 θ =.8 θ = 1. 2.5 1 1.5 2 2.5 3 v GS (V) Fig. 3.3-2 Note as the velocity saturation effect becomes stronger, that the drain current-gate voltage relationship becomes linear. CMOS Analog Circuit Design Page 3.3-4 Circuit Model for Velocity Saturation A simple circuit model to include the influence of velocity saturation is the following: G + v GS D + v GS '- i D R SX We know that i D = K W 2L (v GS -V T )2 and v GS = v GS + i D R SX or v GS = v GS - i D R XS Substituting v GS into the current relationship gives, i D = K W 2L (v GS - i D R SX -V T )2 Solving for i D results in, K W i D = 2 1 + K W L R SX (v GS -V T ) L (v GS - V T )2 Comparing with the previous result, we see that θ = K W L R SX R SX = θl K W = 1 E c K W Fig. 3.3-3 - Therefore for K = 11µA/V 2, W = 1µm and E c = 1.5x1 6 V/m, we get R SX = 6.6kΩ. S
CMOS Analog Circuit Design Page 3.3-5 Output Characteristics of Short-Channel MOSFETs IBM, 1998, t ox = 3.5nm Drain Current (µa/µm) 8 7 6 5 4 3 2 1 PFET L eff =.11µm V GS =-1.8V V GS =-1.4V V GS =-1.V V GS =-.6V NFET L eff =.8µm V GS =1.8V V GS =1.4V V GS =1.V V GS =.6V -1.8-1.2 -.6..6 1.2 1.8 Drain Voltage (V) Fig. 3.3-4 Su, L., et.al., A High Performance Sub-.25µm CMOS Technology with Multiple Thresholds and Copper Interconnects, 1998 Symposium on VLSI Technology Digest of Technical Papers, pp. 18-19. CMOS Analog Circuit Design Page 3.3-6 The Influence Channel Length on Modeling An approximate plot of the n as a function of channel length is shown below where i D (v GS V T ) n 2 1 n 1 2 3 4 5 L L min Fig.3.3-45 To avoid submicron modeling problems (and design problems) use a channel length longer than the minimum channel length.
CMOS Analog Circuit Design Page 3.3-7 SUBTHRESHOLD MOSFET MODEL Subthreshold Operation Weak inversion operation occurs when the applied gate voltage is below V T and pertains to when the surface of the substrate beneath the gate is weakly inverted. V GS n+ n-channel n+ Diffusion Current p-substrate/well Fig. 3.3-5 Regions of operation according to the surface potential, φ S. φ S < φ F : Substrate not inverted φ F < φ S < 2φ F : Channel is weakly inverted (diffusion current) 2φ F < φ S : Strong inversion (drift current) Drift current versus diffusion current in a MOSFET: log i D Diffusion Current 1-6 Drift Current 1-12 V VT Fig. 3.3-6 GS CMOS Analog Circuit Design Page 3.3-8 Large-Signal Model for Subthreshold Model: i D = K W x L evgs/nvt (1 e -v DS/V t ) 1 + v DS V A where K x is dependent on process parameters and the bulk-source voltage n 1.5 3 and V t = kt q If v DS >, then i D = K W x L ev GS/nVt 1 + v DS V A Small-signal model: g m = di D dv GS Q = qi D nkt 1µA i D V GS =V T V GS <V T v DS 1V Fig. 3.3-7 g ds = di D dv DS Q I D V A
CMOS Analog Circuit Design Page 3.3-9 SUBSTRATE CURRENT FLOW IN MOSFETS Impact Ionization Impact Ionization: Occurs because high electric fields cause an impact which generates a hole-electron pair. The electrons flow out the drain and the holes flow into the substrate causing a substrate current flow. Illustration: B p+ p- substrate S V G > V T Polysilicon V D > V DS (sat) ; ;; A ;; n+ Free n+ Fixed electron ; Atom ;;; Free hole Fig. 3.3-8 Depletion Region CMOS Analog Circuit Design Page 3.3-1 Model of Substrate Current Flow Substrate current: i DB = K 1 (v DS v DS (sat))i D e -[K 2/(v DS -v DS (sat))] where K 1 and K 2 are process-dependent parameters (typical values are K 1 = 5V -1 and K 2 = 3V) Schematic model: D G i DB B S Fig.3.3-9 Small-signal model: g db = di DB I DB dv = K DB 2 V DS - V DS (sat) This conductance will limit the amount of output resistance available from high-output resistance current sinks/sources.
CMOS Analog Circuit Design Page 3.4-1 Desired Model 3.4 CAPACITANCES OF THE MOSFET D r D C GD C BD v BD + - Capacitances desired are: Gate-drain C GD Gate-source C GS G r G i D i BD v BS + - i BS r B B Bulk-drain C BD Bulk-source C BS Gate-bulk C GB C GS C BS C GB r S S Fig. 3.4-1 CMOS Analog Circuit Design Page 3.4-2 Types of Capacitance Physical Picture: SiO 2 Source Gate Drain C 1 C 2 C3 FOX C BS C 4 C BD FOX Bulk Fig.3.4-2 MOSFET Capacitances consist of: Depletion capacitance (C BS, C BD, C 4 ) Charge storage or parallel plate capacitance (C 1, C 2, C 3 and C 5 yet to be shown)
CMOS Analog Circuit Design Page 3.4-3 MOSFET Depletion Capacitors Polysilicon gate Model: CJ AS CJSW PS C BS = 1 - v MJ + BS PB 1 - v MJSW, v BS FC PB BS PB and CJ AS C BS = ( 1- FC 1+MJ 1 - (1+MJ)FC + MJ V BS PB ) CJSW PS + ( 1 - FC 1+MJSW 1 - (1+MJSW)FC + MJSW V BS PB, ) v BS > FC PB Source SiO 2 where v BS FC PB AS = area of the source PS = perimeter of the source CJSW = zero bias, bulk source sidewall capacitance MJSW = bulk-source sidewall grading coefficient For the bulk-drain depletion capacitance replace S by D in the above. E A D Bulk Drain bottom = ABCD Drain sidewall = ABFE + BCGF + DCGH + ADHE C BS FC PB H Drain F B PB G C v BS FC PB v BS Fig. 3.4-4 Fig. 3.4-3 CMOS Analog Circuit Design Page 3.4-4 Charge Storage (Parallel Plate) MOSFET Capacitances C 1, C 2, C 3 and C 4 Mask L Oxide encroachment LD Actual L (L eff ) Mask W Actual W (W eff ) Gate Source-gate overlap capacitance C GS (C 1 ) FOX Source Gate-Channel Capacitance (C 2 ) Gate Bulk Overlap capacitances: C 1 = C 3 = LD W eff C ox = CGSO W eff or CGDO W eff Channel capacitances: C 2 = gate-to-channel = C ox W eff (L-2LD) = C ox W eff L eff Drain-gate overlap capacitance C GD (C 3 ) FOX Drain Channel-Bulk Capacitance (C 4 ) Fig. 3.4-5 C 4 = voltage dependent channel-bulk/substrate depletion capacitance (LD.15 µm for LDD structures)
CMOS Analog Circuit Design Page 3.4-5 Charge Storage (Parallel Plate) MOSFET Capacitances C 5 View looking down the channel from source to drain Overlap Overlap Gate FOXC 5 Source/Drain C 5 FOX Bulk Fig. 3.4-6 C 5 = CGBO Capacitance values and coefficients based on an oxide thickness of 14 Å or C ox =24.7 1 4 F/m 2 : Type P-Channel N-Channel Units CGSO 22 1 12 22 1 12 F/m CGDO 22 1 12 22 1 12 F/m CGBO 7 1 12 7 1 12 F/m CJ 56 1 6 77 1 6 F/m 2 CJSW 35 1 12 38 1 12 F/m MJ.5.5 MJSW.35.38 CMOS Analog Circuit Design Page 3.4-6 Expressions for C GD, C GS and C GB Cutoff Region: C GB = C 2 + 2C 5 = C ox (W eff )(L eff ) + 2CGBO(L eff ) C GS = C 1 C ox (LD)(W eff ) = CGSO(W eff ) C GD = C 3 C ox (LD)(W eff ) = CGDO(W eff ) Saturation Region: C GB = 2C 5 = CGBO(L eff ) C GS = C 1 +(2/3)C 2 = C ox (LD+.67L eff )(W eff ) = CGSO(W eff ) +.67C ox (W eff )(L eff ) C GD = C 3 C ox (LD)(W eff ) = CGDO(W eff ) Active Region: C GB = 2C 5 = 2CGBO(L eff ) C GS = C 1 +.5C 2 = C ox (LD+.5L eff )(W eff ) = (CGSO +.5C ox L eff )(W eff ) C GD = C 3 +.5C 2 = C ox (LD+.5L eff )(W eff ) = (CGDO +.5C ox L eff )(W eff ) Cutoff V B = p+ p- substrate Saturated V B = p+ p- substrate Active V B = p+ p- substrate V S = V G < V T V D > C GS Polysilicon C GD n+ C GB n+ V S = V G >V T V D >V G -V T C GS Polysilicon CGD n+ n+ Inverted Region V S = C GS ;;; Polysilicon V G >V T V D <V G -V T C GD n+ n+ Inverted Region Fig. 3.4-7
CMOS Analog Circuit Design Page 3.4-7 Illustration of C GD, C GS and C GB Capacitance C 4 Large C 2 + 2C 5 C C GS 1 +.67C 2 C GS, C C GD 1 +.5C 2 v DS = constant C C GS, C GD C v 1, C GD BS = 3 2C C C GB 4 Small 5 v GS Off Saturation Non- Saturation V T v DS +V T Fig. 3.4-8 Comments on the variation of C BG in the cutoff region: 1 C BG = 1 C 2 + 1 + 2C 5 C 4 For v GS, C GB C 2 + 2C 5 (C 4 is large because of the thin inversion layer in weak inversion where V GS is slightly less than V T ) For v GS V T, C GB 2C 5 (C 4 is small because of the thicker inversion layer in strong inversion) CMOS Analog Circuit Design Page 3.5-1 3.5 SMALL SIGNAL MODELS FOR THE MOSFET Small-Signal Model for the Saturation Region The small-signal model is a linearization of the large signal model about a quiescent or operating point. Consider the large-signal MOSFET in the saturation region (v DS v GS V T ) : i W oc ox D = (v 2L GS - V T ) 2 (1 + λv DS ) The small-signal model is the linear dependence of i d on v gs, v bs, and v ds. Written as, i d g m v gs + g mbs v bs + g ds v ds where and g m di D dv GS Q = β(v GS -V T ) = 2βI D g ds di D dv DS Q = λi D 1 + λv λi DS D dι D di D g mbs = dv BS Q = dv dv GS GS dv = di D - BS dv dv T Q T dv = g m γ = ηg BS Q 2 2 φ F - V m BS
CMOS Analog Circuit Design Page 3.5-2 Small-Signal Model Continued Complete schematic model: D D G B G S S Simplified schematic model (g mbs =): B G + v gs - S B + v bs - g m v gs g mbs v bs r ds i d D + v ds - S Fig. 4.2-4 D G S Extremely important assumption: G D S G + v gs - S g m v gs r ds i d + D v ds - S Fig. 4.2-2 g m 1g mbs 1g ds CMOS Analog Circuit Design Page 3.5-3 Illustration of the Small-Signal Model Application Example of a Gate-Drain connected MOSFET- DC resistor: i AC Resistance DC resistance = v i = V I Q Useful for biasing creating current from voltage and vice versa I D DC Resistance V T V DS v Fig. 4-2-2B Small-Signal Load (AC resistance): G D S B G D S B G + v gs - S B + v bs - g m v gs g mbs v bs v ds 1 AC resistance (Drain connected to gate and V BS = ) = i = d g m + g 1 ds g m r ds i d + D v ds - S Fig. 3.5-4
CMOS Analog Circuit Design Page 3.5-4 Example Small-Signal Load Resistance Find the small signal resistance of the MOS diode shown using the parameters of Table 3.2-1. Assume that the W/L ratio is 1µm/1µm. Solution If we are going to include the bulk effect, we must first find the dc value of the bulk-source voltage. Unfortunately, we do not know the threshold voltage because the bulk-source voltage is unknown. The best approach is to ignore the bulk-source voltage, find the gate-source voltage and then iterate if necessary. V DD = 5V 1µA 2I V GS = β + V T = 2 1 11 1 +.7 = 1.126V Thus let us guess at a gate-source voltage of 1.3V (to account for the bulk effect) and calculate the resulting gate-source voltage. V T = V T + γ 2 φ F - (-3.7) - γ 2 φ F =.7 +.4.7+3.7 -.4.7 = 1.2V V GS = 1.63V Now refine our guess at V GS as 1.6V and repeat the above to get V T = 1.175V which gives V GS = 1.6V. Therefore, V BS = -3.4V. r ac Fig. 4.2-5 CMOS Analog Circuit Design Page 3.5-5 Example Continued The small signal model for this example is shown. The ac input resistance is found by, i ac = g ds v ac g m v gs g mbs v bs = g ds v ac + g m v s + g mbs v s = v ac (g m +g mbs +g ds ) G,D,B i d g m v gs g mbs v bs + r ds v ds = v gs - S v ac 1 r ac = i = ac g m +g mbs +g ds Now we must find the parameters which are, g m = 2βI D = 2 11 1 1 µs = 469µS, g ds =.4V -1 1µA = 4µS, and g mbs = 469µS.4 =.987 469µS = 46.33µS 2.7+3.4 Finally, 1 r ac = 6 469 + 46.33 + 4 = 1926Ω If we had used the previous approximations of g m 1g mbs 1g ds, then we could have simply let r ac 1 1 g = m 469 = 2132Ω Probably the most important result of this approximation is that we would not have to find V BS which took a lot of effort for little return. r ac i ac v ac Fig. 4.2-6
CMOS Analog Circuit Design Page 3.5-6 Small-Signal Model for the Active Region g m = di D dv GS Q = K WV DS K W L (1+λV DS ) L V DS g mbs = di D dv BS Q = 2L K Wγ V DS 2φ F - V BS g ds = di D dv DS Q = K W L ( V I D λ GS - V T - V DS )(1+λV DS ) + 1+λV K W DS L (V GS - V T - V DS ) CMOS Analog Circuit Design Page 3.5-7 Small Signal Model for the Subthreshold Region If v DS >, then i D = K W x L ev GS/nVt (1 + λv DS ) Small-signal model: g m = di D dv GS Q = qi D nkt g ds = di D dv DS Q I D V A
CMOS Analog Circuit Design Page 3.5-8 Small Signal Frequency Dependent Model G C gb + v gs - S C gd C gs g m v gs v bs + + r ds v ds g mbs v bs - - S C bs i d C bd D B Fig. 3.5-6 The depletion capacitors are found by evaluating the large signal capacitors at the DC operating point. The charge storage capacitors are constant for a specific region of operation. Gainbandwidth of the MOSFET: Assume V SB = and the MOSFET is in saturation, f T = 1 g m 2π C gs +C 1 g m gd 2π C gs Recalling that C gs 2 3 C ox WL and g m = µ o C W ox L (V GS -V T ) gives f T = 3 µ o 4π L 2 (V GS -V T ) CMOS Analog Circuit Design Page 3.6-1 3.6 TEMPERATURE AND NOISE MODELS FOR THE MOSFET TEMPERATURE MODELING OF THE MOSFET Large Signal Temperature Model Transconductance parameter: K (T) = K (T ) T T -1.5 (Exponent becomes +1.5 below 77 K) Threshold Voltage: V T (T) = V T (T ) + α(t-t ) + Typically α NMOS = -2mV/ C to 3mV/ C over the range of 2 K to 4 K (PMOS has a + sign) Example Find the value of I D for a NMOS transistor at 27 C and 1 C if V GS = 2V and W/L = 5µm/1µm if K (T ) = 11µA/V 2 and V T (T ) =.7V and T = 27 C and α NMOS = -2mV/ C. Solution At room temperature, the value of drain current is, I D (27 C) = 11µA/V2 5µm 2 1µm (2-.7) 2 = 465µA At T = 1 C (373 K), we get 373 K (1 C) = K (27 C) -1.5 3 = 11µA/V2.72 = 79.3µA/V 2 and V T (1 C) =.7 (.2)(73 C) =.554V I D (1 C) = 79.3µA/V2 5µm 2 1µm (2-.554) 2 = 415µA (Let V GS = 1.5V and see something interesting)
CMOS Analog Circuit Design Page 3.6-2 Experimental Verification of the MOSFET Temperature Dependence NMOS Threshold: 1.6 1.4 1.2 1 V T (V).8.6.4.2 Theory matched at 25 C 5 1 15 2 25 3 Temperature ( C) Fig. 3.6-1 Symbol Min. L NA tox α (cm-3) (A ) (mv/ C) O 6µm 2x116 1-3.5 5µm 1x116 65-2.5 4µm 2x116 5-2.3 2µm 3.3x116 275-1.8 CMOS Analog Circuit Design Page 3.6-3 Experimental Verification of the MOSFET Temperature Dependence PMOS Threshold: 1.6 1.4 1.2 1 V T (V).8.6.4.2 Theory matched at 25 C 5 1 15 2 25 3 Temperature ( C) Fig. 3.6-2 Symbol Min. L NA tox α (cm-3) (A ) (mv/ C) O 6µm 2x115 1 +3.5 5µm 2x115 65 +2.5 4µm 2x116 5 +2.3 2µm 1.1x116 275 +2.
CMOS Analog Circuit Design Page 3.6-4 Experimental Verification of the MOSFET Temperature Dependence NMOS K : 1 8 6 µ(t) (cm2/v s) 4 2 Theory matched at 25 C Data Symbol Min. L 6 µm 5 µm 4 µm 2 µm 5 1 15 2 25 3 Temperature ( C) Fig. 3.6-3 CMOS Analog Circuit Design Page 3.6-5 Experimental Verification of the MOSFET Temperature Dependence PMOS K : 1 8 6 µ(t) (cm2/v s) 4 2 Theory matched at 25 C Data Symbol Min. L 6 µm 5 µm 4 µm 2 µm 5 1 15 2 25 3 Temperature ( C) Fig. 3.6-4
CMOS Analog Circuit Design Page 3.6-6 Zero Temperature Coefficient (ZTC) Point for MOSFETs For a given value of gate-source voltage, the drain current of the MOSFET will be independent of temperature. Consider the following circuit: I D Assume that the transistor is saturated and that: µ = µ o T T -1.5 V and V o T (T) = V T (T o ) + α(t-t o ) GS Fig. 4.5-12 where α = -.23V/ C and T o = 27 C µ o C ox W I D (T) = 2L T T -1.5 [VGS V o T - α(t-t o )] 2 di D dt = -1.5µ o C ox 2T T o T -2.5 [VGS - V o T - α(t-t o )] 2 + αµ o C ox T T -1.5 [VGS - V o T - α(t-t o )] = V GS V T - α(t-t o ) = -4Tα 3 V GS (ZTC) = V T - αt o - ατ 3 Let K = 1µA/V 2, W/L = 5 and V T =.71V. At T = 27 C (3 K), V GS (ZTC) =.71 (-.23)(3 K) (.333)(-.23)(3 K) = 1.63V At T = 27 C (3 K), I D = (1µA/V 2 )(5/2)(1.63-.71) 2 = 21.2µA At T = 2 C (473 K), V GS (ZTC) =.71 (-.23)(3 K) (.333)(-.23)(473 K) = 1.76V CMOS Analog Circuit Design Page 3.6-7 Experimental Verification of the ZTC Point The data below is for a 5µm n-channel MOSFET with W/L = 5µm/1µm, N A = 1-16 cm -3, t ox = 65Å, u o C ox = 1µA/V 2, and V T =.71V. 1 8 V DS = 6V I D (µa) 6 4 2 C 3 C 275 C Zero TC point 2 25 C 25 C 1 C 15 C.6 1.2 1.8 2.4 3 V GS (V)
CMOS Analog Circuit Design Page 3.6-8 ZTC Point for PMOS The data below is for a 5µm p-channel MOSFET with W/L = 5µm/1µm, N D = 2x1-15 cm -3, and t ox = 65Å. 5 3 C 4 V DS = -6V I D (µa) 3 2 275 C V GS (ZTC) SAT -1.95V 1 15 C 25 C 1 C 25 C -.6-1.2-1.8-2.4-3. V GS (V) Zero temperature coefficient will occur for every MOSFET up to about 2 C. CMOS Analog Circuit Design Page 3.6-9 Bulk-Drain (Bulk-Source) Leakage Currents (V GS >V T ) Cross-section of a NMOS in a p-well: V G > V T VD > V DS (sat) B p+ S Depletion Polysilicon Region ;;;;;;; n+ n+ p-well n- substrate Fig.3.6-5
CMOS Analog Circuit Design Page 3.6-1 Bulk-Drain (Bulk-Source) Leakage Currents (V GS <V T ) Cross-section of a NMOS in a p-well: V G <V T VD > V DS (sat) B S p+ ;;; Polysilicon n+ ;; n+ Depletion Region p-well n- substrate Fig.3.6-6 CMOS Analog Circuit Design Page 3.6-11 Temperature Modeling of the PN Junction PN Junctions (Reverse-biased only): i D I s = qa Dppno L + D nnpo p L n qad L n2 i Differentiating with respect to temperature gives, di s dt = 3KT 3 T exp V Go V + qkt 3 V Go t KT 2 exp V Go V t TC F = di s I s dt = 3 T + 1 V Go T V t Example N = KT 3 exp V Go V t = 3I s T + I s T V Go V t Assume that the temperature is 3 Κ (room temperature) and calculate the reverse diode current change and the TC F for a 5 Κ increase. Solution The TC F can be calculated from the above expression as TC F =.1 +.155 =.165 Since the TC F is change per degree, the reverse current will increase by a factor of 1.165 for every degree Κ (or C) change in temperature. Multiplying by 1.165 five times gives an increase of approximately 2. This implies that the reverse saturation current will approximately double for every 5 C temperature increase. Experimentally, the reverse current doubles for every 8 C increase in temperature because the reverse current is in part leakage current.
CMOS Analog Circuit Design Page 3.6-12 Experimental Verification of the PN Junction Temperature Dependence Leakage Current (A) 1-5 1-6 2 C Data Symbol Min. L 1-7 25 C 6 µm 5 µm 4 µm 1-8 I R 2 µm 5µm L min 1 C 1-9 1V Theory 1-1 matched at 15 C Generation- 1-11 Diffusion Recombination Leakage Leakage 1-12 Dominant Dominant 1.8 2 2.2 2.4 2.6 2.8 1/T ( K-1) Fig. 3.6-7 Theory: I s (T) T 3 exp V G (T) kt CMOS Analog Circuit Design Page 3.6-13 Temperature Modeling of the PN Junction Continued PN Junctions (Forward biased v D constant): i D I s exp v D V t Differentiating this expression with respect to temperature and assuming that the diode voltage is a constant (v D = V D ) gives di D dt = i D di s I s dt - 1 V D T V i t D The fractional temperature coefficient for i D is 1 di D i D dt = 1 di s I s dt V D TV = 3 t T + V Go V D TV t If V D is assumed to be.6 volts, then the fractional temperature coefficient is equal to.1 + (.155.77) =.879. It can be seen that the forward diode current will double for approximately a 1 C increase in temperature. PN Junctions (Forward biased i D constant): v D = V t ln I D I s Differentiating with respect to temperature gives dv D dt = v D T V t 1 di s I s dt = v D T 3V t T V Go T = V Go v D T 3V t T Assuming that v D = V D =.6 V the temperature dependence of the forward diode voltage at room temperature is approximately 2.3 mv/ C.
CMOS Analog Circuit Design Page 3.6-14 MOSFET NOISE MOS Device Noise at Low Frequencies D D e N 2 D where i 2 n = G S B 8kTg m (1+η) 3 + KF I D G Noise Free MOSFET f S C ox L 2 f (amperes 2 ) f = bandwidth at a frequency, f S i n 2 B G * Noise Free MOSFET S B η = g mbs g m k = Boltzmann s constant KF = Flicker noise coefficient S = Slope factor of the 1/f noise CMOS Analog Circuit Design Page 3.6-15 Reflecting the MOSFET Noise to the Gate Dividing i n 2 by g m 2 gives i 2 n e 2 n = g 2 = 8kT(1+η) KF m 3g + m 2fC ox WL K f (volts2 ) KF It will be convenient to use B = 2C ox K for model simplification. i n 2 1/f noise Thermal noise log 1 (f)
CMOS Analog Circuit Design Page 3.6-16 MOS Experimental Noise Data W/L I D (µa) Noise Voltage at 1Hz (nv/ Hz ) Thermal Noise Voltage (nv/ Hz ) 25/25 9 36 4 25/25 5 36 35 25/25 2 36 25 1.2/1.2 9 1, 35 1.2/1.2 5 1, 2 1.2/1.2 2 1, 18.8/.8 9 7, 18.8/.8 5 6, 15.8/.8 2 5, 12 25/2 9 9 3 25/2 5 85 28 25/2 2 - - 25/1 9 1 38 25/1 5 85 33 25/1 2 1 3 25/.6 9 95 5 25/.6 5 75 42 25/.6 2 7 35 CMOS Analog Circuit Design Page 3.6-17 MOSFET Noise Model at High Frequencies At high frequencies, the source resistance can no longer be assumed to be small. Therefore, a noise current generator at the input results. MOSFET Noise Models: G C gd D v in C gs v gs g m v gs r ds in 2 i o 2 v in G S S Circuit 1: Frequency Dependent Noise Model e i 2 C gd D * ii 2 C gs v gs r ds i o 2 g m v gs S S Circuit 2: Input-referenced Noise Model
CMOS Analog Circuit Design Page 3.6-18 MOSFET Noise Model at High Frequencies Continued To find e i 2 and i i 2, we will perform the following calculations: e i 2 : Short-circuit the input and find i o 2 of both models and equate to get e i 2. Ckt. 1: i o 2 = i n 2 Ckt. 2: i o 2 = g m 2 e i 2 + (ωc gd ) 2 e i 2 i 2 n e 2 i = g 2 m + (ωc gd ) 2 i i 2 : Open-circuit the input and find i o 2 of both models and equate to get i i 2. Ckt. 1: i o 2 = i n 2 (1/C Ckt. 2: i 2 gs ) o = 2 g 2 m i 2 i (1/C ds ) + (1/C gs ) i 2 i + ω 2 (C gs +C ds ) 2 g 2 m ω 2 C 2 ω 2 C 2 i 2 n if C gd < C gs i 2 gs i = gs g 2 i 2 n m CMOS Analog Circuit Design Page 3.7-1 SEC. 3.7 BJT MODELS Bipolar Transistor Symbol and Sign Convention The bipolar junction transistor (BJT) is a three-terminal device whose symbol and sign convention is given below: C - i C v BC i B + + v B CE + v BE - - i E E npn C - i C v BC i B + + v B CE + v BE - - i E E Fig.3.7-1 We will see that the names of the terminals of the transistor are descriptive of their function. Emitter The emitter is the source of majority carriers that result in the gain mechanism of the BJT. These carriers which are emitted into the base are electrons for the npn transistor and holes for the pnp transistor. Base The base is a region which physically separates the emitter and collector and has an opposite doping (holes for the npn and electrons for the pnp BJTs). The word base comes from the way that the first transistors were constructed. The base supported the whole structure. Collector The collector serves to collect those carries injected from the emitter into the base and which reach the collector without recombination. pnp
CMOS Analog Circuit Design Page 3.7-2 Physical Aspects of an npn BJT A cross-section of an npn BJT is shown below: Depletion Region E B C ;;;;; n+ p n Depletion Region E A B ;; n+ p n C A' Fig.3.7-2 Depletion Region Depletion Region Comments: The emitter-base depeletion region is generally smaller in width because the doping level is higher and base-emitter junction is generally forward-biased. The next slide will examine the carrier concentrations see looking into the above A-A cross-section. CMOS Analog Circuit Design Page 3.7-3 LARGE SIGNAL MODEL Carrier Concentrations of the npn BJT The carrier concentrations (not to scale) for the npn BJT are shown below. A n ne p ne Depletion Region p ne () Carrier Concentration ; ; ; ; n p () p p (x) n p (x) N A ;; ;;; ;; n p (W B ) Depletion Region Emitter Base Collector x = x =W B Fig.3.7-3 Comments: The above carrier concentrations assume that the base-emitter junction is forward biased and the basecollector junction is reverse biased. The above carrier concentration will be used to derive the large signal model on the next slide. N A n nc p nc x A'
CMOS Analog Circuit Design Page 3.7-4 Derivation of the BJT Large Signal Model in the Foward Active Region 1.) Carrier concentrations in the base on the emitter side. The concentration of electrons in the base on the emitter side (x = ) is v BE n p () = n po exp V t The concentration of electrons in the base on the collector side (x = W B ) is v BC n p (W B ) = n po exp V because v t BC is negative and large. 2.) If the recombination of electrons in the base is small, then the minority-carrier concentrations, n p (x), are straight lines and shown on the previous page. From charge-neutrality requirements for the base, N A + n p (x) = p p (x) n p (x) p p (x) = N A 3.) The collector current is produced by minority-carrier electrons in the base diffusing in the direction of the concentration gradient and being swept across the collector-base depletion region by the field existing there. Therefore, the diffusion current density due to electrons in the base is dn p (x) J n = qd n d x where D n is the diffusion constant for electrons. From the previous page, the derivative is the slope of the concentration profile in the base which gives, n p () J n = -qd n W B CMOS Analog Circuit Design Page 3.7-5 Derivation of the BJT Large Signal Model in the Foward Active Region Continued 3.) Continued If the collector current is defined as positive flowing into the collector terminal, then n p () i C = qad n W = qad n n po v BE B W exp B V t where A is the cross-sectional area of the emitter. The desired result is v BE i C = I S exp V t where the saturation current, I S, is I S = qad n n po W B Since, n 2 i = n po N A, we can rewrite I S as I S = qad n n i 2 W B N = qad n n i 2 A Q B where Q B is the number of doping atoms in the base per unit area of the emitter.
CMOS Analog Circuit Design Page 3.7-6 Derivation of the Forward Current Gain of the BJT, β F 1.) The base current, i B, consists of two major components. These components are due to the recombination of holes and electrons in the base, i B1, and the injection of holes from the base into the emitter, i B2. It can be shown that, i B1 = 1 n po W B qa v BE 2 τ exp b V and i t B2 = qad p n 2 i v BE L p N exp D V t 2.) Therefore the total base current is 1 i B = i B1 + i B2 = n po W B qa 2 τ + qad p n 2 i v BE b L p N exp D V t 3.) Define the forward active current gain, β F, as β F = i C i B = qad n n po W B 1 n po W B qa 2 τ + qad p n 2 = i b L p N D 1 W 2 B 2τ b D + D p W B N A n D n L p N D Note that β F is increased by decreasing W B and increasing N D /N A. CMOS Analog Circuit Design Page 3.7-7 Derivation of the Current Gain from Emitter to Collector in the Forward Active Region 1.) Emitter to collector current gain is designated as, α F = i C i. E 2.) Since sum of all currents flowing into the transistor must be zero, we can write that i E = -(i C +i B ) = - i C + i C β = - i F C 1+ 1 β i C F α F α F = β F 1 + β F = where and 1 1 + 1 β F = 1 1 + W B 2 2τ b D + D p W B N α T γ A n D n L p N D 1 α T Base Transport factor 1 + W B 2 1 2τ b D n γ Emitter injection efficiency 1 1 + D p D n W B L p N A N D 1
CMOS Analog Circuit Design Page 3.7-8 Large Signal Model for the BJT in the Foward Active Region Large-signal model for a npn transistor: i B B + v BE - E β F i B i B = Is v exp BE β F Vt C E B + V BE (on) Assumes v BE is a - E constant and i B is determined externally β F i B Fig.3.7-4 C E Large-signal model for a pnp transistor: i B B + v BE β F i B - E i B = - Is exp v - BE β F Vt C E B - i B V BE (on) Assumes v BE is a + E constant and i B is determined externally β F i B Fig.3.7-5 C E CMOS Analog Circuit Design Page 3.7-9 COLLECTOR VOLTAGE INFLUENCE ON THE LARGE SIGNAL MODEL Base Width Dependence on the Collector-Emitter Voltage The large signal model so far has the collector current as a function of only the base-emitter voltage. However, there is a weak dependence of the collector current on the collector-emitter voltage that is developed here. Influence of the base-collector depletion region width: Emitter Carrier Concentration ;; ;; ;; n p () = n po exp Collector depletion region widens due to a change in v CE, V CE i C i C + i C W B Base v BE V t ;;; ;;; ;;; W B Initial Depletion Region x Collector Fig.3.7-6 Note that the change of the collector-emitter voltage causes the amount of charge in the base to change slightly influencing the collector current.
CMOS Analog Circuit Design Page 3.7-1 The Early Voltage of BJTs Previously we saw that, i C = qad n n i 2 v BE Q exp B V t Differentiation of i C with respect to v CE gives, di C dv = - qad n n i 2 CE Q 2 B exp V BE V t dq B dv CE = - I C Q B dq B dv CE For a uniform-base transistor, Q B = W B N A so that the derivative becomes di C dv = - I C dw B CE W B dv - I C dv CE CE V V A A = -W B dw B where V A is called the Early voltage. CMOS Analog Circuit Design Page 3.7-11 Illustration of the Early Voltage The output characteristics of an npn BJT: i C V BE4 V BE3 Modified large signal model becomes, i C = I S 1 + v CE v BE V exp A V t V A V BE2 V BE1 v CE Fig.3.7-7
CMOS Analog Circuit Design Page 3.7-12 SATURATION AND INVERSE ACTIVE REGIONS Regions of Operation of the BJT If we consider the transistor as back-to-back diodes, we can clearly see the four regions of operation. v BE Forward Active Region BE forward biased BC reverse biased Saturation Region BE forward biased BC forward biased C C Cutoff Region BE reverse biased BC reverse biased Inverse Active Region BE reverse biased BC forward biased v BC B E B E Fig.3.7-8 Note: While the back-to-back diode model is appropriate here, it is not a suitable model for the BJT in general because it does not model the current gain mechanism of the BJT. Essentially, the back-to-back diode model has a very wide base region and all the injected carriers from the emitter recombine in the base (β F = ). CMOS Analog Circuit Design Page 3.7-13 Saturation Region In the saturation region, both the base-emitter and base-collector pn junctions are forward biased. Consequently, there is injection of electrons into the base from both the emitter and collector. The carrier concentrations in saturation are: n ne p ne p ne () Carrier Concentration ;; ;; ;; ;; Electrons n p () p p (x) n p (x) n p1 (x) np2 (x) i C n p (W B ) ;; ;; Electrons ;; x W B Emitter Base Collector Fig.3.7-9 n nc p nc
CMOS Analog Circuit Design Page 3.7-14 Typical Output Characteristics for an npn BJT i C (ma) I B =.4mA 5 4.3mA Forward active region I B = Cutoff -8-6 -4-2 I B =.1mA.2mA Inverse active region.3ma 3 Saturation 2.4mA 1.2mA.1mA I B = V 1 2 3 4 CE (V) BV -.2 Cutoff CEO Saturation -.4 -.6 -.8 -.1 Fig.3.7-1 CMOS Analog Circuit Design Page 3.7-15 Large Signal Model in Saturation In saturation, both junctions are forward biased and the impedance levels looking into the emitter or collector is very low. Simplified model: B C B C V BE (on) V CE (sat) V BE (on) V CE (sat) E E npn where V BE (on).6 to.7v and V CE (sat).2v E pnp E Fig.3.7-11
CMOS Analog Circuit Design Page 3.7-16 The Ebers-Moll Large Signal Model Consider the saturation condition with both pn junctions forward biased. Ταβλε. The emitter injected current in the base resulting from n p1 (x) is, i EF = -I ES exp v BE V + 1 t where I ES is a constant called saturation current (no connection with I s ) Ταβλε. The collector injected current in the base resulting from n p2 (x) is, i CR = -I CS exp v BC V + 1 t where I CS is another constant called saturation current (again no connection with I s ) Ταβλε. The total collector current, i C, is equal to i CR plus the n amount of i EF that reaches the collector, p () i C = i CR + α F i EF = α F I ES exp v BE V + 1 I t CS exp v n p (x) i BC C V + 1 t n p1 (x) i np2 (x) CR Also, we can write, v BE v BC W B i E = i EF + α R i CR = I ES exp V + 1 +α t R I CS exp V + 1 Base t n p (W B ) i EF x Fig.3.7-11A where α R is the collector efficiency (as an emitter) and β R = α R 1-α R. These two equations are the Ebers-Moll equations for the BJT. CMOS Analog Circuit Design Page 3.7-17 The Ebers-Moll Equations Continued The reciprocity condition allows us to write, α F I EF = α R I CR = I S Substituting into the previous form of the Ebers-Moll equations gives, i C = I S exp v BE V + 1 I S t α exp v BC R V + 1 t and i E =- I S α exp v BE F V + 1 +I t S exp v BC V + 1 t These equations are valid for all four regions of operation of the BJT.
CMOS Analog Circuit Design Page 3.7-18 TRANSISTOR BREAKDOWN VOLTAGES Common-Base Transistor Breakdown Characteristics i C (ma) i C 1.5 1. I E =1.5mA I E =1.mA I E V CB I E =.5mA.5 I E = V CB (V) Fig.3.7-12 2 4 6 8 1 BV CBO As the collector-base voltage becomes large, the collector current can be written as, i C = -α F i E M where 1 M = -α F i E 1 - v CB n BV CBO CMOS Analog Circuit Design Page 3.7-19 Common-Emitter Transistor Breakdown Characteristics Assume that a constant base current, i B, is applied. Using the previous result gives i C = -α F i E M i E = i C -α F M i C = -(i E + i B ) i C 1 1- α F M = -i B i C = α F M 1-α F M i B where, M = 1 v CB n 1 - BV CBO Breakdown occurs when α F M = 1. Assuming that v CE v CB gives, α F BV CEO = 1 n 1 - BV CBO BV CEO BV = CBO 1-α F 1/n BV CBO β 1/n F Note that BV CEO is much less than BV CBO. For β F = 1 and n = 4, BV CEO.5BV CBO.
CMOS Analog Circuit Design Page 3.7-2 DEPENDENCE OF β F ON OPERATING CONDITIONS Transistor β F Dependence on Collector Current and Temperature Plot of β F as a function of i C : β F 4 3 2 1 Region I Region II Region III T=125 C T=25 C T=-55 C Region I: Low current region where β F decreases as i C decreases. Region II: Midcurrent region where β F is approximately constant. Region III: High current region where β F decreases as i C increases. i C.1µA 1µA 1µA 1µA 1mA 1mA Fig.3.7-13 β F dependence on temperature: The temperature coefficient of βf is, TC F = 1 dβf β F dτ +7ppm/ C (ppm = parts per million) CMOS Analog Circuit Design Page 3.7-21 Variation of Forward Beta with Collector Current Region II: v BE i C = I S exp V and i t B I S v BE β exp FM V t where β FM = the maximum value of β F. Region I: v BE v BE i C = I S exp V and i t BX = I SX exp mv due to recombination, m 2 t Ταβλε. β FL = i C i = I S v BE BX I exp SX V t 1-1 m I S i C [1-(1/m)] I SX I s for m = 2, β FL i C Region III: v BE i C = I SH exp 2V due to the high level injection and i t B I S v BE β exp FM V t β FH I SH I S β F exp - v BE 2V I SH 2 t I β 1 S FM i C
CMOS Analog Circuit Design Page 3.7-22 Illustration of the Dependence of β F on i C ln i ln β FH i C ln β FM ln β FL i B ln I s Fig.3.7-14 Region I Region II Region III v BE (linear scale) CMOS Analog Circuit Design Page 3.7-23 SMALL SIGNAL BJT MODEL BJT, Common-Emitter, Forward-Active Region Effect of a small-signal input voltage applied to a BJT. i C = I C + i c i B = I B + i b v i V BE V CC Emitter Carrier Concentration Emitter Depletion Q ; n p () = n po exp V BE +v be ; ; h Region V t Q e n p () = n po exp Vt ; V BE I C I C +i ; c W B Base ;;; ;;; ;;; Collector Depletion Region x Collector Fig.3.7-16 v i i b i c
CMOS Analog Circuit Design Page 3.7-24 Transconductance of the Small Signal BJT Model The small signal transconductance is defined as g m di C dv BE Q = i C v = i c BE v = i c be v i i c = g m v i The large signal model for i C is i C = I S exp v BE d V g t m = dv I BE S exp v BE V t Q S V exp V BE t V t = I C V t g m = I C V t Another way to develop the small signal transconductance V BE +v i V BE v i v i i C = I S exp V = I t S exp V exp t V = I t C exp V I t C 1 + v i V + 1 v i 2 1 v i 3 t 2 V + t 6 V + t But i C = I C + i c Ταβλε. v i I C v i I 2 C v i I 3 C i c I C V + t 2 V + t 6 V + t V v t i = g m v i CMOS Analog Circuit Design Page 3.7-25 INPUT AND OUTPUT RESISTANCE SMALL SIGNAL MODEL Input Resistance of the Small Signal BJT Model In the forward-active region, we can write that i B = i C β F Small changes in i B and i C can be related as i B = d i C di C β i C F The small signal current gain, β o, can be written as β o = i C i B = 1 = d i C di C β F i c i b Therefore, we define the small signal input resistance as r π v i i b = β o v i i c = β o g m r π = β o g m
CMOS Analog Circuit Design Page 3.7-26 Output Resistance of the Small Signal BJT Model In the forward-active region, we can write that the small signal output conductance, g o (r o = 1/g o ) is g o di C dv CE Q = i C v CE = i c v ce i c = g o v ce The large signal model for i C, including the influence of v CE, is i C = I S 1 + v CE V A exp v BE V t g o di C dv CE Q = I S 1 V A exp V BE V t I C V A r o = V A I C CMOS Analog Circuit Design Page 3.7-27 Simple Small Signal BJT Model Implementing the above relationships, i c = g m v i, i c = g o v ce, and v i = r π i b, into a schematic model gives, B C E B i b + + v i rπ g m v i ro v ce - - E E i c C B Fig. 3.7-17 Note that the small signal model is the same for either a npn or a pnp BJT. Example: Find the small signal input resistance, R in, the output resistance, R out, and the voltage gain of the common emitter BJT if the BJT is unloaded (R L = ), v out /v in, the dc collector current is 1mA, the Early voltage is 1V, and β ο at room temperature. C E G m = I C V = 1mA t 26mV = 1 26 mhos or Siemans R R out = r o = V A I C = 1V 1mA = 1kΩ in = r π = β o g m = 1 26 = 2.6kΩ v out v in = -g m r o = - 26mS 1kΩ = -26V/V