J. Hetthéssy, A. Barta, R. Bars: Dead beat cntrller design Nvember, 4 Dead-beat cntrller design In sampled data cntrl systems the cntrller is realised by an intelligent device, typically by a PLC (Prgrammable Lgic Cntrller). The tas f the PLC is t realise the cntrller algrithm and t handle the signals used fr peratin f the cntrller (filtering, A/D and D/A cnverters, signal cnditining interfaces). As the cntrller algrithm is realised by sftware, there is a pssibility t apply different special, mre sphisticated cntrl algrithms. One f these algrithms ensures the accurate settling f the utput signal during a finite, small number f the sampling perids. In the literature this algrithm is referred as the dead-beat cntrller algrithm. T understand the essence f the methd - fr sae f simplicity - we cnsider a stable plant withut dead time. The reference signal is a unit step. (Let us remar that the dead-beat cntrller can be designed fr unstable plants with dead time cnsidering a reference signal different f unit step as well, in a bit mre cmplex way). In the sequel a design prcedure is derived in three steps. This slutin satisfies the practical requirements as well. In the first step the cntrller is designed fr the fastest behaviur when the utput signal is settled in ne sampling step. It will be seen that with this design with typical sampling times the cntrl signal culd be extremely high, mrever in mst cases scillatins ccur between the sampling pints. In the secnd step the design is mdified t avid intersampling scillatins. It will be shwn that cancellatin f ers utside f the unit circle is the reasn fr scillatins. Zers f the plant pulse transfer functin are separated fr cancellable and nn-cancellable nes and nly the cancellable ers will appear in the cntrller algrithm. This mdificatin f the algrithm increases the settling time. If the cntrl signal is still higher than allwed, the slutin can be refined using a s-called design plynmial. In this case the settling time is increased further (but still remains finite). The design is executed in the peratr dmain. Interesting feature f the design methd is the fact that it remves undesirable time dmain prperties (scillatins, t high values f the cntrl signal) by cnsideratins dne in the peratr dmain. The basic tas is the design f a sampled data cntrller. r[] - e[] u[] u(t) C () D / A P(s) U() y(t) Y(s) y[] Y() A/ D Y P ( ) = U The hybrid (cntinuus-discrete) prblem is cnverted first t a discrete prblem. Pulse transfer functin P() f the plant is determined which cnsiders the D/A cnverter and hld element tgether with the plant transfer functin P(s). Sampling time T s has als t be given. Then design the cntrller C() and chec the clsed lp system perfrmance analysing the cntinuus signals nt nly in the sampling pints, but als between them. r[] e[] u[] y[] C () P ( ) - Speaing abut cntrllers given by their transfer functins let us analyse realisatin aspects. Be the pulse transfer functin f the cntrller: b + b + b + b C ( )= + a + a + a In rder t use the shift peratr - let us divide bth the numeratr and the denminatr by third pwer f. b + b + b + b C ( )= + a + a + a
J. Hetthéssy, A. Barta, R. Bars: Dead beat cntrller design Nvember, 4 As { u [ ]} { e [ ]} Z Z with crss-multiplicatin we get u [ ] + au [ ] + au [ ] + au [ ] = be [ ] + be [ ] + be [ ] + be [ ] r u [ ] = be [ ] + be [ ] + be [ ] + be [ ] au [ ] au [ ] au [ ] It is seen that the pulse transfer functin f the cntrller can be transfrmed simply t a recursive difference equatin. MATLAB functin dlsim calculates the utput f a discrete element n the basis f its difference equatin fr a given input signal. The abve interpretatin f pulse transfer functin C() means that the cntrller in a sampled data cntrl system is implemented by a recursive algrithm Returning t the design f the dead-beat cntrller let us cnsider the fllwing plant given by its transfer functin Ps () = ( + 5s)( + s) The sampling time is T s = sec.» Ts=;» s=p('s');» =p('',ts);» Ps=/((+5*s)*(+*s)) In rder t get an impressin abut the system let us calculate its unit step respnse.» step(ps) The pulse transfer functin f the plant tgether with the er rder hld is btained» P=cd(Ps,Ts) B ( ) ( +.948) P ( ) = =.9559 ( -.887) ( -.948) First design the dead-beat cntrller ensuring settling prcess during ne sampling perid. The cnditin fr this is that the resulting transfer functin f the clsed lp between the utput signal and the input signal (suppsed t be a sampled unit step) be a ne step shift, namely the shift peratr -.. CP ( ) ( ) T = = + CP ( ) ( ) Hence the cntrller pulse transfer functin is expressed as T = P ( )( T ( )) P ( ) Express P() as a rati f tw plynmials: B ( ) P ( ) = Then B ( ) The discrete transfer functin f the cntrller is calculated in Matlab by» T=/» C=T/(P*(-T))» C=minreal(C) ( -.887) ( -.948).45 ( +.948) ( -) The clsed lp system behaviur can be visualised by the step cmmand,
J. Hetthéssy, A. Barta, R. Bars: Dead beat cntrller design Nvember, 4» step(c*p/(+c*p)) The u cntrl signal is displayed:» step(c/(+c*p)) The system shws ne time step delay. Mre accurate behaviur can be investigated by a Simulin mdel. Clc t time u cntrl Scpe y utput C Ps Step Input LTI System Zer-Order Hld LTI SystemPs Scpe The reasn f the scillatins is the fact that the cntrller cntains the ers f the plant as its ples, and sme f these ples result scillatins in cntrl signal u[. (see the appendix at the end)..5.5 5 5-5 5 The ers f the plant (rts f B) ( ) appear in the cntrller as ples, B ( ) P ( ) has nly ne er, = -.948. Examine this in mre detail.» C=/(+.948)» step(c) This cmpnent causes the scillatin. Cnvert bac this ple t the cntinuus dmain. Since, s = ln / TS» p=lg(-.948) p = -. +.46i S = e st, Here we just emphasise that typically ples f negative real value cause the scillatins. Let us separate the cancellable and nn-cancellable ers f the prcess pulse transfer functin accrding t + B ( ) = B( B ) + where B cntains the cmpensable and B the nn cmpensable rts. If a er is nt cmpensated it will appear in the clsed lp transfer functin. Design a cntrller that des nt cmpensate the nn cmpensable rts. T =
J. Hetthéssy, A. Barta, R. Bars: Dead beat cntrller design Nvember, 4 where = +deg ( B B ), =. B () The cmpnent is necassary t get a realisable system (the degree f the denminatr is higher than the degree f the numeratr). Anther requriment is that the static gain is, that is B is nrmalied. + B + B ( ) = B( B ) () = ( B ) n. B () B () = +.948, +.948 = =.55 +.475 and.948 + = pb ()=.7 + [ ] and the MATLAB prgram» Bm =(+.948)» Bpn=P.*dcgain(Bm)» Bmn=Bm/dcgain(Bm)» T=Bmn/(^)» C=T/(P*(-T))»(C=minreal(C,.)) It is seen that there are n scillatins and the verexcitatin in the cntrl signal is als less than befre. The system became slwer, nw the utput signal reaches the steady state during tw sampling steps. As the maximum value f the cntrl signal is still t high, its value f abut 5 wuld exceed the pssibilities f a usual actuatr. S we have t find a mdificatin f the design which wuld decrease the value f the verexcitatin eeping the prperty f a finite settling time. Let us cmplete the cntrl algrithm with a design plynmial, which will lead the finite time settling prcess. Fr example chsing design plynmial + + F = + + = its smthing effect is shwn by its unit step respnse.» F=(^++)/(*^)» step(f) The cntrl equatin with the design plynmial: T = F and the cntrller algrithm: AF ( ) ( ) + B [ B F] Let us bserve that F()=, s the design plynmial des nt affect the er static errr.» T=F*Bmn/(^)» C=T/(P*(-T))» C=minreal(C) n The dead-beat cntrller can be designed als in cases when the plant cntains dead time. Let us suppse that the cntinuus dead time T d is a multiple integer f the sampling time T s. Be this rati d=t d /T s. B ( ) d P ( ) = n.5.5 4 6 8 5-5 4 6 8 4
J. Hetthéssy, A. Barta, R. Bars: Dead beat cntrller design Nvember, 4 Suppsing that the cntinuus plant is stable and the reference input is a unit step, the clsed lp transfer functin is written as: T = but nw the value f has t be increased by d steps. = + deg ( B ) + d Cnsequently the pen lp pulse transfer functin is CP ( ) ( ) =, d A + [ ] In the previus example a T d = sec dead time is added t the cntinuus prcess (d=). Calculate the cntrller and simulate the behaviur f the cntrl system. The cntrller:» Td=» d=td/ts» T=Bmn/(^(+d))» C=T/(P*(-T))» C=minreal(C) The delay can be simulated in Simulin with an added delay blc (Simulin >Cntinuus >Transprt Delay). Similarly t the previus discussin the design can be mdified with a design plynmial. Appendix: Let us analyse the cntur f a cnjugate cmplex pair with a given damping factr in the dmain. In the s dmain the cnstant ζ lines are straight lines s=σ+jω ging thrugh the rig where fr a given σ value ω = σ ς ζ st = e t. These cmplex s values are transfrmed t the dmain by relatinship s curves f heart shape. As a demnstratin be» sigma=:.:.6;» eta=.4;» Ts=;» =exp(ts*(-sigma+j*sqrt(-eta*eta)*sigma/eta));» plt(real(),imag(),real(),-imag()),grid; Thse rts f plynmial B() which belng t plynmial B are inside f the clsed curve (where the damping factr is higher than n the cntur). Thse rts f plynmial B() which belng t plynmial Bare n the cntur r utside f it. 5