High Speed Communication Circuits and Systems Lecture 4 Generalized Reflection Coefficient, Smith Chart, Integrated Passive Components Michael H. Perrott February 11, 2004 Copyright 2004 by Michael H. Perrott All rights reserved. 1
Determine Voltage and Current At Different Positions Z L Incident Wave V+e jwt e jkz E x y x I+e jwt e jkz H y z Z L Reflected Wave H y E x V-e jwt e -jkz z I-e jwt e -jkz L 0 Incident and reflected waves must be added together 2
Determine Voltage and Current At Different Positions Z L Incident Wave V+e jwt e jkz E x y x I+e jwt e jkz H y z Z L Reflected Wave H y E x V-e jwt e -jkz z I-e jwt e -jkz L 0 3
Define Generalized Reflection Coefficient Similarly: 4
A Closer Look at (z) Recall L is Im{Γ(z)} Note: Γ L Γ L Δ = 2kz We can view (z) as a complex number that rotates clockwise as z (distance from the load) increases 0 Γ(z) Γ L Γ L Re{Γ(z)} 5
Calculate V max and V min Across The Transmission Line We found that So that the max and min of V(z,t) are calculated as We can calculate this geometrically! 6
A Geometric View of 1 + (z) Im{1+Γ(z)} 1+Γ(z) Γ L Γ(z) 0 1 Re{1+Γ(z)} 7
Reflections Cause Amplitude to Vary Across Line Equation: Graphical representation: direction of travel t V + e jwt e jkz z λ 1 + Γ(z) max 1+Γ(z) 1+Γ(0) z 0 min 1+Γ(z) 8
Voltage Standing Wave Ratio (VSWR) Definition For passive load (and line) We can infer the magnitude of the reflection coefficient based on VSWR 9
Reflections Influence Impedance Across The Line From Slide 4 - Note: not a function of time! (only of distance from load) Alternatively - From Lecture 2: 10
Example: Z( /4) with Shorted Load λ/4 Z L y x Z(λ/4) z z Calculate reflection coefficient L 0 Calculate generalized reflection coefficient Calculate impedance 11
Generalize Relationship Between Z( /4) and Z(0) General formulation At load (z=0) At quarter wavelength away (z = /4) - Impedance is inverted! Shorts turn into opens Capacitors turn into inductors 12
Now Look At Z( ) (Impedance Close to Load) Impedance formula ( very small) - A useful approximation: - Recall from Lecture 2: Overall approximation: 13
Example: Look At Z( ) With Load Shorted Z L y x Z(Δ) z z Δ 0 Reflection coefficient: Resulting impedance looks inductive! 14
Example: Look At Z( ) With Load Open Z L y x Z(Δ) z z Δ 0 Reflection coefficient: Resulting impedance looks capacitive! 15
Consider an Ideal LC Tank Circuit Z in L C Calculate input impedance about resonance = 0 negligible 16
Transmission Line Version: Z( /4) with Shorted Load λ 0 /4 Z L y x Z(λ 0 /4) z z L As previously calculated 0 Impedance calculation Relate to frequency 17
Calculate Z( f) Step 1 λ 0 /4 Z L y x Z(λ 0 /4) z z L Wavelength as a function of f 0 Generalized reflection coefficient 18
Calculate Z( f) Step 2 λ 0 /4 Z L y x Z(λ 0 /4) z Impedance calculation z L 0 Recall - Looks like LC tank circuit (but more than one mode)! 19
Smith Chart Define normalized impedance Mapping from normalized impedance to is one-to-one - Consider working in coordinate system based on Key relationship between Z n and - Equate real and imaginary parts to get Smith Chart 20
Real Impedance in Coordinates (Equate Real Parts) Γ L =j Im{Γ L } Γ L =-1 Γ L =0 Γ L =1 0.2 0.5 1 2 5 Re{Γ L } Z n =0.5 Γ L =-j 21
Imag. Impedance in Coordinates (Equate Imag. Parts) j1 Im{Γ L } j0.5 Γ L =j j2 j0.2 Z n =j0.5 j5 Γ L =-1 Γ L =0 Γ L =1 0 Re{Γ L } -j0.2 Z n =-j0.5 -j5 -j0.5 Γ L =-j -j2 -j1 22
What Happens When We Invert the Impedance? Fundamental formulas Impact of inverting the impedance - Derivation: We can invert complex impedances in plane by simply changing the sign of! How can we best exploit this? 23
The Smith Chart as a Calculator for Matching Networks Consider constructing both impedance and admittance curves on Smith chart - Conductance curves derived from resistance curves - Susceptance curves derived from reactance curves For series circuits, work with impedance - Impedances add for series circuits For parallel circuits, work with admittance - Admittances add for parallel circuits 24
Resistance and Conductance on the Smith Chart Im{Γ L } Γ L =j Y n =0.5 Z n =0.5 Γ L =-1 Γ L =0 Γ L =1 Y n =2 Z n =2 Re{Γ 0.2 0.5 1 2 5 L } Γ L =-j 25
Reactance and Susceptance on the Smith Chart j1 Im{Γ L } j0.5 Γ L =j j2 j0.2 Y n =-j2 Z n =j2 j5 Γ L =-1 Γ L =0 Γ L =1 0 Re{Γ L } -j0.2 Y n =j2 Z n =-j2 -j5 -j0.5 Γ L =-j -j2 -j1 26
Overall Smith Chart j1 j0.5 j2 j0.2 j5 0 0.2 0.5 1 2 5 j0.2 j5 j0.5 j2 j1 27
Example Match RC Network to 50 Ohms at 2.5 GHz Circuit Matching Network Z in C p =1pF R p =200 Z L Step 1: Calculate Z Ln Step 2: Plot Z Ln on Smith Chart (use admittance, Y Ln ) 28
Plot Starting Impedance (Admittance) on Smith Chart j1 j0.5 j2 j0.2 j5 0 0.2 0.5 1 2 5 -j0.2 -j5 -j0.5 Y Ln =0.25+j0.7854 -j2 -j1 (Note: Z Ln =0.37-j1.16) 29
Develop Matching Game Plan Based on Smith Chart By inspection, we see that the following matching network can bring us to Z in = 50 Ohms (center of Smith chart) Matching Network L m Z in C p =1pF R p =200 C m Z L Use the Smith chart to come up with component values - Inductance L m shifts impedance up along reactance curve - Capacitance C m shifts impedance down along susceptance curve 30
Add Reactance of Inductor L m j1 j0.5 j2 Z 2n =0.37+j0.48 j0.2 j5 0 0.2 0.5 1 2 5 normalized inductor reactance -j0.2 = j1.64 -j5 -j0.5 Z Ln =0.37-j1.16 -j1 -j2 31
Inductor Value Calculation Using Smith Chart From Smith chart, we found that the desired normalized inductor reactance is Required inductor value is therefore 32
Add Susceptance of Capacitor C m (Achieves Match!) j1 j0.5 Z 2n =0.37+j0.48 (note: Y 2n =1.00-j1.31) j2 j0.2 0 normalized capacitor susceptance = j1.31 1.0+j0.0 0.2 0.5 1 2 5 j5 -j0.2 -j5 -j0.5 Z Ln =0.37-j1.16 -j1 -j2 33
Capacitor Value Calculation Using Smith Chart From Smith chart, we found that the desired normalized capacitor susceptance is Required capacitor value is therefore 34
Just For Fun Play the matching game at http://contact.tm.agilent.com/agilent/tmo/an-95-1/classes/imatch.html - Allows you to graphically tune several matching networks - Note: game is set up to match source to load impedance rather than match the load to the source impedance Same results, just different viewpoint 35
Passives 36
Polysilicon Resistors Use unsilicided polysilicon to create resistor A A R poly B B Key parameters - Resistance (usually 100-200 Ohms per square) - Parasitic capacitance (usually small) Appropriate for high speed amplifiers - Linearity (quite linear compared to other options) - Accuracy (usually can be set within ± 15%) 37
MOS Resistors Bias a MOS device in its triode region A R ds W/L B A B High resistance values can be achieved in a small area (MegaOhms within tens of square microns) Resistance is quite nonlinear - Appropriate for small swing circuits 38
High Density Capacitors (Biasing, Decoupling) MOS devices offer the highest capacitance per unit area - Limited to a one terminal device - Voltage must be high enough to invert the channel A A C 1 =C ox WL W/L Key parameters - Capacitance value Raw cap value from MOS device is 6.1 ff/ m 2 for 0.24u CMOS - Q (i.e., amount of series resistance) Maximized with minimum L (tradeoff with area efficiency) See pages 39-40 of Tom Lee s book 39
High Q Capacitors (Signal Path) Lateral metal capacitors offer high Q and reasonably large capacitance per unit area - Stack many levels of metal on top of each other (best layers are the top ones), via them at maximum density A A C 1 B - B Accuracy often better than ±10% - Parasitic side cap is symmetric, less than 10% of cap value Example: C T = 1.5 ff/ m 2 for 0.24 m process with 7 metals, L min = W min = 0.24 m, t metal = 0.53 m - see Capacity Limits and Matching Properties of Integrated Capacitors, Aparicio et. al., JSSC, Mar 2002 40
Spiral Inductors Create integrated inductor using spiral shape on top level metals (may also want a patterned ground shield) A A B L m B - Key parameters are Q (< 10), L (1-10 nh), self resonant freq. - Usually implemented in top metal layers to minimize series resistance, coupling to substrate - Design using Mohan et. al, Simple, Accurate Expressions for Planar Spiral Inductances, JSSC, Oct, 1999, pp 1419-1424 - Verify inductor parameters (L, Q, etc.) using ASITIC http://formosa.eecs.berkeley.edu/~niknejad/asitic.html 41
Bondwire Inductors Used to bond from the package to die - Can be used to advantage Adjoining pins package die From board L bondwire To chip circuits C pin C bonding_pad Key parameters - Inductance ( 1 nh/mm usually achieve 1-5 nh) - Q (much higher than spiral inductors typically > 40) 42
Integrated Transformers Utilize magnetic coupling between adjoining wires A B C par1 k C D L 1 L 2 C C par2 D Key parameters - A B L (self inductance for primary and secondary windings) - k (coupling coefficient between primary and secondary) Design ASITIC, other CAD packages 43
High Speed Transformer Example A T-Coil Network A T-coil consists of a center-tapped inductor with mutual coupling between each inductor half B L 2 C B X k L 1 X A A B Used for bandwidth enhancement - See S. Galal, B. Ravazi, 10 Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18u CMOS, ISSCC 2003, pp 188-189 and Broadband ESD Protection, pp. 182-183 44