EE 435 Lecture Offset Voltages Common Mode Feedback
Review from last lecture Offset Voltage Two types of offset voltage: Systematic Offset Voltage Random Offset Voltage V ICQ Definition: The output offset voltage is the difference between the desired output and the actual output when V id =0 and V ic is the quiescent commonmode input voltage. OFF = - VOUTDES Note: OFF is dependent upon V ICQ although this dependence is usually quite weak and often not specified
Review from last lecture Offset Voltage V OFF V ICQ Definition: The input-referred offset voltage is the differential dc input voltage that must be applied to obtain the desired output when V ic is the quiescent common-mode input voltage. Note: V OFF is usually related to the output offset voltage by the expression V V OUTOFF OFF= C Note: V OFF is dependent upon V ICQ although this dependence is usually quite weak and often not specified
Review from last lecture Offset Voltage Two types of offset voltage: Systematic Offset Voltage Random Offset Voltage V ICQ fter fabrication it is impossible (difficult) to distinguish between the systematic offset and the random offset in any individual op amp Measurements of offset voltages for a large number of devices will provide mechanism for identifying systematic offset and statistical characteristics of the random offset voltage
Gradient and Local Random Effect 100µm 0.01µm Local Random Effects : Vary Locally With No Correlation Gradient Effects : Locally ppear Linear Magnitude and Direction of Gradients are random Highly Correlated over Short Distances Both Contribute to Offset Both are random variables If Not Managed, Both Can Cause Large Offsets Strategies for minimizing their effects are different Will refer to the local random effects as random and the random gradient effects as gradient effects
Offset Voltage V OS Can be modeled as a dc voltage source in series with the input
Offset Voltage Effects of Offset Voltage - an example V IN R 1 R Desired I/O relationship V DD V M t V IN
Effects of Offset Voltage - an example Desired I/O relationship Offset Voltage V IN V DD R 1 R V M t ctual I/O relationship due to offset V IN V DD V M t V IN V DD V M t V IN
Offset Voltage V OS V OS Effects can be reduced or eliminated by adding equal amplitude opposite Dc signal (many ways to do this) Widely used in offset-critical applications Comes at considerable effort and expense Prefer to have designer make V OS small in the first place
Effects of Offset Voltage Deviations in performance will change from one instantiation to another due to the random component of the offset Particularly problematic in high-gain circuits major problem in many other applications Not of concern in many applications as well
Offset Voltage Distribution number -6-5 -4-3 - -1 1 3 4 5 6 Offset Voltage Bins Typical histogram of random offset voltage (binned) after fabrication
Offset Voltage Distribution Gaussian (Normal) pdf number -6-5 -4-3 - -1 1 3 4 5 6 Offset Voltage Bins Typical histogram of offset voltage (binned) after fabrication Mean is nearly 0 (actually the systematic offset voltage)
Offset Voltage Distribution number -6-5 -4-3 - -1 1 3 4 5 6 Offset Voltage Bins Typical histogram of offset voltage (binned) in shipped parts Extreme offset parts have been sifted at test
Offset Voltage Distribution number -6-5 -4-3 - -1 1 3 4 5 6 Offset Voltage Bins Typical histogram of offset voltage (binned) in shipped parts Low-offset parts sold at a premium Extreme offset parts have been sifted at test
Offset Voltage Distribution Pdf of zero-mean Gaussian distribution 0 x Characterized by its standard deviation σ or variance σ Offset voltage often specified as the 1σ or 3σ value
Offset Voltage Distribution Pdf of zero-mean Gaussian distribution f(x) -kσ kσ x Percent between: ±σ 68.3% ±σ 95.5% ±3σ 99.73%
Source of Random Offset Voltages Consider as an example: V DD R 1 R M 1 M I T V SS Ideally R 1 =R =R, M 1 and M are matched IT = VDD - R ssume this is the desired output voltage
Source of Random Offset Voltages Consider as an example: V DD R 1 R M 1 M I T If everything ideal except R =R +ΔR V SS IT = VDD - R+ R I V T OUT = - R
Source of Random Offset Voltages Consider as an example: V DD V DD R 1 R R 1 R M 1 M -V d / M 1 M V d / I T I T V SS V SS g m V = - R
Source of Random Offset Voltages Determine the offset voltage i.e. value of V X needed to obtain desired output V DD R R+ΔR V X M 1 M g m V = - R I T V SS I I V = - ΔR - V T T OUT VDD- R V X -1 I V T X= ΔR V
Source of Random Offset Voltages Determine the offset voltage i.e. value of V X needed to obtain desired output V DD R R+ΔR V X M 1 M I T g m V = - R V SS -1 I V T X= V ΔR IT IT ΔR IT ΔR ΔR V X= ΔR = VEB gmr gm R I T/VEB R R V = V X EB ΔR R
Source of Random Offset Voltages The random offset voltage is almost entirely that of the input stage in most op amps V DD V DD V X M 3 M 4 V X M 3 M 4 V 1 M 1 M V S V V 1 M 1 M V V S I T I T (a) (b)
Random Offset Voltages Bulk Source Gate Drain Bulk Source n-channel MOSFET Gate Drain n-channel MOSFET Impurities vary randomly with position as do edges of gate, oxide and diffusions Model and design parameters vary throughout channel and thus the corresponding equivalent lumped model parameters will vary from device to device
Random Offset Voltages V DD The random offset is due to missmatches in the four transistors, dominantly missmatches in the parameters {V T, μ,c OX,W and L} V X M 3 M 4 The relative missmatch effects become more pronounced as devices become smaller V 1 M 1 M V S V I T V Ti =V TN +V TRi C OXi =C OXN +C OXRi μ i =μ N +μ Ri W i =W N +W Ri L i =L N +L Ri Each design and model parameter is comprised of a nominal part and random component
Random Offset Voltages V DD V Ti =V TN +V TRi V X M 3 M 4 C OXi =C OXN +C OXRi μ i =μ N +μ Ri V 1 M 1 M V S V W i =W N +W Ri I T L i =L N +L Ri For each device, the device model is often expressed as μn μri COXN COXRi W N+WRi L L I = V -(V V ) 1+ λ +λ V Di GSi TN TRi N Ri DS N Ri Because of the random components of the parameters in every device, matching from the left-half circuit to the right half-circuit is not perfect This mismatch introduces an offset voltage which is a random variable
Random Offset Voltages From a straightforward but tedious analysis it follows that: 1 1 1 1 + + μ μ COX + VTO n μ W L W L W L W L p L n V EB n σ + + VOS VTO p W nl n μ n W nl 4 p 1 1 1 1 + L + + w + W n L n W p L p L n W n L p W p n p n n p p n n p p where the terms VT0, μ, COX, L, and W are process parameters V DD 1mV μ (n-ch) VT0 5mV μ (p-ch) μ+ C OX.016μ (n-ch).03μ (p-ch) V X M 3 M 4 L=W 0.017μ VTO n μ p L n VOS W VTO p n L n μ n W n L p σ + 3 Usually the VT0 terms are dominant, thus the variance simplifies to V 1 M 1 M V S I T V
Correspondingly: Random Offset Voltages V OS Wn L VTOn n p n L n n p W L VTOp V EBn 4 1 Wn L n L n 1 Wn L n 1 W L p p 1 p W L p p COX w L 1 W L n 1 n W n n L 1 W L p 1 p W p p which again simplifies to VTO n μ p L n VOS W VTO p n L n μ n W n L p σ + V DD V X M 3 M 4 V 1 M 1 M V V S Note these offset voltage expressions are identical! I T
Random Offset Voltages Example: Determine the 3σ value of the input offset voltage for The MOS differential amplifier if a) M 1 and M 3 are minimum-sized and b) the area of M 1 and M 3 are 100 times minimum size V DD V X a) VTO n μ p L n VOS W VTO p n L n μ n W n L p σ + μ p σ V + OS W VTO n VTO p n L n μ n 1 σ.01 +.05 OS 0.5 3 V σ V OS 7mV M 3 M 4 V 1 M 1 M V V S I T 3 σ 16mV V OS Note this is a very large offset voltage!
Random Offset Voltages Example: Determine the 3σ value of the input offset voltage for The MOS differential amplifier is a) M 1 and M 3 are minimum-sized and b) the area of M 1 and M 3 are 100 times minimum size V DD VTO n μ p L n VOS W VTO p n L n μ n W n L p μ p σ + VOS W VTO n VTO p n L n μ n σ + b) 1 σ.01 +.05 VOS 1000.5 3 V X M 3 M 4 V 1 M 1 M V V S I T σ V OS 7.mV 3 σ 1.6mV V OS Note this is much lower but still a large offset voltage! The area of M 1 and M 3 needs to be very large to achieve a low offset voltage
Random Offset Voltages V CC V CC Q 3 V X Q 4 Q 3 V X Q 4 V 1 Q 1 Q V V 1 Q 1 Q V V E V E I T I T (a) (b) It can be shown that V OS where very approximately V + = = 0.1μ Jn Jp Jn t En Jp Ep
Random Offset Voltages V CC Example: Determine the 3σ value of the offset voltage of a the bipolar input stage if E1 = E3 =10μ Q 3 V X Q 4 V OS V Jn t + En Jp Ep V 1 Q 1 V E I T Q V V OS V t J E 1 5mV 0.1μ 1.6mV V OS 10μ 3 4.7mV V OS Note this value is much smaller than that for the MOS input structure!
Random Offset Voltages Typical offset voltages: MOS - 5mV to 50MV BJT - 0.5mV to 5mV These can be scaled with extreme device dimensions Often more practical to include offset-compensation circuitry
Common Centroid Layouts Define p to be a process parameter that varies with lateral position throughout the region defined by the channel of the transistor. lmost Theorem: If p(x,y) varies throughout a two-dimensional region, then p EQ 1 p x, y dxdy Parameters such at V T, µ and C OX vary throughout a two-dimensional region
y x p EQ 1 p x, y dxdy
Common Centroid Layouts lmost Theorem: If p(x,y) varies linearly throughout a two-dimensional region, then p EQ =p(x 0.y 0 ) where x 0,y 0 is the geometric centroid to the region. If a parameter varies linearly throughout a two-dimensional region, it is said to have a linear gradient. Many parameters have a dominantly linear gradient over rather small regions
(x 0,y 0 ) (x 0,y 0 ) is geometric centroid p EQ 1 p x, y dxdy If ρ(x,y) varies linearly in any direction, then the theorem states 1 p p x,y dxdy p x,y EQ 0 0
Common Centroid Layouts layout of two devices is termed a common-centroid layout if both devices have the same geometric centroid lmost Theorem: If p(x,y) varies linearly throughout a two-dimensional region, then if two devices have the same centroid, the lateral-variable parameters are matched! Note: This is true independent of the magnitude and direction of the gradient!
Recall parallel combinations of transistors equivalent to a single transistor of appropriate W,L W,L W,L W,L M 1 M M k kw,l W,L W,L W,L
Centroids of Segmented Geometries Denotes Geometric Centroid
Common Centroid of Multiple Segmented Geometries
Common Centroid of Multiple Segmented Geometries
Common Centroid Layouts Common centroid layouts widely (almost always) used where matching of devices or components is critical because these layouts will cancel all first-order gradient effects pplies to resistors, capacitors, transistors and other components lways orient all devices in the same way Keep common centroid for interconnects, diffusions, and all features Often dummy devices placed on periphery to improve matching!
Common Centroid Layout Surrounded by Dummy Devices
End of Lecture