1 High-Performance 4nm Gate Length InSb P-Channel Compressively Strained Quantum Well Field Effect Transistors for Low-Power (V CC =.5V) Logic Applications M. Radosavljevic,, T. Ashley*, A. Andreev*, S. D. Coomber*, G. Dewey, M. T. Emeny*, M. Fearn*, D. G. Hayes*, K. P. Hilton*, M. K. Hudait, R. Jefferies*, T. Martin*, R. Pillarisetty, W. Rachmady, T. Rakshit, S. J. Smith*, M. J. Uren*, D. J. Wallis*, P. J. Wilding* ing* and Robert Chau Components Research, TMG Intel Corporation *QinetiQ Contact: robert.s.chau@intel.com
2 Outline Motivation Materials Transistors Benchmarking Summary
3 Outline Motivation Materials Transistors Benchmarking Summary
Advantages of III-V n-qwfets for Low V CC Logic (e.g..5v) 4 ELECTRON MOBILITY [cm 2 /Vs] 1 5 1 4 1 3 Si InSb * InGaAs >3X improvement 1 2 5x1 11 1 12 1 13 2x1 13 SHEET CARRIER DENSITY [cm -2 ] CUT-OFF FREQUENCY, f T [GHZ] 5 4 InSb n-qwfet on Si 3 (L G =85nm) 2 1 V CC =.5V InGaAs n-qwfet on Si (L G =8nm) V CC = 1.1V V CC =.5V Silicon (L G =6nm) 1 1 1 DC POWER DISSIPATION [ W/ m] III-V n-channel has >3X higher electron mobility over Si III-V on Si achieves f T > 4GHz at V CC =.5V
Advantages of III-V n-qwfets for Low V CC Logic (e.g..5v) Measurement Data at V G -V T =.3V >5X Veff=Gmi/Cgi Gmi/Cgi,, extracted from RF measurements Further improvement in Veff via shorter gate-to to-qw separation and continued L G scaling 5
Advantages of III-V n-qwfets for Low V CC Logic (e.g..5v) Experimental Data: Experiment & Simulation: Intrinsic Drive Current (ma/ m) 1.2 1.8.6.4.2 InGaAs QWFET (T OXE =34A) Strained Si (T OXE =14A) SS=9mV/dec DIBL=15mV/V V DS =.5V.2.4.6.8 Gate Overdrive (V -V ) (Volt) G T 8 6 4 2-2 % Gain III-V over Silicon Drain current, I D (ma/ m).6.5.4.3.2 8nm InGaAs QW, T OXE =27A R SD matched to Si (Simulated) 8nm InGaAs QW T OXE =34A 2X R SD 4nm Strained Si 2%.1 T OXE =14A V -V =.3V G T.1.2.3.4.5 Drain voltage, V (V) DS 8% Intrinsic drive current = (q*veff * n S ) At V G - V T =.3V, III-V V shows >5% gain in intrinsic drive current over Si Measured I DSAT gain in current devices >2% over Si 6
7 Advantages of III-V n-qwfets for Low V CC Logic (e.g..5v) Experimental Data: Experiment & Simulation: Intrinsic Drive Current (ma/ m) 8.6 1.2 InGaAs QWFET 8nm InGaAs QW, T OXE =27A (T =34A) OXE 1 6.5 R SD matched to Si (Simulated).8 Strained Si.4 8nm InGaAs QW 4 Question: Can (T we =14A) OXE identify promising p-channel T OXE =34A.6.3 2X R III-V QWFET options for 2 CMOS configuration? SD.4.2 SS=9mV/dec 4nm Strained Si 2%.2 DIBL=15mV/V.1 T OXE =14A V =.5V V -V =.3V DS G T -2.2.4.6.8.1.2.3.4.5 Gate Overdrive (V -V ) (Volt) Drain voltage, V (V) G T DS % Gain III-V over Silicon Drain current, I D (ma/ m) 8%
P-channel QW Materials Options Gate delay [ps] 1 1 GaAs QW [1] InGaSb QW [2] Ge QW [3,4] Si p-mosfet 1 1 1 1 Gate length L [nm] G Ge p-qwfet is an option under investigation Parallel conduction is a major issue Existing III-V p-qwfet data matched to Si at best Can p-channel performance in III-V be improved? InSb has highest hole mobility in III-V [1] Park, Proc. IEEE 1989; [2] Boos, EL 27; [3] Koester, EDL 2; [4] Arafa, EDL 1996. 8
9 Enhancing InSb Hole Mobility via Biaxial Compressive Strain.3 Bulk InSb m hh Effective hole mass m* h [m ].2.1. InSb on Al x In 1-x Sb with increasing Al%.1.2.3.4 E(k) - E(k=) [ev].8% compressive strain 1.6% compressive strain 1.9% compressive strain K.P simulations show that biaxial compressive strain significantly reduces in-plane hole effective mass in InSb
1 Outline Motivation Materials Transistors Benchmarking Summary
11 InSb Quantum Well Device Structure Ti/Au Source 6nm p-doped 1nm p-doped Ti/Au Gate L G Ti/Au Drain low resistance cap Al x In 1-x Sb top barrier 3nm undoped Al x In 1-x Sb top barrier Be -doping 7nm undoped Al x In 1-x Sb spacer 5-15nm InSb quantum well 3 m undoped Al x In 1-x Sb bottom barrier 2nm Al y In 1-y Sb interfacial layer Semi-insulating GaAs substrate Quantum Well Energy [ev] 1.5 -.5 8x8 K.P-Poisson simulation Be -doping CB Al In Sb.35.65 barriers E F VB E wavefunction InSb QW -1 1 2 3 4 5 Distance [nm] Simulations indicate hole confinement in InSb QW Remote doping is utilized to reduce Coulomb scattering Larger biaxial strain requires reduction in QW thickness
12 Modulating Biaxial Compressive Strain in InSb Quantum Well Device Structure X-ray intensity [a.u.] 1.9% compressively strained GaAs InSb QW on Al.35 In.65 Sb substrate Al.3 In.7 Sb (1.6%) Al.15 In.85 Sb (.8%) -17-15 -1 Omega/2theta [arcsec] bottom barrier Ti/Au Source 6nm p-doped 1nm p-doped Ti/Au Gate L G Ti/Au Drain low resistance cap Al x In 1-x Sb top barrier 3nm undoped Al x In 1-x Sb top barrier Be -doping 7nm undoped Al x In 1-x Sb spacer 5-15nm InSb quantum well 3 m undoped Al x In 1-x Sb bottom barrier 2nm Al y In 1-y Sb interfacial layer Semi-insulating GaAs substrate XRD validates the full relaxation of bottom barrier layers Resulting biaxial compressive strain in QW is increased with increasing Al%
13 XTEM Micrographs of InSb QW Device Structure Drain Gate, L G =4nm Source p+ cap Al.4 In.6 Sb top barrier 5nm InSb QW Al.35 In.65 Sb bottom barrier 5nm QW with 1.9% biaxial compressive strain
Mobility of InSb p-qw Device Structure 2D hole mobility [cm 2 /V-s] 1 1 Remote doping & 1.9% strain Remote doping & 1.6% strain Bulk doping & 1.6% strain Strained Silicon InSb QW 1 11 1 12 1 13 2DHG sheet carrier density [cm -2 ] Mobility improves with increased biaxial compressive strain and remote doping Highest p-qw p device structure mobility: =123cm 2 /V-s s at n s =1.1e12/cm 2 InSb QW hole mobility is 5X higher than strained Si 14
15 Outline Motivation Materials Transistors Benchmarking Summary
InSb p-qwfet Fabrication A two gate finger InSb QWFET is fabricated with gate air-bridge using mesa isolation L G =4-125nm fabricated with recess etch Schottky gate Gate-to to-qw separation in SiO 2 equivalent thickness, OXE = 3A at V G -V T = -.3V T OXE 16
17 InSb p-qwfet L G =125nm Drain current, I D [ma/ m] -.15 -.1 -.5 T =3A OXE V =-.4V GS -.3V -.2V -.1V V -.1 -.2 -.3 -.4 -.5 Drain voltage, V [V] DS I D & I G [ma/ m] 1 1-1 1-2 1-3 1-4 1-5 1-6 1-7 I D @V DS = -.5V I D @V DS = -.5V I G @V DS = -.5V I G @V DS = -.5V -.4 -.2.2 Gate voltage, V [V] G L G =125nm device has SS =9mV/dec, and DIBL =8mV/V I ON /I OFF > 7 at V DS = -.5V with.5v V G swing
InSb p-qwfet L G =4nm Drain current, I D [ma/ m] -.2 -.15 -.1 -.5 T OXE =3A V GS =-.4V -.3V -.1 -.2 -.3 -.4 Drain voltage, V [V] DS -.2V -.1V V -.5 I & I [ma/ m] D G 1 1-1 1-2 1-3 1-4 1-5 1-6 1-7 I D @V DS = -.5V I D @V DS = -.5V I G @V DS = -.5V I G @V DS = -.5V -.4 -.2.2 Gate voltage, V [V] G L G =4nm device has SS=16mV/dec, and DIBL=22mV/V I ON /I OFF =15 at V DS = -.5V with.5v V G swing OXE reduction required for SS and DIBL improvement T OXE 18
19 InSb p-qwfet L G =4nm 5 4 V DS = -.5V G m [ S/ m] 3 2 1 L G = 4nm T OXE = 3A -.4 -.2.2 Gate voltage, V G [V] L G =4nm device achieves G m =5 S/ S/ m m at V CC =.5V, the highest reported for III-V V p-qwfetp
2 InSb p-qwfet Short-Channel Effects Sub-threshold slope [mv/dec] 2 25 18 T OXE =3A 2 16 14 15 12 1 1 8 V DS = -.5V 5 6 2 4 6 8 1 12 14 Gate length, L [nm] G DIBL [mv/v] Ti/Au Source 6nm p-doped 1nm p-doped Ti/Au Gate L G Ti/Au Drain low resistance cap Al x In 1-x Sb top barrier 3nm undoped Al x In 1-x Sb top barrier Be -doping 7nm undoped Al x In 1-x Sb spacer 5-15nm InSb quantum well 3 m undoped Al x In 1-x Sb bottom barrier 2nm Al y In 1-y Sb interfacial layer Semi-insulating GaAs substrate Short channel effects can be improved by further reducing gate to channel separation
21 InSb p-qwfet RF Measurements and Modeling Measured and modeled S-parameters S fit each other with RMS error <2% Extracted gate capacitance is independent of frequency
22 InSb p-qwfet RF Performance h 21 [db] 6 5 De-embedded 4-2dB/dec 3 Model 2 f T = 14GHz Embedded 1 V DS = -.5V 1-1 1 1 1 1 2 Frequency [GHz] L G =4nm device achieves f T =14GHz at V CC =.5V, the highest reported for III-V V p-qwfetp
23 Outline Motivation Materials Transistors Benchmarking Summary
Benchmarking of InSb p-qwfet Gate delay [ps] 1 GaAs QW [1] InGaSb QW [2] Si p-mosfet 1 This work 1 1 1 1 Gate length L [nm] G Energy x Delay / Width [Js/m] 1-17 1-18 1-19 1-2 1-21 1-22 1-23 GaAs QW [1] InGaSb QW [2] Si p-mosfet This work 1 1 1 Gate length L [nm] G InSb p-qwfets exhibit significant improvement in gate delay and energy-delay product [1] Park, Proc. IEEE 1989; [2] Boos, EL 27 24
25 Speed-Power Performance of InSb p-qwfet Cut-off frequency, f [GHz] T 15 1 5 InSb p-qwfet [L G = 4nm] V DS = -.5V -1.1V Strained Si V DS = -.5V p-mosfet [L G = 6nm] 1 1 1 2 1 3 DC power dissipation [ W/ m] L G =4nm device achieves f T =14GHz at V CC =.5V, the highest reported for III-V V p-qwfetp
Veff [x1 7 cm/s].8.6.4 InSb p-qwfet Effective Velocity and Intrinsic Drive Current Effective velocity >2X InSb p-qwfet (T OXE =3A).2 Strained Si (T =14A) OXE V -V = -.3V G T 1 2 DIBL [mv/v] q*veff*n S (ma/ m).6.4.2 Intrinsic Drive Current Strained Si (T OXE =14A) InSb p-qwfet (T OXE =3A) SS=125mV/dec DIBL=15mV/V V DS = -.5V -.6 -.4 -.2 Gate Overdrive (V -V ) (Volt) G T 6 4 2-2 -4 % Gain InSb over Silicon InSb p-qwfets show >2X Veff gain over strained Si p-mosfets at matched DIBL At V G - V T = -.3V, InSb p-qwfet is matched in intrinsic drive current to Si despite less gate control Further improvement via T OXE reduction or strain increase 26
27 Outline Motivation Materials Transistors Benchmarking Summary
28 Summary InSb p-qw device structure demonstrates 1.9% biaxial compressive strain hole mobility of 1,23cm 2 /V-s s at n s =1.1e12/cm 2 InSb device with L G =4nm achieves peak G m =5 S/ S/ m at V CC =.5V,, highest reported for III-V p-qwfets peak f T =14GHz at V CC =.5V, highest reported for III-V p-qwfets Benchmarking InSb p-qwfets to standard strained Si >2X Veff gain at same DIBL Intrinsic I DSAT (q*n S *Veff)) matched at V CC =.5V despite thicker T OXE Strained InSb p-qwfet intrinsic transport advantages make it a promising option for the III-V V CMOS configuration
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