July 5th, 4 Goals of This Chapter Quantification of Design Metrics of an inverter Static (or Steady-State) Behavior Chapter 5 CMOS Inverter Boonchuay Supmonchai Integrated Design Application Research (IDAR) Laboratory July 5, 4; Revised - June 5, 5 Dynamic (or Transient Response) Behavior Energy Efficiency Optimization of an inverter design Technology Scaling and its impact on the inverter metrics -545 Digital ICs CMOS Inverter Digital Gate Design Metrics: Recap Why CMOS Inverter? Cost Complexity and Area Reliability and Robustness Static Behavior Noise Margin, Regenerative Property Performance Dynamic Behavior Speed (Delay) Energy Efficiency Energy and Power Consumption, Energy-Delay CMOS because it is the dominating technology of the era. High Packing Density Relatively Easy Process Inverter because it is the nucleus of all digital designs. Behavior of more intricate structures (logic gates, adders, etc.) can be almost completely derived by extrapolating the results obtained from the inverters. -545 Digital ICs CMOS Inverter 3-545 Digital ICs CMOS Inverter 4-545 Digital ICs
July 5th, 4 CMOS Inverter: A First Glance CMOS Inverter: Physical View Recap Driven by Output Of another gate => Fanin PMOS In PMOS Out N Well PMOS l Contacts NMOS Collective Capacitances Of Wires and Gates => Fanout NMOS Polysilicon NMOS In Out Metal GND -545 Digital ICs CMOS Inverter 5-545 Digital ICs CMOS Inverter 6 Two CMOS Inverters: Physical View CMOS Inverter Static Behavior Share power and ground R p Connect In Metal R n Vout Vout Abut Cells -545 Digital ICs CMOS Inverter 7 = = State of Transistors ON: V GT = V GS - V T > V T, R on Æ OFF: V GT = V GS - V T > V T, R off finite -545 Digital ICs CMOS Inverter 8-545 Digital ICs
July 5th, 4 Charge Discharge R n Low to High High to Low = = response time is determined by the time to charge CL through lgate Rp (discharge through R n ) CMOS Inverter Dynamic Behavior R p CMOS Properties Full rail-to-rail swing High noise margins Logic levels not dependent upon the relative device sizes => Ratioless Transistors can be minimum size Regenerative Property Low output impedance Large Fan-out (albeit with degraded performance) Typical output resistance in kw range. -545 Digital ICs CMOS Inverter 9-545 Digital ICs CMOS Inverter CMOS Properties () Extremely high input resistance (MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path between power and ground under steady-state (but there always exists a path with finite resistance between the output and either or GND) no static power dissipation Propagation delay a function of load capacitance and resistance of transistors -545 Digital ICs CMOS Inverter NMOS Short Channel I-V Plot Recap I D (A) X.5-4.5.5.5.5.5 V DS (V) V GS =.5 V V GS =. V V GS =.5 V V GS =. V NMOS transistor,.5 mm, L d =.5 mm, W/L =.5, =.5 V, V T =.4 V -545 Digital ICs CMOS Inverter Linear dependence -545 Digital ICs 3
July 5th, 4 PMOS Short Channel I-V Plot Recap l All polarities of all voltages and currents are reversed - V GS = -. V V GS = -.5 V V GS = -. V V DS (V) - -. -.4 -.6 I D (A) Transforming PMOS I-V Plot I DSp = -I DSn V GSn = ; V GSp = - V DSn = ; V DSp = - = =.5 I Dn l NMOS and PMOS VTC must be put into a common coordinate set of,, and I Dn = =.5 V GS = -.5 V -.8 - X -4 PMOS transistor,.5 mm, L d =.5 mm, W/L =.5, =.5 V, V T = -.4 V -545 Digital ICs CMOS Inverter 3 V GSp = - V GSp = -.5 Mirror around x-axis = + V GSp I Dn = -I Dp Horiz. shift over = + V DSp -545 Digital ICs CMOS Inverter 4 CMOS Inverter Load-Line Plot I Dn (A) PMOS X -4 NMOS.5 = V =.5 V.5 =. V = V (V) =.5 V =. V =.5 V = V =.5 V.5 =.5 V =. V =. V =.5 V.5.5.5 =.5 V =.5 V = V CMOS.5 mm, W/L n =.5, W/L p = 4.5, =.5 V, V Tn =.4 V, V Tp = -.4 V -545 Digital ICs CMOS Inverter 5 CMOS Inverter VTC (V) * VTC = Voltage-Transfer Characteristics.5.5.5 NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat = NMOS res PMOS sat NMOS res PMOS off.5.5.5 (V) -545 Digital ICs CMOS Inverter 6-545 Digital ICs 4
July 5th, 4 Robustness of CMOS Inverter Precise Values of Switching Threshold, V M V M is defined as the point where = Noise Margins Piece-Wise Linear Approximation Maximization Process Variations Device Variations Technology Scaling -545 Digital ICs CMOS Inverter 7 Switching Threshold At V M where =, both PMOS and NMOS transistors are in saturation (since V DS = V GS ) V M ª r /( + r) where r = k p V DSATp /k n V DSATn Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors Goal: To set V M = / (to maximize noise margins), so r ª ( W L) p W L ( ) n = ( ) ( ) k n 'V DSAT,n V M -V T,n -V DSAT,n / [ ] k p 'V DSAT,p - V M -V T,p -V DSAT,p / -545 Digital ICs CMOS Inverter 8 Switch Threshold Example Example: Simulated Results In our generic.5 micron CMOS process, using the process parameters from Table 3., at =.5V, and a minimum size NMOS device ((W/L) n of.5) NMOS PMOS V T (V).43 -.4 g(v.5 ).4 -.4 V DSAT (V).63 - k (A/V ) 5 x -6-3 x -6 l(v - ).6 -. V (V) M.8.7.6.5.4.3..5 V (W/L) p (W/L) n = 5 x -6.63 (.5.43.63/) x x = 3.5-3 x -6 -. (.5.4./) (W/L) p = 3.5 x.5 = 5.5 for a V M of.5 V -545 Digital ICs CMOS Inverter 9..9 r = 3.4.8 W p /W n Minimum Width-to-Length =.5-545 Digital ICs CMOS Inverter -545 Digital ICs 5
July 5th, 4 Observations I V M is relatively insensitive to variations in device ratio Small Variations of the ratio do not significantly disturb VTC. Common Industry Practice to set W p smaller than the reuirement. Increasing the width of the PMOS moves V M towards Increasing the width of the NMOS moves V M toward GND -545 Digital ICs CMOS Inverter 3 V OH = V OL = GND VIL IL V VIH IH A piece-wise linear approximation of VTC Noise Margins: Determining V IH and V IL By definition, V IH and V IL are where gain d /d = - Slope = g V M Gain g = Slope NM H = - V IH NM L = V IL - GND Approximating: V IH = V M - V M /g V IL = V M + ( - V M )/g So high gain in the transition region is very desirable -545 Digital ICs CMOS Inverter CMOS Voltage Gain gain - -4-6 -8 - - -4-6 -8.5.5 Gain is a strong function of the slopes of the currents in the saturation region, for = V M Determined only by technology parameters, especially channel length modulation (l). Only designer influence through supply voltage and V M (transistor sizing). -545 Digital ICs CMOS Inverter 3 Example: VTC and Noise Margin For a.5mm, (W/L) p /(W/L) n = 3.4, (W/L) n =.5 (min size) =.5V V M ª.5 V, g = -7.5 V IL =. V, V IH =.3 V NM L = NM H =. Real Value V IL =.3 V, V IH =.45 V NM L =.3, NM H =.5 Output resistance fi Sensitivity of gate output with respect to noise low-output =.4 kw high-output = 3.3 kw Preferably as low as possible -545 Digital ICs CMOS Inverter 4-545 Digital ICs 6
July 5th, 4 Observations II First-Order Analysis overestimates the gain Max. gain only 7 at V M Æ V IL =.7V, V IH =.33V Piecewise Linear Approximation is too overly optimistic Major contributor to deviation from the true gain CMOS inverter is a poor analog amplifier! One of the major differences between analog and digital designs is that digital circuits operate in the regions of extreme nonlinearity. Well-defined and well-separated high and low signals -545 Digital ICs CMOS Inverter 5 Vout(V).5.5 Impact of Process Variation on VTC.5 Bad PMOS Good.5.5.5 Vin(V) variations (mostly) NMOSlProcess cause a shift in the switching threshold -545 Digital ICs CMOS Inverter 6 Nominal Good PMOS Bad NMOS Scaling the Supply Voltage Vout(V).5.5.5.5.5.5 (V)..5..5.5..5. Vin(V) Reducing improves Gain But it deteriorates for very low -545 Digital ICs CMOS Inverter 7 Vout(V) Gain=- Practical Lower Bound: min > to 4 kt / Observations III Reducing the supply voltage has a positive impact on the energy dissipation But is also detrimental to the delay of the gate DC Characteristic becomes increasingly sensitive to device variations once supply and intrinsic voltages become comparable Scaling the supply voltage = reducing the swing Reduce internal noise (e.g., crosstalk) More susceptible to external noise that do not scale -545 Digital ICs CMOS Inverter 8-545 Digital ICs 7
July 5th, 4 CMOS Inverter Dynamic Behavior Transient behavior of the gate is determined by the time it takes to charge and discharge the load capacitance,, through on-transistors Delay is a function of load capacitances and transistor on-resistances Getting as small as possible is crucial to the realization of high-performance CMOS circuits Transistor Capacitances Wire Capacitances Fanout Wire Resistances also become more important. -545 Digital ICs CMOS Inverter 9 Computing the Capacitances V Extrinsic DD M C M4 db C g4 C V gd out C db C w C g3 M M3 Interconnect Intrinsic Fanout Simplified Model -545 Digital ICs CMOS Inverter 3 Finding C gd : The Miller Effect M and M are either in cut-off or in saturation. The floating gate-drain capacitor is replaced by a capacitance-to-ground (gate-bulk capacitor). DV C gd M DV A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground whose value is two times the original value -545 Digital ICs CMOS Inverter 3 DV M DV C gd Diffusion Capacitances: C db and C db We can simplify the diffusion capacitance calculations by using a K e to linearize the nonlinear capacitor to the value of the junction capacitance under zero-bias.5 mm Process NMOS PMOS high-to-low K ebp.57.79 C e = K e C j K esw.6.86 low-to-high K ebp.79.59 K esw.8-545 Digital ICs CMOS Inverter 3.7-545 Digital ICs 8
July 5th, 4 Extrinsic Capacitances: C g3 and C g4 Example: Layout of Two Inverters Simplification of the actual situation Assumes all the components of C gate are between and GND (or ) Assumes the channel capacitances of the loading gates are constant The extrinsic, or fan-out, capacitance is the total gate capacitance of the loading gates M 3 and M 4. PMOS.5/.5 Polysilicon NMOS.375/.5 In Out GND Metal l =.5 AD = Drain Area PD = Drain Perimeter AS = Source Area PS = Source Perimeter Minimum Drawn Length C fan-out = C gate (NMOS) + C gate (PMOS) = (C GSOn + C GDOn + W n L n C ox ) + (C GSOp + C GDOp + W p L p C ox ).5 mm NMOS PMOS W/L.375/.5.5/.5 AD (mm ).3.7 PD (mm).875.375 AS (mm ).3.7 PS (mm).875.375-545 Digital ICs CMOS Inverter 33-545 Digital ICs CMOS Inverter 34 Example: Components of (.5 mm) C Term C gd Expression Value (ff) HÆL Value (ff) LÆH C gdn W n.3.3 C gd C gdp W p.6.6 C db K ebpn AD n C j + K eswn PD n C jsw.66.9 C db K ebpp AD p C j + K eswp PD p C jsw.5.5 C g3 ( C gdn )W n + C ox W n L n.76.76 C g4 ( C gdp )W p + C ox W p L p.8.8 C w from extraction.. Â 6. 6. Wiring Capacitance The wiring capacitance depends upon the length and width of the connecting wires and is a function of the fan-out from the driving gate and the number of fan-out gates. Wiring capacitance is growing in importance with the scaling of technology. -545 Digital ICs CMOS Inverter 35-545 Digital ICs CMOS Inverter 36-545 Digital ICs 9
July 5th, 4 Inverter Propagation Delay R p = Charge Low to High = V DD Propagation delay is proportional to the time-constant of the network formed by the on-resistance and the load capacitance t p = f(r on, ) t plh =.69 R ep t phl =.69 R en t p = t + t phl plh Ê R =.69C en + R ep ˆ L Á Ë Discharge -545 Digital ICs CMOS Inverter 37 R n High to Low To eualize rise and fall times make the on-resistance of the NMOS and PMOS approximately eual. Inverter Transient Response (.5 µm) Vin, Vout(V) 3.5.5.5 t phl Simulation -.5 5 5 5 t(psec) t plh t phl = 39.9 psec and t plh = 3.7 psec Analysis =.5V W/L n =.5 W/L p = 4.5 R en = 3 kw /.5 R ep = 3 kw /4.5 t phl = 36 psec t plh = 9 psec t p = (36+9)/ = 3.5 psec Analysis results is too optimistic ~ % better -545 Digital ICs CMOS Inverter 38 Inverter Propagation Delay, Revisited To see how a designer can optimize the delay of a gate, we have to expand R e in the delay euation. tp(normalized) 5.5 5 4.5 4 3.5 3.5.5.8..4.6.8..4 (V) t phl =.69 R en =.69(3C )/(4I DSATn ) t phl ª.5 W L -545 Digital ICs CMOS Inverter 39 ( ) n k n V DSATn Minimizing Propagation Delay Reduce Keep the drain diffusion as small as possible Increase W/L ratio of the transistor Most powerful and effective way Watch out for self-loading! When the intrinsic capacitance dominates Increase Trade off energy efficiency for performance Very minimal improvement above a certain level Reliability concerns enforce a firm upper bound on -545 Digital ICs CMOS Inverter 4-545 Digital ICs
July 5th, 4 PMOS-to-NMOS Ratio So far PMOS and NMOS have been sized such that their R e s match (ratio of 3 to 3.5) symmetrical VTC eual high-to-low and low-to-high propagation delays If speed is the only concern, reduce the width of the PMOS device! widening the PMOS degrades the t phl due to larger parasitic capacitance Ê C ˆ b = (W/L) p /(W/L) b n opt = r + W Á Ë C dn + C Cgn r = R ep /R en resistance ratio of identically-sized PMOS and NMOS -545 Digital ICs CMOS Inverter 4 PMOS-to-NMOS Ratio Effects tp(psec) 5 45 4 35 3 t plh.4.5.5 3 3.5 4 4.5 5 b t p t phl b of.4 (= 3 kw/3 kw) gives symmetrical response b opt ~.6 -.9 Analytic Simulated When wire capacitance is negligible (C dn +C gn >> C W ), b opt = r If wire capacitance dominates then larger value of b must be used -545 Digital ICs CMOS Inverter 4 Device Sizing for Performance Divide capacitive load,, into C int : intrinsic - diffusion and Miller effect C ext : extrinsic - wiring and fanout t p =.69 R e C int ( + C ext /C int ) = t p ( + C ext /C int ) where t p =.69 R e C int is the intrinsic (unloaded) delay of the gate Widening both PMOS and NMOS by a factor S reduces R e by an identical factor (R e = R ref /S), but raises the intrinsic capacitance by the same factor (C int = SC iref ) t p =.69 R ref C iref ( + C ext /(SC iref )) = t p ( + C ext /(SC iref )) Observation IV Intrinsic Delay of the inverter t p is independent of the sizing of the gate; t p can be determined purely by technology and inverter layout With no load the increased drive strength of the gate is totally offset by the increased capacitance Any S sufficiently larger than (C ext /C int ) would yield a much better performance gain with a substantial area increase -545 Digital ICs CMOS Inverter 43-545 Digital ICs CMOS Inverter 44-545 Digital ICs
July 5th, 4 Sizing Impacts on Delay tp(psec) for a fixed load 38 36 34 3 3 8 6 4 3 5 7 9 3 5 S The majority of the improvement is already obtained for S = 5. Sizing factors larger than barely yield any extra gain (and cost significantly more area). self-loading effect (intrinsic capacitance dominates) -545 Digital ICs CMOS Inverter 45 Impact of Fanout on Delay Extrinsic capacitance, C ext, is a function of the fanout of the gate the larger the fanout, the larger the external load. First determine the input loading effect of the inverter. Both C g and C int are proportional to the gate sizing, so C int = gc g is independent of gate sizing and t p = t p ( + C ext / gc g ) = t p ( + f /g) The delay of an inverter is a function of the ratio between its external load capacitance and its input gate capacitance: the effective fan-out f f = C ext /C g -545 Digital ICs CMOS Inverter 46 Inverter Chain Goal: to minimize the delay through an inverter chain In C g, N The delay of the j-th inverter stage is t p,j = t p ( + C g,j+ /(gc g,j )) = t p ( + f j / g) Overall Delay: t p = Ât p,j = t p  ( + C g,j+ /(gc g,j )) If is given How should the inverters be sized? How many stages are needed to minimize the delay? Out -545 Digital ICs CMOS Inverter 47 Sizing the Inverters in the Chain The optimum size of each inverter is the geometric mean of its neighbors meaning that if each inverter is sized up by the same factor f wrt the preceding gate, it will have the same effective fan-out and the same delay f = N N C g, = F where F represents the overall effective fan-out of the circuit (F = /C g, ) The minimum delay through the inverter chain is t p = Nt p + N ( F /g) The relationship between t p and F is linear for one inverter, suare root for two, etc. -545 Digital ICs CMOS Inverter 48-545 Digital ICs
July 5th, 4 Example: Inverter Chain Sizing In C g, f = f = 4 /C g, has to be evenly distributed over N = 3 inverters /C g, = 8/ f = 3 8 = Out = 8 C g, -545 Digital ICs CMOS Inverter 49 Determining N: Optimal Number of Inverters What is the optimal value for N given F (=f N )? If the number of stages is too large, the intrinsic delay of the stages becomes dominate If the number of stages is too small, the effective fan-out of each stage becomes dominate The optimum N is found by differentiating the minimum delay expression divided by the number of stages and setting the result to, giving N N g + F - ( F lnf)/n = For g = (ignoring self-loading) N = ln (F) and the effective-fan out becomes f = e =.788 For g = (the typical case) the optimum effective fan-out (tapering factor) turns out to be close to 3.6-545 Digital ICs CMOS Inverter 5 Optimum Effective Fan-Out Example: Inverter (Buffer) Staging Fopt 5 4.5 4 3.5 3.5.5.5.5 3 g.5.5 3 3.5 4 4.5 5 f Choosing f larger than optimum has little effect on delay and reduces the number of stages (and area). Common practice to use f = 4 (for g = ) But too many stages has a substantial negative impact on delay -545 Digital ICs CMOS Inverter 5 Normalized Delay 7 6 5 4 3 C g, = = 64 C g, 8 C g, = = 64 C g, 4 6 C g, = = 64 C g,.8 8.6 C g, = = 64 C g, N f t p 64 65 8 8 3 4 5 4.8 5.3-545 Digital ICs CMOS Inverter 5-545 Digital ICs 3
July 5th, 4 Impact of Buffer Staging for Large F (g = ),, Unbuffered, Two Stage Chain 8.3 4.8 33. Impressive speed-ups with optimized cascaded inverter chain for very large capacitive loads. -545 Digital ICs CMOS Inverter 53 65 Opt. Inverter Chain 8.3 6.5 Input Signal Rise/Fall Time In reality, the input signal changes gradually (and both PMOS and NMOS conduct for a brief time). This affects the current available for charging/discharging and impacts propagation delay. t p increases linearly with increasing input slope, t s, once t s > t p t s is due to the limited driving capability of the preceding gate -545 Digital ICs CMOS Inverter 54 tp(psec) 54 5 5 48 46 44 4 4 38 36 t s = input signal slope 4 6 8 t S (psec) for a minimum-size inverter with a fan-out of a single gate Design Challenge A gate is never designed in isolation: its performance is affected by both the fan-out and the driving strength of the gate(s) feeding its inputs. (Revised t p expression) t i p = ti step + h ti- step (h ª.5) Keep signal rise times smaller than or eual to the gate propagation delays. good for performance good for power consumption Keeping rise and fall times of the signals small and of approximately eual values is one of the major challenges in high-performance designs - slope engineering. -545 Digital ICs CMOS Inverter 55 Delay with Long Interconnect When gates are farther apart, wire capacitance and resistance can no longer be ignored. c int (r w, c w, L) t p =.69R dr C int + (.69R dr +.38R w )C w +.69(R dr +R w )C fan where R dr = (R en + R ep )/ Wire delay rapidly becomes the dominant factor (due to the uadratic term) in the delay budget for longer wires. -545 Digital ICs CMOS Inverter 56 c fan t p =.69R dr (C int +C fan ) +.69(R dr c w +r w C fan )L +.38r w c w L -545 Digital ICs 4
July 5th, 4 Where Does Power Go? Static Power Consumption Ideally zero for static CMOS but in the real world.. Leakage Current Loss Diodes and Transistors constantly losing charge Dynamic Power Consumption Charging/Discharging Capacitances Major Source of Power Dissipation in CMOS Circuits Direct-Path Current Loss Short circuit between Power Rail during Switching -545 Digital ICs CMOS Inverter 57 Dynamic Power Consumption Energy Supplied/Cycle = Energy Stored/Cycle = i VDD (t) P dyn = Energy/cycle * f clk -545 Digital ICs CMOS Inverter 58 Ú i VDD (t) dt = * V DD Ú i VDD (t)v out (t)dt = * V DD / = * * f clk Switching Activity Power dissipation does not depend on the size of the devices but depends on how often the circuit is switched. Switching Activity freuency of energy-consuming transition = f Æ Clock Gate output P dyn = * * f Æ = * * P Æ * f clk = C eff * * f clk Lowering Dynamic Power Lowering Physical Capacitance Capacitance: Function of fan-out, wire length, transistor sizes Activity factor: How often, on average, do gates switch? P dyn = P Æ f Quadratic Effect Supply Voltage: Has been dropping with successive generations Clock freuency: Increasing P Æ =.5, f Æ = f clk / 4 Effective Capacitance C eff = Average Capacitance Switched per clock cycle Reduction can be obtained only at Logic and Architectural Abstraction Levels -545 Digital ICs CMOS Inverter 59-545 Digital ICs CMOS Inverter 6-545 Digital ICs 5
I peak (A) July 5th, 4 Short Circuit Power Consumption Short Circuit Currents Determinates t sc E sc = t sc I peak P Æ I sc P sc = t sc I peak f Æ Finite slope of the input signal causes a direct current path between and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting (active). -545 Digital ICs CMOS Inverter 6 t sc = Duration of the slope of the input signal I peak determined by the saturation current of the PMOS and NMOS transistors which depend on their sizes, process technology, temperature, etc. strong function of the ratio between input and output slopes a function of -545 Digital ICs CMOS Inverter 63 Impact of on P sc I peak as a Function of I sc ª Large capacitive load Output fall time significantly larger than input rise time. I sc ª I max Small capacitive load -545 Digital ICs CMOS Inverter 64 Output fall time substantially smaller than input rise time. x -4.5.5.5 4 6 -.5 x - time (sec) 5 psec input slope = ff = ff = 5 ff When load capacitance is small, I peak is large. Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering. -545 Digital ICs CMOS Inverter 65-545 Digital ICs 6
July 5th, 4 P sc as a Function of Rise/Fall Times Static (Leakage) Power Consumption P normalized 8 7 6 5 4 3 = 3.3 V =.5 V 3 4 5 t sin /t sout W/L p =.5 mm/.5 mm W/L n =.375 mm/.5 mm = 3 ff =.5V When load capacitance is small (t sin /t sout > for > V) the power is dominated by P sc If < V Tn + V Tp then P sc is eliminated since both devices are never on at the same time. normalized wrt zero input rise-time dissipation -545 Digital ICs CMOS Inverter 66 Gate leakage VDD = P stat = I stat Drain junction leakage Sub-threshold current dominant factor. All leakages increase exponentially with temperature Junction leakage doubles every 9C Sub-threshold current becomes more concern in vdsm The closer the threshold voltage to zero, the larger the leakage current at V GS = V (when NMOS off) -545 Digital ICs CMOS Inverter 67 Leakage as a Function of V T Continued scaling of supply voltage and the subseuent scaling of threshold voltage will make sub-threshold conduction a dominant component of power dissipation. ID (A).E-.E-4.E-6.E-8.E-.E-..4.6.8 V GS (V) VT=.4V VT=.V An 9mV/decade V T roll-off - so each 55mcrease in V T gives 3 orders of magnitude reduction in leakage (but adversely affects performance) -545 Digital ICs CMOS Inverter 68 TSMC Processes Leakage and VT From MPR, June, pp. 9 Performance of various TSMC processes (G generic, LP low power, ULP ultra low power, HS high speed) V dd T ox (effective) L gate I DSat (n/p) (ma/mm) I off (leakage) (ra/mm) V Tn FET Perf. (GHz) CL8 G.8 V 4 Å.6 mm 6/6.4 V 3 CL8 LP.8 V 4 Å.6 mm 5/8.6.63 V CL8 ULP.8 V 4 Å.8 mm 3/3.5.73 V 4 Å CL5 HS.5 V 9 Å. mm 86/37,8.9 V CL3 HS. V 4 Å.8 mm 9/4 3,.5 V -545 Digital ICs CMOS Inverter 69 4 CL8 HS V.3 mm 78/36 3.4 V 43 5 8-545 Digital ICs 7
July 5th, 4 Exponential Increase in Leakages Energy and Power Euations Ileakage(nA/mm) Leakage currents double every degree increase in temperature 3 4 5 6 7 8 9 Temperature (C). mm.3 mm.8 mm.5 mm The Leakage Power is six orders of magnitude smaller than the dynamic power (at room temperature) -545 Digital ICs CMOS Inverter 7 E = P Æ + t sc I peak P Æ + I leakage T clock Dynamic power (~9% today and decreasing relatively) f Æ = P Æ * f clock P = f Æ + t sc I peak f Æ + I leakage Short-circuit power (~8% today and decreasing absolutely) Leakage power (~% today and increasing) -545 Digital ICs CMOS Inverter 7 Sizing for Minimum Energy In C g Goal: Minimize Energy of the whole circuit Design parameters: f and t p t pref of circuit with f = and = V ref Overall Effective Fan-out F = C ext /C g Ê Ê t p = t p + f ˆ Á Ë g + Ê + F ˆ ˆ Á Á Ë fg Ë -545 Digital ICs CMOS Inverter 7 f Out C ext Intrinsic Delay of the inverter t p ~ t /(t - V TE ) Sizing for Minimum Energy II Performance Constraint (g=) t p t pref = t p t pref Ê + f + F ˆ Á Ë f ( 3 + F) = V ref Energy for single Transition E = V DD C g + g E E ref Ê + f + F ˆ Á V ref -V TE Ë f = -V TE ( 3 + F) [( )( + f ) + F] = V Ê ˆ Ê DD + f + F ˆ Á Ë V Á ref Ë 4 + F -545 Digital ICs CMOS Inverter 73-545 Digital ICs 8
July 5th, 4 Sizing for Minimum Energy III (V) 4 3.5 3.5.5.5 F= 3 4 5 6 7 f 5 3 4 5 6 7-545 Digital ICs CMOS Inverter 74 E/E ref Optimum sizing occurs at f opt = F Increasing device sizes beyond f opt increase self-loading factor Deteriorate performance and reuire increase in supply voltage.5.5 f Observation V Device sizing, combined with supply voltage reduction, is very effective in reducing the energy consumption For F =, minimum size device is the most effective For network with large effective fan-out (F >> ), a large reduction factor of almost can be obtained. Oversizing transistors beyond the optimal value results in a hefty increase of energy Unfortunately, a common approach in many today s design Optimal sizing factor for energy is smaller than the one for performance (delay), especially for large F For a fan-out of, f opt (energy) = 3.53, f opt (delay) = 4.47-545 Digital ICs CMOS Inverter 75 Power-Delay and Energy-Delay Product Power-delay product (PDP) = P av * t p = ( )/ PDP is the average energy consumed per switching event (Watts * sec = Joule) Lower power design could simply be a slower design Energy-delay product (EDP) = PDP * t p = P av * t p EDP is the average energy consumed multiplied by the computation time reuired Takes into account that one can trade increased delay for lower energy/operation (e.g., via supply voltage scaling that increases delay, but decreases energy consumption) -545 Digital ICs CMOS Inverter 76 Energy-Delay Plot Energy-Delay (normalized) 5 5 Energy Energy-Delay. V.5.5.5 V dd (V).5 micron Delay V Tn =.43 V, V DSATn =.63 V, V TEn =.74 V V Tp = -.4 V, V DSATp = - V, V TEp = -.9 V ac 3 EDP = L -V TE ( ) Where V TE = V T +V DSAT / opt = 3 V TE V TE (V Tn + V Tp )/ =.8 V opt = (3/)*.8 =. V -545 Digital ICs CMOS Inverter 77-545 Digital ICs 9
July 5th, 4 Observation VI Voltage Dependence of the EDP Higher Supply Voltages reduce delay, but harm the energy. Vice Versa for low voltages opt simultaneously optimizes performance (delay) and energy For submicron technologies with V T in the range of.5 V, opt ~ V. opt does not necessarily represent the optimum voltage for a given design problem Goal of the design (speed or power) determinates the supply voltage -545 Digital ICs CMOS Inverter 78 Goals of Technology Scaling Make things cheaper: Want to sell more functions (transistors) per chip for the same money Build same products cheaper, sell the same part for less money Price per transistor has to be reduced But also want to be faster, smaller, lower power -545 Digital ICs CMOS Inverter 79 Technology Scaling Goals of scaling the dimensions by 3%: Reduce gate delay by 3% (increase operating freuency by 43%) Double transistor density Reduce energy per transition by 65% (5% power savings @ 43% increase in freuency Die size used to increase by 4% per generation Technology generation spans -3 years Technology Evolution (ITRS) International Technology Roadmap for Semiconductors (ITRS) (http://public.itrs.net) Year of Introduction Technology node [nm] Supply [V] Wiring levels Max freuency [GHz],Local-Global Max mp power [W] Bat. power [W] 999 8.5-.8 6-7. 9.4.5-.8 6-7.6-.4 6.7 3.-.5 7.-.6 3. 4 9.9-. 8 3.5-6.4 8 6.6-.9 9 7.-.5 7. 4.5-.6 9- -3 77.3 4 3.3-.6 4.9-3.6 86.5 Node years: 7/65nm, /45nm, 3/33nm, 6/3nm -545 Digital ICs CMOS Inverter 8-545 Digital ICs CMOS Inverter 8-545 Digital ICs
July 5th, 4 Technology Evolution (999) Technology Scaling Models Full Scaling (Constant Electrical Field) Ideal model - dimensions and voltage scale together by the same factor S Fixed Voltage Scaling Most common until recently Only dimensions scale, voltages remain constant General Scaling Most realistic for todays situation Voltages and dimensions scale with different factors -545 Digital ICs CMOS Inverter 8-545 Digital ICs CMOS Inverter 83 Scaling Long Channel Devices Scaling Short Channel Devices -545 Digital ICs CMOS Inverter 84-545 Digital ICs CMOS Inverter 85-545 Digital ICs
July 5th, 4 Scaling Wire Capacitances Power Density vs. Scaling Factor S = Technology Scaling, U = Voltage Scaling, S L = Wire-length Scaling e c = impact of fringing and interwire capacitance Wire Delay Parameter Wire Capacitance Wire Energy Wire Delay/Intrinsic Delay Wire Energy/ Intrinsic Energy Relation WL/t R on C int C m V General Scaling e c /S L e c /S L e c /S L U e c S/S L e c S/S L Power Density (mw/mm ) µ k 3 µ k.7 Scaling Factor k?i normalized by 4mm design rule?j Power density increase approximately with S In correspondance with fixed-voltage scaling Recent Trend is more in line with Full-scaling Constant power density Accelerated scaling and more attention to powerreducing design techniues -545 Digital ICs CMOS Inverter 86-545 Digital ICs CMOS Inverter 87 Evolution of Wire Delay and Gate Delay How the ratio of wire over intrinsic contributions will actually evolve is debatable -545 Digital ICs CMOS Inverter 88 Looking into the Future (Year ) Performance X/6 months TIP (terra instructions/s) 3 GHz clock Size No of transistors: Billion Die: 4*4 mm Power kw!! Leakage: /3 active Power -545 Digital ICs CMOS Inverter 89-545 Digital ICs
July 5th, 4 Some Interesting Questions What will cause this model to break? When will it break? Will the model gradually slow down? Power and power density Leakage Process Variation -545 Digital ICs CMOS Inverter 9-545 Digital ICs 3