ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 10: February 16, 2016 MOS Inverter: Dynamic Characteristics

Lecture Outline! Review: Symmetric CMOS Inverter Design! Inverter Power! Dynamic Characteristics " Delay 2

Review: CMOS Inverter: Visual VTC -1 V out = V in - V T0p V th V T0p V out = V in - V T0n V th V th V T0n -V T0n V IL -1 V th V IH V DD 3

Review: CMOS Inverter: Visual VTC -1 V out = V in - V T0p V th V T0p V out = V in - V T0n V th V th V T0n -V T0n V IL -1 V th V IH V DD 4

Review: CMOS Inverter: Design/Sizing V th = V T 0n + 1 k R 1+ ( V DD +V T 0 p ) 1 k R " k R = V +V V DD T 0 p th $ # V th % ' & 2 Important design Eq. for CMOS inverter VTC. If V th is set to ideal case: V th = 1 2 V DD " k R = V +V 1 2V % DD T 0 p DD $ ' # 1 2V DD & 2 " = 1 2V +V % DD T 0 p $ ' # 1 2V DD & If V T0n = -V T0p = -V T0 (symmetric CMOS) 2 ideal V th " k R = V +V 1 2V DD T 0 p DD $ 1 2V DD If, # also % ' & 2 " = 1 2V +V DD T 0 $ # 1 2V DD +V T 0 % ' & 2 k R symetric = 1 =1 1= µ W n n W p = µ n µ p W p W n µ p 5

Review: Noise Margin Example Compute the noise margins for a symmetric CMOS inverter has been designed to achieve V th = V DD /2, where V DD = 5 V and V T0n = - V T0p = 1 V. NM H = NM L = 2.125 RECALL (with V DD = 5 V) 1. NM H, NM L > V DD /4 = 1.25 V 2. Ideal NM => NM H = NM L = 2.5 V > V DD /2 6

Inverter Power

Power! P = I V! Tricky part: " Understanding I " (pairing with correct V) 8

Static Current! P = I static V DD 9

Switching Currents! Dynamic current flow:! If both transistor on: " Current path from V dd to Gnd " Short circuit current 10

Currents Summary! I changes over time! At least two components " I static no switching " I switch when switching " I dyn and I sc 11

Currents Summary! I changes over time! At least two components " I static no switching " I switch when switching " I dyn and I sc CLK φ ramp_enable V RAMP 12

Switching Dynamic Power 13

Switching Currents! I switch (t) = I sc (t) + I dyn (t)! I(t) = I static (t)+i switch (t) I dyn I static I sc 14

Charging! I dyn (t) " I ds = f(v ds,v gs ) " and V gs, V ds changing I DS = k n ( 2 V GS V ) 2 T I DS = k n " # 2 2 V V GS T ( 2 )V DS V DS $ % 15

Switching Energy focus on I dyn (t) I dyn I static I sc 16

Switching Energy focus on I dyn (t) I dyn E = P(t)dt = I(t)V dd dt = V dd I(t)dt 17

Switching Energy! Do we know what this is? I dyn (t)dt I dyn E = P(t)dt = I(t)V dd dt = V dd I(t)dt 18

Switching Energy! Do we know what this is? Q = I dyn (t)dt I dyn E = P(t)dt = I(t)V dd dt = V dd I(t)dt 19

Switching Energy! Do we know what this is? Q = I dyn (t)dt! What is Q? I dyn E = P(t)dt = I(t)V dd dt = V dd I(t)dt 20

Switching Energy! Do we know what this is? Q = I dyn (t)dt! What is Q? I dyn E = P(t)dt Q = CV = I(t)dt = I(t)V dd dt = V dd I(t)dt 21

Switching Energy! Do we know what this is? Q = I dyn (t)dt! What is Q? I dyn E = P(t)dt Q = CV = I(t)dt = I(t)V dd dt = V dd I(t)dt E = CV dd 2 Capacitor charging energy 22

Switching Power! Every time output switches 0#1 pay: " E = CV 2! P dyn = (# 0#1 trans) CV 2 / time! # 0#1 trans = ½ # of transitions! P dyn = (# trans) ½CV 2 / time 23

Switching Short Circuit Power 24

Short Circuit Power! Between V TN and V dd - V TP " Both N and P devices conducting! Roughly: I sc 25

Peak Current! I peak around V dd /2 " If V TN = V TP and sized equal rise/fall I DS = k n ( 2 V GS V T ) 2 26

Peak Current! I peak around V dd /2 " If V TN = V TP and sized equal rise/fall I DS = k n ( 2 V GS V T ) 2 I(t)dt I t % ' 1( peak sc & 2 * ) 27

Peak Current! I peak around V dd /2 " If V TN = V TP and sized equal rise/fall I DS = k n ( 2 V GS V T ) 2 I(t)dt I t % ' 1( peak sc & 2 * ) # E = V dd I peak t sc % 1& ( $ 2' 28

Dynamic Characteristics 29

Inverter Delay! Caused by charging and discharging the capacitive load " What is the load? 30

Inverter Delay 31

Inverter Delay 32

Inverter Delay C gb = C gbn + C gbp C load = C # dbn + C# dbp + C# gdn + C# gdp + C int + C gb 33

Inverter Delay Usually C db >> C gd C sb >> C gs C load C # dbn + C# dbp + C int + C gb 34

Inverter Delay n = fan-out 1 C load C dbn + C dbp + C int + nc gb 35

Propogation Delay Definitions V DD 0 t V DD 0 V 50% = V DD /2 36

Propogation Delay Definitions t 37

Propogation Delay Definitions 38

Rise/Fall Times 39

MOS Inverter Dynamic Performance! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C load, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C load*, determine the MOS inverter schematic METHODS: 1. Average Current Model τ PHL C load ΔV HL I avg,hl = C load V OH V 50% I avg,hl τ PLH C load ΔV LH I avg,lh = C load V 50% V OL I avg,lh Assume V in ideal 40

MOS Inverter Dynamic Performance! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C load, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C load*, determine the MOS inverter schematic METHODS: 2. Differential Equation Model i C = C load dv out dt dv dt = C out load i C dt τ PHL or τ PLH Assume V in ideal 41

MOS Inverter Dynamic Performance! ANALYSIS (OR SIMULATION): For a given MOS inverter schematic and C load, estimate (or measure) the propagation delays! DESIGN: For given specs for the propagation delays and C load*, determine the MOS inverter schematic METHODS: 3. 1 st Order RC delay Model τ PHL 0.69 C load R n τ PLH 0.69 C load R p Assume V in ideal 42

Method 1 Average Current Model

Calculation of Propagation Delays τ PHL C load ΔV HL I avg,hl = C load V OH V 50% I avg,hl τ PLH C load ΔV LH I avg,lh = C load V 50% V OL I avg,lh 44

Calculation of Propagation Delays τ PHL C load ΔV HL I avg,hl = C load V OH V 50% I avg,hl τ PLH C load ΔV LH I avg,lh = C load V 50% V OL I avg,lh 45

Calculation of Propagation Delays τ PHL C load ΔV HL I avg,hl = C load V OH V 50% I avg,hl τ PLH C load ΔV LH I avg,lh = C load V 50% V OL I avg,lh 46

Calculation of Rise/Fall Times τ fall C load ΔV 90% 10% I avg,90% 10% = C load V 90% V 10% I avg,90% 10% τ rise C load ΔV 10% 90% I avg,10% 90% = C load V 90% V 10% I avg,10% 90% 47

Calculation of Rise/Fall Times τ fall C load ΔV 90% 10% I avg,90% 10% = C load V 90% V 10% I avg,90% 10% τ rise C load ΔV 10% 90% I avg,10% 90% = C load V 90% V 10% I avg,10% 90% 48

Calculation of Rise/Fall Times τ fall C load ΔV 90% 10% I avg,90% 10% = C load V 90% V 10% I avg,90% 10% τ rise C load ΔV 10% 90% I avg,10% 90% = C load V 90% V 10% I avg,10% 90% 49

Method 2 Differential Equation Model

Calculating Propagation Delays Assume V in is an ideal step-input Two Cases 1. V in abruptly rises => V out falls => τ PHL 2. V in abruptly falls => V out rises => τ PLH i DP - i Dn 51

Case 1: V in Abruptly Rises - τ PHL 52

Case 1: V in Abruptly Rises - τ PHL 53

Case 1: V in Abruptly Rises - τ PHL 54

Case 1: V in Abruptly Rises - τ PHL 55

Case 1: V in Abruptly Rises - τ PHL V out = V DD V T0n 56

Recall: CMOS Inverter: Visual VTC -1 V out = V in - V T0p V th V T0p V out = V in - V T0n V th V th V T0n -V T0n V IL -1 V th V IH V DD 57

Case 1: V in Abruptly Rises - τ PHL C load dv out dt i Dn τ PHL = τ PHL =C load dv dt = C out load i Dn t=t 50% V out =V DD /2$ 1' dt = C t=t load & ) 0 V out =V DD % ( i Dn dv out V DD V T 0 n $ 1' V DD /2 $ 1' & ) dv V out + C load & DD ) V % ( DD V T 0 n % ( i Dn t 0 #t 1 t 1 #t 50% i Dn dv out V out = V DD V T0n 58

Case 1: V in Abruptly Rises - τ PHL saturation linear τ PHL =C load t 0 #t 1 t 1 #t 50% V DD V T 0 n " 1% V DD /2 " 1% $ ' dv V out + C load $ DD ' V # & DD V T 0 n # & i Dn i Dn dv out V out = V DD V T0n saturation: i Dn = k n 2 (V in )2 τ PHL,sat = C load τ PHL,sat = V DD V T 0 n V DD " $ $ $ # C load 1 k n 2 (V DD ) 2 % ' ' ' & dv k n 2 (V V V out DD DD T 0n )2 V DD V T 0 n dv out τ PHL,sat = 2C load V T 0n k n (V DD ) 2 59

Case 1: V in Abruptly Rises - τ PHL saturation linear τ PHL =C load t 0 #t 1 t 1 #t 50% V DD V T 0 n " 1% V DD /2 " 1% $ ' dv V out + C load $ DD ' V # & DD V T 0 n # & i Dn i Dn dv out V out = V DD V T0n ( ) linear: i Dn = k n 2 (V V )V V 2 in T 0n out out " V DD /2 $ 1 τ PHL,lin = C load $ V DD V T 0 n $ k n 2 2(V DD )V out V 2 out # τ PHL,lin = 2C " V load DD /2 1 V k n $ # 2(V DD )V out V 2 DD V T 0 n out τ PHL,lin = 2C load k n ( ) ( ) 1 2(V DD ) ln " V out $ # 2(V DD ) V out ( ) % ' ' ' & % ' & % ' & dv out dv out V out =V DD /2 V out =V DD V T 0 n 60

Case 1: V in Abruptly Rises - τ PHL τ PHL,lin = 2C load k n τ PHL,lin = 1 2(V DD ) ln # V out % $ 2(V DD ) V out ( ) # C load k n (V DD ) ln 2(V DD ) V DD 2 % V DD 2 $ & ( ' V out =V DD /2 V out =V DD V T 0 n & ( ' 61

Case 1: V in Abruptly Rises - τ PHL saturation linear τ PHL =C load t 0 #t 1 t 1 #t 50% V DD V T 0 n " 1% V DD /2 " 1% $ ' dv V out + C load $ DD ' V # & DD V T 0 n # & i Dn i Dn dv out V out = V DD V T0n τ PHL,sat = 2C load V T 0n k n (V DD ) 2 τ PHL,lin = " C load k n (V DD ) ln 2(V DD ) V DD 2 $ V DD 2 # % ' & τ PHL = 2C load V T 0n k n (V DD ) 2 + " C load k n (V DD ) ln 2(V DD ) V DD 2 $ V DD 2 # % ' & 62

Case 1: V in Abruptly Rises - τ PHL saturation linear τ PHL =C load t 0 #t 1 t 1 #t 50% V DD V T 0 n " 1% V DD /2 " 1% $ ' dv V out + C load $ DD ' V # & DD V T 0 n # & i Dn i Dn dv out V out = V DD V T0n τ PHL,sat = 2C load V T 0n k n (V DD ) 2 τ PHL,lin = τ PHL = 2C load V T 0n k n (V DD ) 2 + " C load k n (V DD ) ln 2(V DD ) V DD 2 $ V DD 2 " # C load k n (V DD ) ln 2(V DD ) V DD 2 $ V DD 2 # % ' & % ' & 63

Case 1: V in Abruptly Rises - τ PHL saturation linear τ PHL =C load t 0 #t 1 t 1 #t 50% V DD V T 0 n " 1% V DD /2 " 1% $ ' dv V out + C load $ DD ' V # & DD V T 0 n # & i Dn i Dn dv out V out = V DD V T0n τ PHL,sat = 2C load V T 0n k n (V DD ) 2 τ PHL,lin = " C load k n (V DD ) ln 2(V DD ) V DD 2 $ V DD 2 # % ' & τ PHL = 2C load V T 0n k n (V DD ) 2 + " C load k n (V DD ) ln 2(V DD ) V DD 2 $ V DD 2 1 ) 2V τ PHL =C load T 0n k n (V DD ) (V DD ) + ln # 2(V V ) &, DD T 0n + % 1(. * $ V DD 2 '- # % ' & R n 64

Case 1: V in Abruptly Rises - τ PHL 1 ) 2V τ PHL =C load T 0n k n (V DD ) (V DD ) + ln # 2(V V ) &, DD T 0n + % 1(. * $ V DD 2 '- Recall from static CMOS Inverter: V th = V T 0n + 1 k R 1+ ( V DD +V T 0 p ) 1 k R " k R = V DD +V T 0 p V th $ # V th % ' & 2 DESIGN: (1) V th k R ; (2) τ PHL k n ; (3) k R & k n k p 65

Idea! P tot = P static + P dyn + P sc " Can t ignore Static Power (aka. Leakage power)! Propogation Delay " Average Current Model " Differential Equation Model " 1 st Order Model 66

Admin! HW 4 due Thursday, 2/18 " If you submit online and in-class only the online one will be graded.! Tania Office Hours on Wednesday 2-4pm! Journal Thursday " Gregory Fredeman, et. al., A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access, pp 230-239 67