EE 330 Lecture 36 Digital Circuits Transfer Characteristics of the Inverter Pair One device sizing strategy Multiple-input gates
Review from Last Time The basic logic gates It suffices to characterize the inverter of a logic family and then express the performance of other gates in that family in terms of the performance of the inverter. What characteristics are required and desirable for an inverter to form the basis for a useful logic family?
Review from Last Time Ask the inverter how it will interpret logic levels IN Inverter pair OUT L TRIP H When OUT =, H and L are stable operating points, TRIP is a quasi-stable operating point Observe: slope of IPTC is greater than 1 at TRIP and less than 1 at H and L
Review from Last Time Observation OUT When = for the inverter, OUT is also equal to. Thus the intersection point for = in the inverter transfer characteristics (ITC) is also an intersection point for OUT = in the inverter-pair transfer characteristics (IPTC) 1 1 OUT 1 1 TRIP L TRIP H Implication: Inverter characteristics can be used directly to obtain TRIP
Review from Last Time Logic Family Characteristics What properties of an inverter are necessary for it to be useful for building a two-level logic family? The inverter-pair transfer characteristics must have three unique intersection points with the OUT = line What are the logic levels for a given inverter of for a given logic family? The two extreme intersection points of the inverter-pair transfer characteristics with the OUT = line OUT 1 1 Can we legislate H and L for a logic family? No! What other properties of the inverter are desirable? L TRIP H Reasonable separation between H and L (enough separation so that noise does not cause circuit to interpret level incorrectly) TRIP + H 2 L (to provide adequate noise immunity and process insensitivity)
What are the transfer characteristics of the static CMOS inverter pair? OUT Consider first the inverter
M 2 M 1
M 2 M 1
Case 1 M 1 triode, M 2 cutoff W L 2 1 OUT I μ C D1 n OXn IN Tn OUT ID2 0 Equating I D1 and I D2 we obtain: 1 W L 2 1 OUT 0 μ C n OXn IN Tn OUT 1 It can be shown that setting the first product term to 0 will not verify, thus M 2 M 1 OUT 0 valid for: GS1 Tn DS1 GS1 Tn thus, valid for: IN Tn OUT IN Tn IN DD Tp GS2 Tp
Graphical Interpretation of these conditions: IN Tn OUT IN Tn IN DD Tp
Case 1 OUT 0 M 1 triode, M 2 cutoff IN Tn M 1 CO OUT IN Tn M 2 CO - Tp M 1 SAT M 1 TR IN DD Tp - Tn + Tp
Case 1 OUT 0 M 1 triode, M 2 cutoff IN Tn M 1 CO OUT IN Tn M 2 CO - Tp M 1 SAT M 1 TR IN DD Tp - Tn + Tp
Partial solution: Case 1 - Tp - Tn + Tp
Case 2 M 1 triode, M 2 sat M 2 TR M 2 CO M 1 CO M 2 SAT - Tp M 1 SAT M 1 TR - Tn + Tp
Case 1 OUT 0 M 1 triode, M 2 cutoff IN Tn M 1 CO OUT IN Tn M 2 CO - Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
Partial solution: Case 1 - Tp Tn + Tp
Regions of Operation for Devices in CMOS inverter M 2 M 1 M 2 TR M 2 CO M 1 CO M 2 SAT - Tp M 1 SAT M 1 TR - Tn + Tp
Case 2 M 1 triode, M 2 sat M 2 TR M 2 CO M 1 CO M 2 SAT - Tp M 1 SAT M 1 TR Tn + Tp
Case 2 M 1 triode, M 2 sat W L 2 1 μc p OXp W2 I 2 L 1 OUT I μ C D1 n OXn IN Tn OUT Equating I D1 and I D2 we obtain: 2 D2 IN DD Tp 2 μc p OXp W W 2 2 1 OUT μ C 2 L L 2 IN DD Tp n OXn IN Tn OUT 2 1 M 2 M 1 valid for: - GS1 Tn DS1 GS1 Tn GS2 Tp DS2 GS2 T2 thus, valid for: - - - IN Tn OUT IN Tn IN DD Tp OUT DD IN DD Tp
Case 2 M 1 triode, M 2 sat - - - OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT OUT IN Tn - Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
Case 2 M 1 triode, M 2 sat - - - OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT OUT IN Tn - Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
Partial solution: Case 2 Case 1 - Tp Tn + Tp
Case 3 M 1 sat, M 2 sat M 2 TR M 2 CO M 1 CO M 2 SAT - Tp M 1 SAT M 1 TR Tn + Tp
Case 3 M 1 sat, M 2 sat μc W n OXn 1 I 2 D1 IN Tn 2 L1 μc p OXp W2 I 2 L 2 D2 IN DD Tp Equating I D1 and I D2 we obtain: 2 μc W μc W 2 L 2 L IN DD Tp IN Tn 2 2 p OXp 2 n OXn 1 2 1 Which can be rewritten as: μc W μc W 2 L 2 L + DD Tp IN IN Tn p OXp 2 n OXn 1 IN 2 1 Which can be simplified to: μc W μc W 2 L 2 L p OXp + n OXn 1 2 Tn DD Tp 1 2 μc W μc W 2 L 2 L n OXn 1 p OXp 2 1 2 M 2 M 1 This is a vertical line
Case 3 M 1 sat, M 2 sat IN Since IN valid for: μc W μc W 2 L 2 L p OXp + n OXn 1 2 Tn DD Tp C C =C OXn OXp OX 1 2 μc W μc W 2 L 2 L n OXn 1 p OXp 2 W L 1 2 this can be simplified to: p + 1 2 Tn DD Tp 1 n 2 W L μ W μ L 1 p 2 1 n 2 GS1 Tn DS1 GS1 Tn thus, valid for: μ W μ L M 2 M 1 - GS2 Tp DS2 GS2 T2 - - - IN Tn OUT IN Tn IN DD Tp OUT DD IN DD Tp
Case 3 M 1 sat, M 2 sat - - - OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT OUT IN Tn - Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
Case 3 M 1 sat, M 2 sat - - - OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT OUT IN Tn - Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
Partial solution: Case 3 Case 2 Case 1 - Tp Tn + Tp
Case 4 M 1 sat, M 2 triode M 2 TR M 2 CO M 1 CO M 2 SAT - Tp M 1 SAT M 1 TR Tn + Tp
Case 4 M 1 sat, M 2 triode μc W n OXn 1 I 2 D1 IN Tn 2 L1 W2 - OUT DD I μ C - L 2 D2 p OXp IN DD Tp OUT DD 2 Equating I D1 and I D2 we obtain: μ C W W - 1 2 2 L L 2 2 μ C - n OXn OUT DD IN Tn p OXp IN DD Tp OUT DD 1 2 M 2 M 1 valid for: - GS1 Tn DS1 GS1 Tn GS2 Tp DS2 GS2 T2 thus, valid for: - - - IN Tn OUT IN Tn IN DD Tp OUT DD IN DD Tp
Case 4 M 1 sat, M 2 triode - - - OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT OUT IN Tn - Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
Case 4 M 1 sat, M 2 triode - - - OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT OUT IN Tn - Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
Partial solution: Case 4 Case 3 Case 2 Case 1 - Tp Tn + Tp
Case 4 M 1 cutoff, M 2 triode M 2 TR M 2 CO M 1 CO M 2 SAT - Tp M 1 SAT M 1 TR Tn + Tp
Case 5 M 1 cutoff, M 2 triode ID1 0 W2 - OUT DD I μ C - L 2 D2 p OXp IN DD Tp OUT DD Equating I D1 and I D2 we obtain: valid for: GS1 2 W2 - OUT DD μ C p OXp - 0 IN DD Tp OUT DD L 2 2 - Tn GS2 Tp DS2 GS2 T2 M 2 M 1 thus, valid for: IN Tn - - - IN DD Tp OUT DD IN DD Tp
Case 5 M 1 cutoff, M 2 triode - - - OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT - Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
Case 5 M 1 cutoff, M 2 triode - - - OUT DD IN DD Tp M 2 TR M 2 CO IN Tn M 1 CO M 2 SAT - Tp M 1 SAT M 1 TR IN DD Tp Tn + Tp
Case 5 Case 4 M 2 Case 3 M 1 Case 2 Case 1 - Tp Tn + Tp
- Tp Tn + Tp
1 1 - Tp From Case 3 analysis: Tn TRIP IN Tn + DD Tp 1 μ W L μ W L p 2 1 n 1 2 μ W L μ W L p 2 1 n 1 2 DD+Tp
Inverter Transfer Characteristics of Inverter Pair OUT What are H and L? OUT L TRIP H Find the points on the inverter pair transfer characteristics where = and the slope is less than 1
Inverter Transfer Characteristics of Inverter Pair for THIS Logic Family OUT M 2 M 1 OUT DD 1 DD 1 1 1 -Tp -Tp -Tn TRIP DD -Tn TRIP DD DD+Tp DD+Tp H = and L =0 - Tp Note this is independent of device sizing for THIS logic family!! L - Tn + Tp TRIP H
Sizing of the Basic CMOS Inverter M 2 M 1 The characteristic that device sizes do not need to be used to establish H and L logic levels is a major advantage of this type of logic How should M 1 and M 2 be sized? How many degrees of freedom are there in the design of the inverter?
How should M 1 and M 2 be sized? M 2 M 1 How many degrees of freedom are there in the design of the inverter? { W 1,W 2,L 1,L 2 } 4 degrees of freedom But in basic device model and in most performance metrics, W 1 /L 1 and W 2 /L 2 appear as ratios { W 1 /L 1,W 2 /L 2 } effectively 2 degrees of freedom
How should M 1 and M 2 be sized? M 2 M 1 { W 1,W 2,L 1,L 2 } 4 degrees of freedom Usually pick L 1 =L 2 =L min { W 1 /L 1,W 2 /L 2 } effectively 2 degrees of freedom How are W 1 and W 2 chosen? Depends upon what performance parameters are most important for a given application!
How should M 1 and M 2 be sized? M 2 M 1 Usually pick L 1 =L 2 =L min { W 1 /L 1,W 2 /L 2 } 2 remaining degrees of freedom One popular sizing strategy: 1. Pick W 1 =W MIN to minimize area of M 1 2. Pick W 2 to set trip-point at /2
How should M 1 and M 2 be sized? pick L 1 =L 2 =L min One popular sizing strategy: 1. Pick W 1 =W MIN to minimize area of M 1 2. Pick W 2 to set trip-point at /2 M 2 M 1 Observe Case 3 provides expression for TRIP 1 Thus, at the trip point, - Tp Tn TRIP 1 = OUT IN TRIP Tn + DD Tp 1 μ W L μ W L p 2 1 n 1 2 μ W L μ W L p 2 1 n 1 2 DD+Tp
How should M 1 and M 2 be sized? pick L 1 =L 2 =L min One popular sizing strategy: 1. Pick W 1 =W MIN to minimize area of M 1 2. Pick W 2 to set trip-point at /2 M 2 M 1 Typically Tn =0.2, Tp =0.2 \ TRIP Tn + DD Tp 1 μ W L μ W L p 2 1 n 1 2 μ W L μ W L 0.2-0.2 DD 2 μ W 1 μ W DD DD DD p 2 n 1 p 2 1 n 1 2 μ W μ W p 2 n 1 Solving this equation for W 2, obtain μ W W μ n 2 1 Other sizing strategies are used as well and will be discussed later! p
Extension of Basic CMOS Inverter to Multiple-Input Gates A M 4 B M 1 M 2 M 3 Y A B Y 0 0 1 0 1 0 1 0 0 1 1 0 Truth Table Performs as a 2-input NOR Gate Can be easily extended to an n-input NOR Gate A B Y
Extension of Basic CMOS Inverter to Multiple-Input Gates A M 3 M 4 M 1 B M 2 Y A B Y 0 0 1 0 1 1 1 0 1 1 1 0 Truth Table Performs as a 2-input NAND Gate Can be easily extended to an n-input NAND Gate A B Y
Static CMOS Logic Family M 2 M 2 Pull-up Network PUN M 1 M 1 Pull-down Network PDN Observe PUN is p-channel, PDN is n-channel
Static CMOS Logic Family M 2 M 4 M 3 M 4 M 1 A M 3 Y A M 1 Y B M 1 M 2 B M 2 M 4 M 3 M 4 M 2 A M 3 Y Y A M 1 M 1 B M 1 M 2 B M 2 n-channel PDN and p-channel PUN H =, L =0 (same as for inverter!)
General Logic Family PUN PUN PDN PDN Compound Gate in CMOS Process p-channel PUN n-channel PDN H =, L =0 (same as for inverter!) Arbitrary PUN and PDN
Other MOS Logic Families M 2 M 2 M 2 M 1 M 1 M 1 Enhancement Load NMOS Enhancement Load Pseudo-NMOS Depletion Load NMOS
End of Lecture 36