ourse dministration PE/EE 47, PE 57 VLI esign I L6: omplementary MO Logic Gates epartment of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www.ece.uah.edu/~milenka ) www.ece.uah.edu/~milenka/cpe57-5f Instructor: leksandar Milenkovic milenka@ece.uah.edu www.ece.uah.edu/~milenka E 7-L Mon. 5:3 PM 6:3 PM, Wen. :3 3:3 PM URL: http://www.ece.uah.edu/~milenka/cpe57-5f T: Joel Wilder Labs: Lab# posted (due 9/3/5) Text: MO VLI esign, 3 rd ed., Weste, Harris Review: Introduction, esign Metrics, I Fabrication (Read hapter ); I Fabrication (hapter 3) Today: MO Non-ideal IV, MO Inverter (hapter ) 9/4/5 VLI esign I;. Milenkovic MO Inverter VT eta Ratio NMO off PMO res.5 NMO sat PMO res If β p / β n, switching point will move from / alled skewed gate Other gates: collapse into equivalent inverter (V).5 NMO sat PMO sat.5 NMO res PMO sat NMO res PMO off.5.5.5 β p. β = n β p β = n.5 (V) 9/4/5 VLI esign I;. Milenkovic 3 9/4/5 VLI esign I;. Milenkovic 4 Noise Margins How much noise can a gate input see before it does not recognize the input? Logic Levels To maximize noise margins, select logic levels at Logical High Output Range Output haracteristics Input haracteristics V OH NM H V IH Indeterminate V Region IL Logical High Input Range β p /β n > Logical Low Output Range V OL NM L Logical Low Input Range 9/4/5 VLI esign I;. Milenkovic 5 9/4/5 VLI esign I;. Milenkovic 6 VLI esign I;. Milenkovic
V OL Logic Levels MO Inverter: witch Model of ynamic ehavior To maximize noise margins, select logic levels at unity gain point of transfer characteristic R p Unity Gain Points V OH lope = - L L β p /β n > R n = = V tn V IL V V IH - V tp 9/4/5 VLI esign I;. Milenkovic 7 9/4/5 VLI esign I;. Milenkovic 8 MO Inverter: witch Model of ynamic ehavior Relative Transistor izing R p L R n L When designing static MO circuits, balance the driving strengths of the transistors by making the PMO section wider than the NMO section to maximize the noise margins and obtain symmetrical characteristics = = Gate response time is determined by the time to charge L through R p (discharge L through R n ) 9/4/5 VLI esign I;. Milenkovic 9 9/4/5 VLI esign I;. Milenkovic witching Threshold V M where = (both PMO and NMO in saturation since V = V G ) V M r /( + r) where r = k p V Tp /k n V Tn witching threshold set by the ratio r, which compares the relative driving strengths of the PMO and NMO transistors Want V M = / (to have comparable high and low noise margins), so want r (W/L) p k n V Tn (V M -V Tn -V Tn /) = (W/L) n k p V Tp ( -V M +V Tp +V Tp /) witch Threshold Example In our generic.5 micron MO process, using the process parameters from slide L3.5, a =.5V, and a minimum size NMO device ((W/L) n of.5) NMO PMO (W/L) p (W/L) n = V T (V).43 -.4 γ(v.5 ).4 -.4 V T (V).63 - k (/V ) 5 x -6-3 x -6 λ(v - ).6 -. 9/4/5 VLI esign I;. Milenkovic 9/4/5 VLI esign I;. Milenkovic VLI esign I;. Milenkovic
witch Threshold Example imulated Inverter V M In our generic.5 micron MO process, using the process parameters, a =.5V, and a minimum size NMO device ((W/L) n of.5) NMO PMO V T (V).43 -.4 γ(v.5 ).4 -.4 V T (V).63 - k (/V ) 5 x -6-3 x -6 λ(v - ).6 -. (W/L) p 5 x -6.63 (.5.43.63/) = x x (W/L) n -3 x -6 = 3.5 -. (.5.4./) (W/L) p = 3.5 x.5 = 5.5 for a V M of.5v V M (V).5.4.3...9.8. ~3.4 (W/L) p /(W/L) n Note: x-axis is semilog V M is relatively insensitive to variations in device ratio setting the ratio to 3,.5 and gives V M s of.v,.8v, and.3v Increasing the width of the PMO moves V M towards Increasing the width of the NMO moves V M toward 9/4/5 VLI esign I;. Milenkovic 3 9/4/5 VLI esign I;. Milenkovic 4 3 V OH = V OL = Noise Margins etermining V IH and V IL VIL V M piece-wise linear approximation of VT VIH y definition, V IH and V IL are where d /d = - (= gain) NM H = -V IH NM L = V IL - pproximating: V IH = V M -V M /g V IL = V M + ( -V M )/g o high gain in the transition region is very desirable 9/4/5 VLI esign I;. Milenkovic 5 (V).5.5.5 MO Inverter VT from imulation.5.5.5 (V).5um, (W/L) p /(W/L) n = 3.4 (W/L) n =.5 (min size) =.5V V M.5V, g = -7.5 V IL =.V, V IH =.3V NM L = NM H =. (actual values are V IL =.3V, V IH =.45V NM L =.3V & NM H =.5V) Output resistance low-output =.4kΩ high-output = 3.3kΩ 9/4/5 VLI esign I;. Milenkovic 6 gain - -4-6 -8 - - -4-6 -8.5.5 Gain eterminates Gain is a strong function of the slopes of the currents in the saturation region, for = V M (+r) g ---------------------------------- (V M -V Tn -V Tn /)(λ n - λ p ) etermined by technology parameters, especially channel length modulation (λ). Only designer influence through supply voltage and V M (transistor sizing). 9/4/5 VLI esign I;. Milenkovic 7 Impact of Process Variation on VT urve (V).5.5.5 ad PMO Good NMO.5.5.5 (V) Good PMO ad NMO Nominal process variations (mostly) cause a shift in the switching threshold 9/4/5 VLI esign I;. Milenkovic 8 VLI esign I;. Milenkovic 3
caling the upply Voltage.5..5 (V).5 (V).5 Gain=-.5..5..5 (V).5.5 (V) evice threshold voltages are evice threshold voltages are kept (virtually) constant kept (virtually) constant 9/4/5 VLI esign I;. Milenkovic 9..5 tatic MO Logic MO ircuit tyles tatic omplementary MO tatic complementary MO - except during switching, output connected to either V or via a lowresistance path high noise margins full rail to rail swing VOH and VOL are at V and, respectively low output impedance, high input impedance no steady state path between V and (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) ynamic MO - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes simpler, faster gates increased sensitivity to noise 9/4/5 VLI esign I;. Milenkovic Pull-up network () and pull-down network (PN) In In In N In In In N PN PMO transistors only pull-up: make a connection from to F when F(In,In, In N ) = F(In,In, In N ) pull-down: make a connection from F to when F(In,In, In N ) = NMO transistors only and PN are dual logic networks 9/4/5 VLI esign I;. Milenkovic Threshold rops Threshold rops V G -V Tn L L L L PN L L PN L V G L V Tp 9/4/5 VLI esign I;. Milenkovic 3 9/4/5 VLI esign I;. Milenkovic 4 VLI esign I;. Milenkovic 4
onstruction of PN NMO devices in series implement a NN function NMO devices in parallel implement a NOR function + ual and PN and PN are dual networks emorgan s theorems + = = + [!( + ) =!! or!( ) =! &!] [!( ) =! +! or!( & ) =!!] a parallel connection of transistors in the corresponds to a series connection of the PN omplementary gate is naturally inverting (NN, NOR, OI, OI) Number of transistors for an N-input logic gate is N 9/4/5 VLI esign I;. Milenkovic 5 9/4/5 VLI esign I;. Milenkovic 6 MO NN MO NN F NN F = NN(,) F = = F= = = F= = = F= = = F= 9/4/5 VLI esign I;. Milenkovic 7 9/4/5 VLI esign I;. Milenkovic 8 MO NOR MO NOR F NOR F = NOR(,) F + = = = = = F= = F= = F= = F= 9/4/5 VLI esign I;. Milenkovic 9 9/4/5 VLI esign I;. Milenkovic 3 VLI esign I;. Milenkovic 5
omplex MO Gate omplex MO Gate OUT =!( + ( + )) OUT =!( + ( + )) 9/4/5 VLI esign I;. Milenkovic 3 9/4/5 VLI esign I;. Milenkovic 3 NOR NOR/OR Implementation 9/4/5 VLI esign I;. Milenkovic 33 How many transistors in each? OR an you create the stick transistor layout for the lower left circuit? ombinational Logic ells MO logic cells N-OR-INVERT (OI) OR-N-INVERT(OI) Example: OI Z = (* + * + E) Z = OI(,,,, E) Exercise: onstruct this logic cell? Example: OI3 Z = [(++)*(+E)*F] Z = OI3(,,,, E, F) Exercise: onstruct this logic cell? OI nd Or Inverter 9/4/5 VLI esign I;. Milenkovic 34 E Z OI tandard ell Layout Methodology Routing channel E signals Z E 9/4/5 VLI esign I;. Milenkovic 35 What logic function is this? 9/4/5 VLI esign I;. Milenkovic 36 VLI esign I;. Milenkovic 6
OI Logic Graph Two tick Layouts of!( ( + )) j i =!( ( + )) i j PN uninterrupted diffusion strip 9/4/5 VLI esign I;. Milenkovic 37 9/4/5 VLI esign I;. Milenkovic 38 onsistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. onsistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. i i j j For a single poly strip for every input signal, the Euler paths in the and PN must be consistent (the same) 9/4/5 VLI esign I;. Milenkovic 39 For a single poly strip for every input signal, the Euler paths in the and PN must be consistent (the same) 9/4/5 VLI esign I;. Milenkovic 4 OI Logic Graph OI Layout =!((+) (+)) PN ome functions have no consistent Euler path like x =!(a + bc + de) (but x =!(bc + a + de) does!) 9/4/5 VLI esign I;. Milenkovic 4 9/4/5 VLI esign I;. Milenkovic 4 VLI esign I;. Milenkovic 7
ombinational Logic ells (cont d) The OI family of cells with 3 index numbers or less = {OI, OI, O, O}; a,b,c={,3} ell Type a a ab ab abc Total, 3, 3 ells, 33, 3, 3, 33, 333, 33, 3 Number of Unique ells 3 3 4 4 9/4/5 VLI esign I;. Milenkovic 43 V G = V V V G = V M 3 M 4 M M VT is ata-ependent F= int 9/4/5 VLI esign I;. Milenkovic 44 3 weaker.5µ/.5µ NMO.75µ /.5µ PMO,: -> =, : -> =, :-> The threshold voltage of M is higher than M due to the body effect (γ) V Tn = V Tn V Tn = V Tn + γ( ( φ F + t ) - φ F ) since V of M is not zero (when V = ) due to the presence of int tatic MO Full dder ircuit! out =! in & (!!) (! &!) tatic MO Full dder ircuit!um = out & (!!! in ) (! &! &! in ) in in in! out!um in in in! out!um in in in in out = in & ( ) ( & ) um =! out & ( in ) ( & & in ) 9/4/5 VLI esign I;. Milenkovic 45 9/4/5 VLI esign I;. Milenkovic 46 VLI esign I;. Milenkovic 8