COMP 103 Lecture 10 Inverter Dynamics: The Quest for Performance Section 5.4.2, 5.4.3 [All lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al.] COMP103-L10.1 What is this lecture+ about? PERFORMANCE 1. Factors affecting performance: C L, W/L, VDD, 2. The ratio of the PMOS to NMOS could be optimized for symmetrical t phl & t plh and symmetric VTC but here we learn how to set the ratio to optimize t p 3. While sizing up an inverter reduces its delay, it also increase its input capacitance impacting the delay of the driving gate! (selfloading). What s the best sizing? In Out 4. Now we can size a chain of inverters.. If C L is given - How should the inverters be sized? - How many stages are needed to minimize the delay? 5. What about input slope impact (instead of a step)? 6. What about inverters with long wire delays inbetween? COMP103-L10.2 C g,1 1 C L = 8 C g,1
Inverter Propagation Delay, revisited Propagation delay is proportional to the time-constant of the network formed by the pull-down resistor and the load capacitance V DD t phl = f(r n, C L ) R n C L V out = 0 t phl = ln(2) R eqn C L = 0.69 R eqn C L t plh = ln(2) R eqp C L = 0.69 R eqp C L V in = V DD t p = (t phl + t plh )/2 = 0.69 C L (R eqn + R eqp )/2 To equalize rise and fall times make the on-resistance of the NMOS and PMOS approximately equal. COMP103-L10.3 Inverter Propagation Delay, Revisited To see how a designer can optimize the delay of a gate have to expand the R eq in the delay equation t phl = 0.69 R eqn C L t p(normalized) = 0.69 (3/4 (V DD )/I DSATn ) C L 0.52 C L / (W/L n k n V DSATn ) 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 For VGS = VDD, VDS = VDD-> VDD/2 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 V DD (V) COMP103-L10.4
Derivation of Reqn COMP103-L10.5 Yes. That should have looked familiar.. Same results with simulated equivalent resistance of a minimum size NMOS transistor R eq (Ohm) 7 6 5 4 3 2 1 x10 5 (for V GS = V DD, V DS = V DD V DD /2) 0 0.5 1 1.5 2 2.5 V DD (V) V DD (V) NMOS(kΩ) PMOS (kω) 1 35 115 1.5 19 55 2 15 38 2.5 13 31 COMP103-L10.6
Design for Performance Reduce C L COMP103-L10.7 internal diffusion capacitance of the gate itself - keep the drain diffusion as small as possible interconnect capacitance fanout Increase W/L ratio of the transistor the most powerful and effective performance optimization tool in the hands of the designer watch out for self-loading! when the intrinsic capacitance dominates the extrinsic load Increase V DD can trade-off energy for performance increasing V DD above a certain level yields only very minimal improvements reliability concerns enforce a firm upper bound on V DD NMOS/PMOS Ratio Concerns: symmetrical VTC equal high-to-low and low-to-high propagation delays speed, t p So far have sized the PMOS and NMOS so that the R eq s match (ratio of 2-3) symmetric VTC, equal t phl & t plh If speed is the only concern, reduce the width of the PMOS device! What happens? There must be a ratio β = (W/L p )/(W/L n ) that optimizes t p!! r = R eqp /R eqn (resistance ratio of identically-sized PMOS and NMOS) COMP103-L10.8 β opt = r when wiring capacitance is negligible
Derivation of β opt COMP103-L10.9 PMOS/NMOS Ratio Effects -- Simulation 5 x 10-11 t p (sec) 4.5 4 3.5 t plh t phl t p β of 2.4 (= 31 kω/13 kω) gives symmetrical response β of 1.6 to 1.9 gives optimal performance 3 1 2 3 4 5 β = (W/L p )/(W/L n ) COMP103-L10.10
Device Sizing for Performance Divide capacitive load, C L, into C int : intrinsic - diffusion and Miller effect C ext : extrinsic - wiring and fanout t p = t p0 (1 + C ext /C int ) where t p0 = 0.69 R eq C int is the intrinsic (unloaded) delay of the gate Widening both PMOS and NMOS by a factor S reduces R eq by an identical factor (R eq = R ref /S), but raises the intrinsic capacitance by the same factor (C int = SC iref ) t p = 0.69 R ref C iref (1 + C ext /(SC iref )) = t p0 (1 + C ext /(SC iref )) COMP103-L10.11 t p0 is independent of the sizing of the gate with no load, there is no gain. The drive of the gate is totally offset by the increased capacitance any S sufficiently larger than (C ext /C int ) yields the best performance gains with least area impact Example of finding S Given a time budget of 4 ps, t p0 = 2ps, C ext =9 ff, C int = 3ff, determine the smallest S that would allow tp to meet the timing budget. COMP103-L10.12
Sizing Impacts on Delay t p (sec) x 10-11 3.8 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 for a fixed load 1 3 5 7 9 11 13 15 S The majority of the improvement is already obtained for S = 5. Sizing factors larger than 10 barely yield any extra gain (and cost significantly more area). self-loading effect (intrinsic capacitance dominates) COMP103-L10.13 Can t study delay in isolation Simplest case studied in an inverter chain but basics apply (creatively) to other cases In C g,1 1 2 N C L Out COMP103-L10.14
Impact of Fanout on Delay Extrinsic capacitance, C ext, is a function of the fanout of the gate - the larger the fanout, the larger the external load. Two stages: First, determine the relationship between input loading C g and output loading C int, both are proportional to the gate sizing. Define: γ = C int / C g Second, determine the relationship between the C ext and C g f = C ext /C g (f is the effective fan-out) t p = t p0 (1 + C ext / C int ) = Because γ is close to 1 in most processes, the delay of an inverter is a function of the ratio between its external load capacitance and its input gate capacitance: f COMP103-L10.15 Inverter Chain Our goal is to minimize the delay through an inverter chain In C g,1 1 2 N C L Out The delay through the stages:of the j-th inverter stage is t p, total = t p,j = t p0 (1 + C g,j+1 /(γc g,j )) COMP103-L10.16
Sizing Inverter Chains: The Questions If C g,1 and C L is given Given a fixed number of inverter stages, how should the inverters be sized? How many stages are needed to minimize the delay? And what sizes should they be? COMP103-L10.17 Sizing the Inverters in the Chain How many unknowns are there? (check with the t p, total equation) Take N-1 partial derivatives, and equate to 0. Result: constraints: Cg, j+1 / Cg, j = Cg, j / Cg, j -1, with j = 2,.. N The optimum size of each inverter is the geometric mean of its neighbors Each gate will have the same effective fan-out and the same delay. If each inverter is sized up by the same factor f wrt the preceding gate, then, N N f = C L /C g,1 = F where F represents the overall effective fan-out of the circuit (F = C L /C g,1 ) and the minimum delay through the inverter chain is COMP103-L10.18 t p = N t p0 (1 + ( F ) / γ)
Example of Inverter Chain Sizing In C g,1 1 Out C L = 8 C g,1 C L /C g,1 has to be evenly distributed over N = 3 inverters C L /C g,1 = 8/1 f = COMP103-L10.19