M630/M640 Main Board.

chematics Page Index ( / Revision / hange ate) Page of chematics Page Rev. ate Page 0 chematics Page Index 0 lock iagram 0 Merom(HOT U) / 0 Merom(HOT U) / 0 Merom(Power/nd) / 0 0 LOK N 0 restline (HOT) / 0 restline (MI) / 0 restline (RPHI) / 0 restline (RII) / restline (POWR,V) / restline (V OR) / restline (V) / RII(O-IMM_0) / RII(O-IMM_) / 0 RII(Termination) / LV IH-M( PI/U ) / IH-M( LP,I,T )/ 0 IH-M( PIO) / IH-M( POWR) / IH-M( N) / T H/-ROM (P) (K0) 0 Flash ROM XU/PI Mini ard FN/HWM/HW THRML PROTT XPR ard/m/rf K 0 PI (PI U/TV Tuner) PI ( ILINK) PI (M-UO/) PI (PMI) U PORT & M LN (/) of chematics Page LN (/) V(PI-) / V(TRP) / V(R) / V(POWR) / V(POWR) / V(POWR) / V(MULTIU) / V(LV/V ) / VRM(R) / VRM(R) / VRM(YP) / VRM(YP) / UIO(O & POWR) UIO( MP & HP & PK) UIO( ubwoofer MP) UIO( XT-MI&LIN IN) UIO (MUT & INT-MI) UIO( Q ) (FM00) Power esign iagram IN YPWR(VLW/VLW) RPWR(_/0_V U) VHOR(IL) V POWR(MH) YPWR(_VRUN/_0VRUN) H PWR (VRUN) Others power plan OVP protection ONN RT HOL/O P Rev. ate Page of chematics Page OM OPTION OMPONNT WINON N,RP N TUFF R0.K K OMPONNT amsung Qimonda R tuff N R N tuff - - P P/N: - - - - Project ode & chematics ubject: M0/M0 Main oard R_ NV_ N_ xclude "M0_" (efault) M0M M0PM M0M M0PM V V V V V V V V V V V P. Leader heck by esign by HON HI PRIION IN. O., LT. FOXONN P - R& ivision Index Page ize ocument Number Rev ustom M0/M0 ate: Wednesday, July, 00 heet of

M0/0 lock iagram ("/" Wide creen) TV Tuner ombination. ingle igital. ingle nalog. nalognalog. nalogigital. HybridHybrid " 0X00 WX Panel " 0X00 WX Panel TP0 Power W ub Woofer 0 Watt x Int. peaker.0 Watt x /PIF Out. phi V In -Video In RF IN Int Mic In (Uni) Int Mic In (Omni) OMMON M Only H ONLY Line In Jack Mic In Jack Head Phone Jack RJ VRM RF plitter PMI onn. Type II M_uo_Pro lot /MM lot i-link H H ebug Only *L0 only supports 0MHz RT RT Nvidia NM-T NP- LV 0W mplifier L0H W mplifier x LML FM00 HP mplifier NJMV M. Modem TI Mini-PI lot Mini-PI lot ardus ardreader i.link Q R0 XK udio odec RT (00MHz) PIX *L0 only supports MHz -Link0 *L0 only supports IHM RII RM / MHz O-IMM / MHz O-IMM *L0 only supports MHz PI x PT U.0 x Robson M/lu-Ray O (lot In)." T H U.0 Port x PU Fan.M amera Winbond P nd Fan N K0 IR (U. ) rd Fan Flash IO Mbits LV H udio PI U y kus PI / XU Thermal ensor -Pf (PU/TV) Processor Merom/eleron-M North ridge M PM L0 outh ridge IHM IHM- LP mbedded ontroller M hannel F /00MHz Thermal ensor Pf (V/O-IMM) X MI Nvidia NX V U.0 T x lear utton oard lock en. ILPRYLFT M hannel (Reserved) Pure H/W Thermal hotdown 0 (Reserved) Mini-ard WLN Marvell 0 0/00/000 ase-tx xpress ard NTWP N0P." T H RF Keyboard Mouse Receiver (U.) IR laster RJ TPPW Power W YTM / MX P. INPUT OUTPUT VLW VLW_LO TOUT VLW V YTM / P. INPUT P. INPUT OUTPUT TOUT _V U 0_V U HON HI PRIION IN. O., LT. FOXONN P - R& ivision LOK IRM ize ocument Number Rev ustom M0/0 OUTPUT _V U _VRUN PU / IL INPUT TOUT OUTPUT VHOR PU / MX INPUT TOUT YTM / P. MT/MT P. INPUT OUTPUT *OI on RF keyboard _V U _VRUN YTM / OZ MT(PX_V) INPUT OUTPUT OUTPUT P. VRUN P.0 TOUT _0VRUN TOUT NV_V _V U PX_V Nvidia fx V INPUT OUTPUT VFX_OR _0VRUN (or NV_V) Wednesday, July, 00 ate: heet of

Layout note: no stub on H_TPLK# 0,,,0 OVT_# OVT_# H_T#0 H_RQ#[..0] H_#[..] Layout note: no stub on H_TPLK TP. H_TPLK# to be routed in daisy chain fashion from IH to LP slot and then to PU. H_T# H_0M# H_FRR# H_INN# H_TPLK# H_INTR H_NMI H_MI# VRUN 00 _0VRUN PROHOT# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# PVT / remove TP0,TP,TP,TP,TP,TP,TP,TP,TP,TP R.K_J 00 Q N00W--F P R0 _J 00 Q N00W--F LO_JUMP_0X0 H_TPLK#_R TPLK# LINT0 LINT MI# If PROHOT# is routed between PU,IMVP and MH, pull-up resistor has to be ohm -% IHM's PIO: VIL---> -0.V ~ 0.V VIH--->.0V ~.0.V MROM's PROHOT#: VIL---> -0.V ~ 0.*VP VIH---> 0.*VP ~ VP0. U J []# # H L []# NR# L []# PRI# K []# M []# FR# H N []# RY# F J []# Y# N [0]# P []# R0# F P []# L []# IRR# 0 P []# INIT# P []# R []# LOK# H M T[0]# RT# K RQ[0]# R[0]# F H RQ[]# R[]# F K RQ[]# R[]# J RQ[]# TRY# L RQ[]# HIT# Y []# HITM# U []# R []# PM[0]# W [0]# PM[]# U []# PM[]# Y []# PM[]# U []# PRY# R []# PRQ# T []# TK T []# TI W []# TO W []# TM Y []# TRT# U [0]# R# 0 V []# W []# []# THRML []# []# PROHOT# V T[]# THRM THRM 0M# FRR# THRMTRIP# INN# R ROUP 0 R ROUP M RV[0] N RV[0] T RV[0] V RV[0] RV[0] RV[0] RV[0] RV[0] RV[0] F RV[0] IH RRV XP/ITP INL ONTROL PU OKT_P FOX_PZ-M-0 H LK LK[0] LK[] H_IRR# H_R#0 H_R# H_R# XP_TK XP_TI XP_TM XP_TRT# PROHOT# H_THRM H_THRM PM_THRMTRIP#,,0,,,,,,,, PM_THRMTRIP# H_THRM H_THRM _0VRUN H_# H_NR# H_PRI# H_FR# H_RY# H_Y# H_RQ#0 H_INIT# H_LOK# H_PURT# H_R#[..0] H_TRY# H_HIT# H_HITM# PVT / remove TP,TP,TP0,TP,TP,TP,TP,TP 0MIL TP _0VRUN R _J 00 LK_PU_LK LK_PU_LK# R.K_J 00 Q PLT_RT#, THRMTRIP_FX# _0VRUN R _J 00 H_THRM H_THRM PM_THRMTRIP#, PMT0. VRUN close to cpu V 00 XP_TI XP_TM XP_TK XP_TRT# PM_THRMTRIP# should connect to IH-M and MH without T-ing (No stub) VT : place close to R0 K for N 0 K_J.K for Winbond 00 Q R N_NV_.K_J 00 00 R N_NV_ N_00P_0V_K_ 00 N_PMT0.VT Reserved for FX Over temperature ( degree) protection Q N00PT FOXONN _0VRUN ebug port not used. resistors close to PU. 0.U_V_M 00 RT#_K VT : place close to TUFF for N 0 N for Winbond HON HI Precision Ind. o., Ltd. P - R& ivision LOK IRM ize ocument Number Rev M0/M0 R 00 R0 _ 00 R _F 00 R _F 00 ate: Wednesday, July, 00 heet of

H_#[..0] H_TN#0 H_TP#0 H_INV#0 H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# U [0]# F []# []# []# F []# []# []# []# K []# []# J [0]# J []# H []# F []# K []# H []# J TN[0]# H TP[0]# H INV[0]# T RP 0 T RP []# []# []# []# []# []# []# []# [0]# []# []# []# []# []# []# []# TN[]# TP[]# INV[]# Y V V V T U U Y W Y W W Y U H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_TN# H_TP# H_INV# Place close to PU R K_F 00 R K_F 00 _0VRUN Place close to the PU_TT pin. Make sure PU_TT routing is reference to N and away from other noisy signals. Layout Note: Zo= ohm, 0." max for TLRF. H_TN# H_TP# H_INV# PU_L0 PU_L PU_L R N_K_J 00 R N_K_J 00 H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_TLRF PU_TT PU_TT PVT / remove TP,TP, TP, Route PU_TT/ through a ground referenced Z0 = ohm trace that ends in a via that is near a N via and is accessible through an oscilloscope connection. N K P R L M L M P P P T R L T N L M N F F H_# []# []# H_# []# []# H_#0 []# [0]# H_# []# []# H_# [0]# []# H_# []# []# H_# []# []# 0 H_# []# []# H_# []# []# F H_# []# []# H_# []# []# H_# []# []# H_#0 []# [0]# H_# []# []# H_# [0]# []# F H_# []# []# TN[]# TN[]# TP[]# TP[]# F INV[]# INV[]# 0 OMP0 R._F 00 TLRF OMP[0] R MI OMP R._F 00 TT OMP[] U OMP R._F 00 TT OMP[] OMP R._F 00 TT OMP[] Y TT TT PRTP# H_PRTP#,,0 TT PLP# H_PLP# PWR# L[0] PWROO L[] LP# L[] PI# PU OKT_P FOX_PZ-M-0 Layout Note: omp0, connect with Zo=. ohm, make trace length shorter then 0.". omp, connect with Zo= ohm, make trace length shorter then 0.". T RP T RP H_TN# H_TP# H_INV# H_PWR# H_PWR H_PULP# PI# 0 Layout: onnect test point with no stub PVT / remove TP IMVP (ILRZ-T) cpu PI# <-> ILRZ-T PI# ILRZ-T: VIHmin=0.V VILmax=0.V (ref. IMVP- NO:0) F Frequency Table: L[:0] Freq.(MHz) L L L MHz L L H MHz L H H MHz L H L 00MHz H H L 00MHz H H H Reserve H L H 00MHz H L L MHz HON HI PRIION IN. O., LT. FOXONN P - R& ivision Merom (HOT U) / ize ocument Number Rev M0/M0 ate: Wednesday, July, 00 heet of

0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR VHOR VHOR VHOR VHOR VHOR VHOR VHOR VHOR VHOR 0U_.V_M 00_XR 0U_.V_M 00_XR 0 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR U V[00] V[0] 0 V[00] V[0] 0 V[00] V[00] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] 0 V[00] V[0] V[00] V[0] V[0] V[0] 0 V[0] V[0] 0 V[0] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] 0 V[0] V[0] V[0] V[0] 0 0 V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[0] V[0] V[0] V[0] 0 V[0] V[0] F 0 V[0] V[0] F0 V[0] V[0] F V[0] V[0] F V[00] V[0] F V[0] V[0] F V[0] V[0] F V[0] V[00] F0 V[0] 0 V[0] VP[0] V[0] VP[0] V V[0] VP[0] J V[0] VP[0] K V[0] VP[0] M V[00] VP[0] J 0 V[0] VP[0] K F V[0] VP[0] M F V[0] VP[0] N F0 V[0] VP[0] N F V[0] VP[] R F V[0] VP[] R F V[0] VP[] T F V[0] VP[] T F V[0] VP[] V F0 V[00] VP[] W V[0] V[0] V[0] 0 V[0] V[0] V[0] V[0] VI[0] V[0] VI[] F V[0] VI[] V[0] VI[] F 0 V[0] VI[] V[00] VI[] F 0 V[0] VI[] 0 V[0] V[0] V[0] VN F V[0] V[0] V[0] VN PU OKT_P FOX_PZ-M-0 VN VN P 0U_.V_M ame Length Layout Note: Route VN & VN traces at. Ohms with 0 mil spacing. Place PU and P within inch of PU. M width= mil spacing= mil PU_V---->0m PU_VP----->. PU_V------> 0.U_.V_K 00_XR 0U_.V_M 00_XR VI0 0 VI 0 VI 0 VI 0 VI 0 VI 0 VI 0 0.U_.V_K 00_XR L width= mil spacing= mil 0.0U_V_K 00 0m 0.U_.V_K 00_XR VHOR _VRUN R 00_F 00 R 00_F 00 0.U_.V_K 00_XR LYOUT NOT: Place 0.0uF near PIN. 0 mil VN 0 VN 0 0.U_.V_K 00_XR _0VRUN 0.U_.V_K 00_XR PU & P avoid to route with stub lose PU side U V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] V[00] V[0] F V[00] V[0] V[00] V[00] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[00] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[0] V[00] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[0] V[00] V[] V[0] V[] V[0] V[] V[0] V[] F V[0] V[] F V[0] V[] F V[0] V[] F V[0] V[] F V[0] V[] F V[0] V[0] F V[00] V[] F V[0] V[] F V[0] V[] V[0] V[] V[0] V[] V[0] V[] V[0] V[] H V[0] V[] H V[0] V[] H V[0] V[0] H V[00] V[] J V[0] V[] J V[0] V[] J V[0] V[] J V[0] V[] K V[0] V[] K V[0] V[] K V[0] V[] K V[0] V[] L V[0] V[0] L V[00] V[] L V[0] V[] L V[0] V[] M V[0] V[] M V[0] V[] M V[0] V[] M V[0] V[] N V[0] V[] N V[0] V[] N V[0] V[0] N V[00] V[] P V[0] V[] V[] PU OKT_P FOX_PZ-M-0 P P P R R R R T T T T U U U U V V V V W W W W Y Y Y Y F F F F F F F F HON HI PRIION IN. O., LT. FOXONN P - R& ivision Merom (POWR/ROUN) / ize ocument Number Rev M0/M0 ate: Wednesday, July, 00 heet of

_VRUN H0KF-T0 L 0R-00MHZ_00 VP0 VRUN H0KF-T0 L 0R-00MHZ_00 VOUT_LK R N_ 00 R N J 00 Q0 N_ 00 N_00P_0V_K_N 0 0U_.V_M 00_XR 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 0.U_V_Y_Y 00 V_LK_F V_LK_ V_LK_ V_LK_ V_LK_ V_LK_ V_LK_ V_LK_ 0.0U_V_K 00 V_LK_F 0.0U_V_K 00 0.0U_V_K 00 R0 00 _F U_.V_M 00_XR R 00 _F U_.V_M 00_XR R 00 _F U_.V_M 00_XR R 00 V_LK F U_.V_M 0.0U_V_K 00_XR 00 R 00 _F 0U_.V_M 00_XR U_.V_M 00_XR R 00 V_LK F U_.V_M 0.0U_V_K 00_XR 00 V_LK_ 0 0.0U_V_K 00 R#_/F//H pins control R output Table LK_ N_0P_0V N 00 LK_U N_0P_0V N 00 LK_KPI N_0P_0V N 00 N_0P_0V N PLK_ 00 LK_IHPI N_0P_0V N 0 00 LK_IH N_0P_0V N 00 PLK_JI N_0P_0V N 00 0 PLK_MINI 0 PLK_MINI close to clk gen (For MI) F Frequency Table: FL FL FL PU R[:0] PI 0 0 0. 00 0 0. 00 0 0 00 00 0. 00 0 0. 00 0 00 00 0 00 00 Y ITTI_L00-.-0 U.MHZ_0P_0PPM VP0 V_IO VPU_IO 0 VPLL_IO VR_IO PI_TOP# PM_TPPI# 0 P_0V_J_N P_0V_J_N VR_IO VR_IO PU_TOP# TP_PU# 0 RP 00_PR R_LK_MH_LK PUT_F LK_MH_LK Length as short R 00 R_LK_MH_LK# LK_MH_LK# 00 PU_F 0 RP 00_PR as possible. U_XTLIN 0 R_LK_PU_LK X PUT0 LK_PU_LK R0 R_LK_PU_LK# 0 LK J 00 LK_PU_LK# U_XTLOUT PU0 RP 00_PR R _J 00 X R_LK_PI_ROON 0 LK_U RT/PUT_ITP LK_PI_ROON R_LK_PI_ROON# LK_PI_ROON# PU_L0 LP0_LK R/PU_ITP R0.K_J 00 0 PU_L FL/U_MHZ ROON_T#_R ROON_T# R FL/TT_MO RT/R#_F R _F 00 RP 00_PR VOUT_LK R_LK_MH_PLL N RT 0 LK_MH_PLL R_LK_MH_PLL# LK_MH_PLL# R_PLK_IH_JI R R LK_IHPI _J 00 R PI_F/ITP_N MH_LK_RQ#_R MH_LK_RQ# R PLK_JI _J 00 R/R#_ R _F 00 RP 00_PR L R 0 00 R_PLK_MINI R_LK_PI_LN PI RT LK_PI_LN MMZ00T 0R-00MHZ_00 R_LK_PI_LN# R 0 LK_PI_LN# L R 0 00 R_PLK_MINI PI_LN_LKRQ# R PI/TM R/R#_ R N_0K_J MMZ00T 0R-00MHZ_00 RP 00 R_LK_PI_XP LK_PI_XPR R_PLK K RT R R_LK_PI_XP# 0 PLK J 00 PI/_elect R LK_PI_XPR# R LK_KPI _J 00 XPR_T#_R XPR_T# R or PI/R#_ R _F 00,,0,, M_LK_ RP0 00_PR VT : change for I LK,,0,, M_T_ R_LK_PI_MINI# LK_PI_MINI# 00_PR RP T R0 R_LK_PI_MINI LK_PI_MINI R_LK_PI_IH# RT0 LK_PI_IH# R_LK_PI_IH R/R#_ MINI_R_T#_R MINI_R_T# R0 or LK_PI_IH RT/R#_ RT/R#_H R _F 00 RP VT : change for I RFLK_OR_M R_LK_PI_T LK_PI_T RFLK#_OR_M RT//MHZ_nonss RT/TT R_LK_PI_T# R//MHZ_ R/T LK_PI_T# 00_PR TLKRQ#_R TLKRQ# R0 or N PI0/R#_ R _F 00 N VRUN R NV_0K_J 00 R_PLK K NR OT_OR_R0 strap for pin / NR RT0/OTT_ OT#_OR_R0# NR R0/OT_ R R_0K_J 00 N VRUN R R_PLK_MINI NPU 0K_J 00 LK_PWR 0 Overclock not allowed NPI K_PWR/P# R_LK_IH NRF FL/RF0/TT_L LK_IH 0 R _J 00 R 0K_J 00LK_IHPI ILPRLFT strap for pin / VT(update symbol) Hardware trapping (lose to U) R 0K_J 00 M bus ddress : PU_L RP R_ 00_PR 000x(HX:) (IHM) For clock generator _LK R0 N J 00 OT_OR_R0 OT#_OR_R0# RP 00_PR PU_L VPU VR VRF VPI V VPLL MH_L R#_:yte:bit=0, disable R#_;, enable R#_ R R#_F:yte:bit=0, disable R#_F;, enable R#_F R R#_:yte:bit=0, disable R#_;, enable R#_ R R#_H:yte:bit=0, disable R#_H;, enable R#_H R0 VRUN VRUN VRUN VRUN VRUN RP RFLK_OR_M RFLK#_OR_M ROON_T# MH_LK_RQ# R0 0K_J 00 XPR_T# MINI_R_T# TLKRQ# 00_PR RFLK RFLK RFLK# MP / RFLK# R PU_L0 00 NV_ MH_L0 R NV J 00 R LK_PI_P R_NV_XTLIN N_00 R LK_PI_P# R_XTLIN NV J 00 00 R PU_L MH_L R N_00 00 R R N_00 R0 0K_J 00 R 0K_J 00 R 0K_J 00 R 0K_J 00 ROON_T# MH_LK_RQ# XPR_T# MINI_R_T# TLKRQ# 0 HON HI PRIION IN. O., LT. FOXONN P - R& ivision LOK N ize ocument Number Rev M0/M0 R_ ate: Wednesday, July, 00 heet of

_0VRUN _0VRUN _0VRUN R _F 00 R 00_F 00 R._F 00 R._F 00 R._F 00 W/ = 0/0mil H_WIN 0.U_.V_K 00_XR W/ = 0/0mil H_ROMP H_OMP H_OMP# _0VRUN R K_F 00 H_#[..0] H_#[..0] H_PURT# H_PULP# Place ap near MH within 00 mils. H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_WIN H_ROMP H_OMP H_OMP# H_PURT# H_PULP# H_VRF U H_#0 H_# H_# M H_# H H_# H H_# H_# F H_# N H_# H H_# M0 H_#0 N H_# N H_# H H_# P H_# K H_# M H_# W0 H_# Y H_# V H_# M H_#0 J H_# N H_# N H_# W H_# W H_# N H_# Y H_# Y H_# P H_# W H_#0 N H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# Y H_# H_# H_# H_# H_# J H_# H H_# J H_#0 H_# H_# H H_# J H_# H H_# J H_# H_# J H_# J H_# H_#0 J H_# H H_# H H_# H_WIN H_ROMP W H_OMP W H_OMP# H_PURT# H_PULP# H_VRF H_VRF LPM(LU) HOT H_# J H_# H_# H_# M H_# H_# F H_# L H_#0 H_# H_# K H_# H_# L H_# J H_# H_# K H_# P H_# R H_#0 H_# H0 H_# L H_# H_# M H_# N H_# J H_# H_# H_# H_#0 H_# H_# H_# H_# H_# N H_# H_T#0 H H_T# 0 H_NR# H_PRI# H_RQ# F H_FR# H_Y# 0 HPLL_LK M HPLL_LK# M H_PWR# H H_RY# K H_HIT# H_HITM# H_LOK# 0 H_TRY# H_INV#0 K H_INV# L H_INV# H_INV# H_TN#0 M H_TN# K H_TN# H_TN# H H_TP#0 L H_TP# K H_TP# H_TP# J0 H_RQ#0 M H_RQ# H_RQ# H_RQ# H H_RQ# H_R#0 H_R# H_R# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_# H_# H_# H_# H_#0 H_# H_# H_# H_# H_# H_INV#0 H_INV# H_INV# H_INV# H_TN#0 H_TN# H_TN# H_TN# H_TP#0 H_TP# H_TP# H_TP# H_RQ#0 H_RQ# H_RQ# H_RQ# H_RQ# H_R#0 H_R# H_R# PVT / hipset OM change table H_# H_T#0 H_T# H_NR# H_PRI# H_RQ#0 H_FR# H_Y# LK_MH_LK LK_MH_LK# H_PWR# H_RY# H_HIT# H_HITM# H_LOK# H_TRY# H_#[..] H_INV#[..0] H_TN#[..0] H_TP#[..0] H_RQ#[..0] H_R#[..0] R K_F 00 0.U_.V_K 00_XR Z=ohm,Trace Width=mils(M), mils(l). L<0." -RTL-000 (PM) -RTL-000 (M) -RTL-0 (L) HON HI PRIION IN. O., LT. FOXONN P - R& ivision restline (HOT) /of ize ocument Number Rev M0/M0 ate: Wednesday, July, 00 heet of

U Notes: F[:] = Internal Pull-ups F[:] = Internal Pull-downs MH_F_[:0] (F Frequency) MH_F_ (MI Type) MH_F_ (Intel Management ngine rypto trap) MH_F_ (PI raphics Lane) MH_F_[:] (Test Mode Type) MH_F_ (F ynamic OT) MH_F_ (MI Lane Reversal) MH_F_0 (oncurrent VO/PIe), R_LRT# N_0P_0V_J_N 00 N_0K_F 00 00 R NV_ 00 R0 NV_ 00 R NV_ 00 R NV_ 00 VRUN R 0K_J 00 PM_XTT#0 R 0K_J 00 PM_XTT# _V U R0 R0 N_0K_F 00 V U RFLK# RFLK RFLK# RFLK [:0] = 00 = 00MT/s [:0] = 0 = MT/s [:0] = 00 = MT/s Low = MIx High = MIx (efault) Low = Intel Management ngine rypto Transport Layer ecurity (TL cipher suite with no confidentiality High = Intel Management ngine rypto TL cipher suite with confidentiality(efault) Low = Reverse Lane High = Normal operation (efault) [:] = = Normal Operating (efault) [:] = 0 = ll Z Mode [:] = 0 = XOR Mode [:] = 00 = Reserved Low = ynamic OT isabled High = ynamic OT nable (efault) Low = Normal operation (efault) High = Lane Reversed Low = Only VO or PIe is operational (efault) High = VO & PIe operate simultaneously through the PI xpress raphics attach port R 00-0,, IMVP_PWR,,0,,,,,,,, PLT_RT#, PM_THRMTRIP# PM_XTT#0 0,0 PRLPVR N_0.U_V_Y_Y 00 U R0 N_ 00 00 N_LMIMX RIMM_VRF _V U 0 PM_M_UY#,,0 H_PRTP# R0 00 0.U_.V_K 00_XR R K_F 00 R.0K_F 00 R K_F 00 MR_VRF 0.U_.V_K 00_XR 0 0.0U_V_K 00 0.0U_V_K 00,, M_ROMP_VOH 0.U_0V_M 00_XR M_ROMP_VOL.U_0V_M 00_XR M M M_O_RXIN- M_O_RXIN M_VN_RXIN- M_VN_RXIN MH_L0 MH_L MH_L MH_F_ TP0MIL MH_F_ TP0MIL MH_F_ TP 0MIL MH_F_ TP0MIL MH_F_ TP0MIL MH_F_ TP0MIL MH_F_ TP 0MIL MH_F_0 TP0MIL MH_F_ TP0MIL MH_F_ TP00MIL MH_F_ TP0MIL MH_F_ TP00MIL MH_F_ TP0MIL MH_F_ TP 0MIL MH_F_ TP0MIL MH_F_ TP 0MIL MH_F_ TP0MIL MH_F_0 TP00MIL PM_XTT#0 PM_XTT#0 PM_XTT# PM_XTT# R 00 PLTRT#_R R 00 PRLPVR reserved for resume shutdown P RV P RV R RV N RV R RV R RV M RV N RV J RV R RV0 M RV L RV M RV 0 RV H0 RV0 RV J0 RV K RV F RV H0 RV K RV J RV F RV RV RV0 RV J _M _M H RV W0 RV K0 RV LV_T# LV_T RV LV_T# RV0 LV_T RV RV RV RV RV P F0 N F N F F F F F N F F J0 F 0 F R F0 L F J F F 0 F K F M0 F M F L F N F L F0 F[:] internal pull-up F[0:] internal pull-down PM_M_UY# L PM_PRTP# L PM_XT_T#0 J PM_XT_T# W PWROK V0 RTIN# N0 THRMTRIP# PRLPVR J N K N K0 N L0 N L N L N L N K N J N N0 N N 0 N 0 N N K N LPM(LU) RV R MUXIN LK F MI RPHI VI PM M N MI M_K0 M_K M_K M_K M_K#0 M_K# M_K# M_K# M_K0 M_K M_K M_K M_#0 M_# M_# M_# M_OT0 M_OT M_OT M_OT M_ROMP M_ROMP# M_ROMP_VOH M_ROMP_VOL M_VRF0 M_VRF PLL_RF_LK PLL_RF_LK# PLL_RF_LK PLL_RF_LK# P_LK P_LK# MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP FX_VI0 FX_VI FX_VI FX_VI FX_VR_N L_LK L_T L_PWROK L_RT# L_VRF VO_TRL_LK VO_TRL_T LKRQ# IH_YN# TT TT V V W0 W W Y 0 K H J J L K K L R W H H K K N J N N M J N N J J M0 M J J M M M K0 T N M0 M_ROMP M_ROMP# M_ROMP_VOH M_ROMP_VOL MR_VRF MI_TXN0 MI_TXN MI_TXN MI_TXN MI_TXP0 MI_TXP MI_TXP MI_TXP MI_RXN0 MI_RXN MI_RXN MI_RXN MI_RXP0 MI_RXP MI_RXP MI_RXP FT_VR_N MH_LVRF H VO_TRLLK K VO_TRLT 0 R MH_TT_ R0 0K_J 00 M_LK_R0 M_LK_R M_LK_R M_LK_R M_LK_R#0 M_LK_R# M_LK_R# M_LK_R# M_K0, M_K, M_K, M_K, M_#0, M_#, M_#, M_#, M_OT0, M_OT, M_OT, M_OT, 0MILTP 0MILTP RFLK RFLK# RFLK RFLK# _V U R 0_F 00 R 0_F 00 LK_MH_PLL LK_MH_PLL# MI_TXN[:0] MI_TXP[:0] MI_RXN[:0] MI_RXP[:0] 0MILTP 0MILTP 0MILTP 0MILTP 0MILTP0 VT : FT_VR_N change to TP L_LK0 0 L_T0 0 MPWROK 0 L_RT#0 0 MH_LK_RQ# MH_IH_YN# 0 _VRUN HON HI PRIION IN. O., LT. FOXONN P - R& ivision restline (MI) of ize ocument Number Rev M0/M0 R _F 00 ate: Wednesday, July, 00 heet of 0.U_.V_K 00_XR PR K_F 00

VRUN PVT / : isable RT R N_0K_J R N_0K_J PVT / : isable RT, delete R, R0, N : R tuff : R U R NV_ M_T R NV_ M_LK R R R R R M_HYN M_VYN M_LU M_RN M_R When disable RT, hange R,R, R from 0R to 0R R TV_ R TV_ R TV_ When disable TV/RT, hange R,R,R from R to 0R PVT / : isable RT M_VYN M_HYN M_T M_LK VRUN R N_.K_J 00 R0 N_.K_J 00 PVT / : isable RT M_R M_RN M_LU When disable TV/RT tuff R,R0 R N_.K_F 00 R 00 M_R M_RN M_LU M_VYN M_HYN TV_ONL TV_ONL0 R0 NV_ 00 M_VN_RXIN M_VN_RXIN M_VN_RXIN0 M_O_RXIN M_O_RXIN M_O_RXIN0 RT_IRF M_VN_RXIN- M_VN_RXIN- M_VN_RXIN0- M_O_RXIN- M_O_RXIN- M_O_RXIN0- M_VN_LKIN M_VN_LKIN- M_O_LKIN M_O_LKIN- 00 R R_ 00 VRUN R R_ LV_I R R_.K_F00 R0 R R R R_.K_J R_.K_J N_0K_J N_0K_J 00 00 00 00 M_LV_N L T L LK L_TRL_T L_TRL_LK M_INV_N R NV_ 00 M_RJ R NV_ 00 R NV_ 00 R0 NV_ 00 R NV_ 00 RT_VYN RT_TVO_IRF F RT_HYN RT T K RT LK RT_R# F RT_R J RT_RN# K RT_RN RT_LU# H RT_LU P TV_ONL M TV_ONL0 L TV_RTN J TV_RTN F TV_RTN TV_ K TV_ TV_ TV_ TV_ TV_ LV_T LV_T LV_T0 LV_T# LV_T# LV_T#0 F LV_T 0 LV_T 0 LV_T0 F LV_T# LV_T# LV_T#0 LV_LK LV_LK# LV_LK LV_LK# N0 LV_VRFL N LV_VRFH L LV_V L LV_I K0 L_V_N L T L LK 0 L_TRL_T L_TRL_LK H L_KLT_N J0 L_KLT_TRL LPM(LU) TV V LV PI-XPR RPHI P_TX P_TX P_TX P_TX P_TX P_TX0 P_TX P_TX P_TX P_TX P_TX P_TX P_TX P_TX P_TX P_TX0 P_TX# P_TX# P_TX# P_TX# P_TX# P_TX#0 P_TX# P_TX# P_TX# P_TX# P_TX# P_TX# P_TX# P_TX# P_TX# P_TX#0 P_RX P_RX P_RX P_RX P_RX P_RX0 P_RX P_RX P_RX P_RX P_RX P_RX P_RX P_RX P_RX P_RX0 P_RX# P_RX# P_RX# P_RX# P_RX# P_RX#0 P_RX# P_RX# P_RX# P_RX# P_RX# P_RX# P_RX# P_RX# P_RX# P_RX#0 P_OMPO P_OMPI H P_TXP 0 P_TXP P_TXP P_TXP 0 P_TXP P_TXP0 P_TXP Y P_TXP Y P_TXP W P_TXP U P_TXP R P_TXP N0 P_TXP T P_TXP T P_TXP M P_TXP0 H P_TXN P_TXN H P_TXN P_TXN P_TXN P_TXN0 P_TXN W P_TXN W P_TXN Y P_TXN T P_TXN R0 P_TXN N P_TXN U P_TXN U P_TXN N P_TXN0 P_RXP H P_RXP P_RXP H P_RXP P_RXP P_RXP0 Y P_RXP 0 P_RXP W P_RXP W P_RXP T P_RXP T P_RXP U P_RXP M P_RXP L0 P_RXP J0 P_RXP0 P_RXN P_RXN H P_RXN P_RXN 0 P_RXN P_RXN0 W P_RXN P_RXN Y0 P_RXN Y P_RXN U0 P_RXN T0 P_RXN T P_RXN N P_RXN L P_RXN J P_RXN0 M P_OMP N P_RXP[..0] P_RXN[..0] V_P R._F 00 NV_0.U_V_M_ P_TXN0 00 P_RXN_0 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN0 00 P_RXN_0 0 NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXN 00 P_RXN_ NV_0.U_V_M_ P_TXP0 00 P_RXP_0 0 NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ 0 NV_0.U_V_M_ P_TXP 00 P_RXP_ 0 NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ 0 NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP0 00 P_RXP_0 0 NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ 00 NV_0.U_V_M_ P_TXP 00 P_RXP_ NV_0.U_V_M_ P_TXP 00 P_RXP_ P_RXN_[..0] P_RXP_[..0] HON HI PRIION IN. O., LT. FOXONN P - R& ivision restline (fx) of ize ocument Number Rev M0/M0 ate: Wednesday, July, 00 heet of

M Q[..0] M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q M Q M Q M Q M Q M Q M Q M Q0 M Q M Q M Q U R _Q0 W _Q _Q Y _Q R _Q R _Q T _Q W _Q _Q F _Q _Q0 J _Q _Q 0 _Q H _Q _Q W _Q _Q _Q 0 _Q F _Q0 H _Q 0 _Q F0 _Q R0 _Q W0 _Q T _Q W _Q W _Q Y _Q V _Q0 T _Q V _Q T _Q W _Q V _Q U _Q T _Q _Q _Q 0 _Q0 0 _Q _Q Y _Q 0 _Q W _Q _Q _Q _Q Y _Q T _Q0 T _Q Y _Q _Q R _Q R _Q R _Q N _Q M _Q N0 _Q T _Q0 N _Q M _Q N _Q LPM(LU) R YTM MMORY _0 _# _M0 _M _M _M _M _M _M _M _Q0 _Q _Q _Q _Q _Q _Q _Q _Q#0 _Q# _Q# _Q# _Q# _Q# _Q# _Q# _M0 _M _M _M _M _M _M _M _M _M _M0 _M _M _M _R# _RVN# _W# K F L T M M0 M M M M W M M W M M M M Y M M N M M T H P T H P J 0 K H L K J J L 0 J Y0 M Q0 M Q M Q M Q M Q M Q M Q M Q M Q#0 M Q# M Q# M Q# M Q# M Q# M Q# M Q# M 0 M M M M M M M M M M 0 M M M TP_M_RVN# M Q[..0] U M Q0 M 0, P M Q _Q0 _0 Y M 0, M, R M Q _Q _ M, M, W0 M Q _Q _ M, W M Q _Q M #, N M Q _Q _# M #, M M[..0] N0 M Q _Q M M[..0] V0 M M0 M Q _Q _M0 R0 V M M M Q _Q _M 0 M M M Q _Q _M K 0 M M M Q0 _Q _M L M M M Q _Q0 _M H 0 M M M Q _Q _M J M M M Q _Q _M F Y M M M Q _Q _M W M Q[..0] F0 M Q _Q M Q[..0] F M Q0 M Q _Q _Q0 T0 J0 M Q M Q _Q _Q 0 J M Q M Q _Q _Q K J M Q M Q _Q _Q K L M Q M Q0 _Q _Q J K M Q M Q _Q0 _Q L K M Q M Q _Q _Q M Q M Q#[..0] K M Q#[..0] M Q _Q _Q V K M Q#0 M Q _Q _Q#0 U0 J M Q# M Q _Q _Q# 0 L M Q# M Q _Q _Q# L J M Q# M Q _Q _Q# K J M Q# M Q _Q _Q# K K M Q# M Q _Q _Q# K J0 M Q# M Q0 _Q _Q# F L M Q# M Q _Q0 _Q# V M [..0], K M [..0], M Q _Q K M 0 M Q _Q _M0 M M Q _Q _M K M M Q _Q _M M M Q _Q _M W M M Q _Q _M F M M Q _Q _M M M Q _Q _M M M Q0 _Q _M J0 M M Q _Q0 _M Y L M M Q _Q _M K M 0 M Q _Q _M0 L M M Q _Q _M K M M Q _Q _M K0 M M Q _Q _M J M Q _Q J M R#, M Q _Q _R# V TP_M_RVN# M R#, F 0MIL TP M Q _Q _RVN# Y H M Q0 _Q M W#, M Q _Q0 _W# M W#, M Q _Q K M Q _Q M Q _Q M Q _Q J M Q _Q M Q _Q M Q _Q R M Q _Q T M Q0 _Q Y M Q _Q0 Y M Q _Q U M Q _Q T _Q LPM(LU) R YTM MMORY 0MIL TP HON HI PRIION IN. O., LT. FOXONN P - R& ivision restline (RII) of ize ocument Number Rev M0/M0 ate: Wednesday, July, 00 heet 0 of

_VRUN V.M_MH_PLL R 00 _VRUN L R_0UH_00 L0-00K _VRUN R 0._F 00 L R_0UH_00 L0-00K L 0R-00MHZ_00 H0KF-T L 0R-00MHZ_00 H0KF-T U_.V_M_ 00 0m 0m 0m 0m V.M_HPLL V.M_MPLL isable RT & TV: Remove L,L, tuff R nable RT: tuff L,L, Remove R QTV_F isable RT: Remove L,L, tuff R V._PLL V._PLL iable RT & TV tuff R N R nable RT tuff R N R V_TV_TV L V_TV N FILTR R NFMR N_ 00 R N_0.U_.V_K 00 00_XR V._TV NFMR L _FILTR NFMR V._Q L N FILTR _VRUN V. VRUN VRUN R N_ VRUN._RT L V_RT 00 L N FILTR N_0R-00MHZ_00 NFMR LMPN VRUN R N_ 00 V_TV 0m VT : delete filter,reserved R and R for UM/iscrete selection Refer to anta Rosa esgin uide Rev.0 p Table. Removing this filter circuit is recommended to improve the VFX_OR power plane to MH 0.0U_V_M 00_XR N_0U_.V_M R_0U_.V_M P P L LMPN N_0R-00MHZ_00 0 U_.V_M_ 00 N_0U_.V_M R_0U_.V_M P P 0U_.V_M 00_XR 0.U_.V_K 00_XR 0.U_.V_K 00_XR R_0.U_.V_K 00_XR R_0.U_.V_K 00_XR 0.U_.V_K 00_XR N_0.U_.V_K 00_XR R0 NV_ 00 R NV_ 00 R 00 PVT / : isable RT N_0.U_.V_K 00_XR 0m m isable RT: Remove R,,L tuff R PVT / : isable RT PVT / : isable RT R 00 V._PLL V._PLL V.M_HPLL V._TXLV V._PPLL _VRUN R 00 P N_0U_.V_M 00_XR 0U_.V_M isable RT: Remove R tuff V._TV R V.M_MH_PLL _V U R_000P_0V_K_ 00 00_XR 0U_.V_M 00_XR N_U_.V_M 00_XR R_0.U_.V_K m R R_ 00 V.M_MPLL 0.U_.V_K 00_XR V._Q V._PPLL V._PPLL_R 00_XR 0U_.V_M 00_XR 0U_.V_M 00_XR N_0.U_.V_K 00_XR R_0.U_.V_K VRUN 0m m 0m 0m 00_XR U_.V_M 00_XR 0.U_.V_K 00u 0m 00m 0m V._LV 0 00_XR R_U_.V_M 00_XR.U_.V_K 00_XR R_0U_.V_M 0m 00 R N_0.U_.V_K 00_XR UH J K0 U V_TV_ V_TV_ V_TV_ V_TV_ V_TV_ V_TV_ R 00 R N_R_ 00 M V_RT L V_TV R NV_ 00 L LMPN 0R-00MHZ_00 R _F 00 V_RT_ V_RT_ 0 H L M K N U V_YN V V_PLL V_PLL V_HPLL V_MPLL V_LV V_P_ V_P_PLL W V_M V V_M U V_M U V_M U V_M T V_M T V_M T V_M T V_M0 T V_M R V_M_NTF R V_M_NTF V_M_K V_M_K N V V_LV V_P_ V_Q V_HPLL V_P_PLL J V_LV H V_LV LPM(LU) isable LV: Remove R,0, tuff R V._PPLL isable RT: Remove R, tuff R RT PLL K M P LV POWR TV TV/RT LV 0.U_.V_K 00_XR X XF M K MI P VTT HV VTTLF VTT U VTT U VTT U VTT U VTT U VTT U VTT U VTT U VTT U VTT0 U VTT T VTT T VTT T0 VTT T VTT T VTT T VTT T VTT T VTT T VTT0 R VTT R VTT R V_X T V_X U V_X U V_X T V_X T V_X T0 V_X_NTF V_XF V_XF V_XF V_MI J0 V_M_K K V_M_K K V_M_K J V_M_K J V_TX_LV R V_HV 0 V_HV 0 V_P V_P W0 V_P W V_P V V_P V0 V_RXR_MI H0 V_RXR_MI H VRUN V._HV 00m 0m 00_XR 0.U_.V_K _0VRUN VTTLF_P VTTLF VTTLF_P VTTLF F VTTLF_P VTTLF H 0m 00m 00m 00m 00m R_000P_0V_K_ 00 0m 0U_.V_M 00_XR V._TXLV 0.U_.V_K 00_XR 0m V._HV _VRUN U_.V_M 00_XR _VRUN _VRUN 0 00_XR 0.U_.V_K L _V U R_U_00 L0-R0M 0. V_MI R 00 VT: change mainsource H00H-0PT R 00.U_.V_K 00_XR 00_XR 0.U_.V_K R 00 U_.V_M 00_XR 00_XR 0.U_.V_K.U_.V_K 00_XR R NV_ 00 N_U_0V_Y 0_YV 0.U_.V_K 00_XR VT: change mainsource V_P _0VRUN V._M_K _V U HON HI PRIION IN. O., LT. FOXONN P - R& ivision 0.U_.V_K restline (POWR,V) of 00_XR ize ocument Number Rev M0/M0 VT: change mainsource VT : mount P for LV signal abnormal (signal with sine wave ) P R_0U_.V_M MP / V_MI _0VRUN L N_0.0UH_00 WF0-0NM-L0 P 0U_.V_M N_0U_.V_M 00_XR 0.U_.V_K 00_XR 00_XR 0.U_.V_K isable LV: Remove L,P, tuff R ate: Wednesday, July, 00 heet of V_P _0VRUN L 0.0UH_00 WF0-0NM-L0 P 0U_.V_M 0U_.V_M 00_XR 0.U_.V_K 00_XR U_.V_M_ 00 00 U_.V_M_ P N_0U_.V_M L L0-R0M 0. U_00 R _F 00 0U_.V_M 00_XR

_0VRUN R 00 Note: ll VM pins shorted internally. VFX_OR _V U U T V T V H V V V K V J V J V H V H V0 H V F V R0 V U V_M U V_M U V_M V V_M W V_M W V_M Y V_M V_M V_M V_M0 V_M V_M V_M V_M V_M V_M V_M V_M V_M F V_M0 F V_M V_M V_M V_M H V_M H V_M H V_M J V_M J V_M J V_M0 K V_M K V_M K V_M K V_M L V_M U0 V_M V OR R0 V_X T V_X W V_X W V_X Y V_X 0 V_X V_X V_X V_X V_X0 V_X V_X 0 V_X V_X V_X V_X V_X V_X V_X 0 V_X0 V_X V_X V_X F V_X F V_X V_X H0 V_X H V_X H V_X H V_X0 H V_X V_X J0 V_X N V_X POWR V M V FX LPM(LU) V FX NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF V_X_NTF0 V_X_NTF V_X_NTF V_X_NTF V M LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF V_M_LF VFX_OR T T T T T T T U U U U U0 U U U V V V V0 V V V Y Y Y Y Y0 Y Y Y Y Y Y F F H H H H J J J K K L L L L0 L L M M M M0 M M P P P P P0 P P P R0 R R R R V V V Y W W T VFX_OR 00_XR 0.U_.V_K 0 P0 P R_0U_.V_M N_0U_.V_M 0 mils from the dge. 00_XR 0.U_.V_K 00_XR 0.U_.V_K _V U Place 0 where LV and R taps. 0 00_XR 0.U_.V_K 0 00_XR 0.U_.V_K 0 R_0.U_.V_K 00_XR R_0U_.V_M R_U_.V_M_ R_0.U_.V_K R_0.U_.V_K 00_XR R_0.U_.V_K 00_XR 00 00_XR 00_XR VT: change mainsource 0 0.U_.V_K 00_XR 0 00 U_.V_M_ 00 U_.V_M 0VRUN VT: change mainsource P N_0U_.V_M avity apacitors U_.V_M_ 00 Place on the dge. P N_0U_.V_M U_.V_M_ 00 0.U_.V_K 00_XR 0 U_.V_M_ 00 0.U_.V_K 00_XR Place on the dge. 0.U_.V_K 00_XR 0.U_.V_K 00_XR U_.V_M_ 00 0.U_.V_K 00_XR 0.U_.V_K 00_XR _0VRUN R NV_ 00 0.U_.V_K 00_XR avity apacitors N_0.U_.V_K 00_XR 0.U_.V_K 00_XR UF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF V_NTF F V_NTF F V_NTF0 H V_NTF H V_NTF H V_NTF H V_NTF J V_NTF J V_NTF K V_NTF K V_NTF K V_NTF K V_NTF0 V_NTF J V_NTF M V_NTF L V_NTF L V_NTF V_NTF V_NTF V_NTF P V_NTF P V_NTF0 R V_NTF R V_NTF Y V_NTF Y V_NTF Y V_NTF Y V_NTF Y V_NTF T0 V_NTF T V_NTF T V_NTF0 U V_NTF U V_NTF U V_NTF U V_NTF U V_NTF U V_NTF V V_NTF V V_NTF V V_NTF V V_NTF0 L V_XM_NTF L V_XM_NTF L V_XM_NTF M V_XM_NTF M V_XM_NTF M V_XM_NTF M V_XM_NTF M V_XM_NTF M V_XM_NTF P V_XM_NTF0 P V_XM_NTF P V_XM_NTF P V_XM_NTF L V_XM_NTF L V_XM_NTF L V_XM_NTF R V_XM_NTF R V_XM_NTF R V_XM_NTF LPM(LU) HON HI PRIION IN. O., LT. FOXONN P - R& ivision restline(v OR) of ize ocument Number Rev M0/M0 V NTF V NTF POWR V XM NTF V V XM V_NTF T V_NTF T V_NTF U V_NTF U V_NTF V V_NTF V V_NTF V_NTF V_NTF V_NTF0 V_NTF V_NTF F V_NTF F V_NTF K V_NTF M V_NTF M V_NTF P V_NTF P V_NTF R V_NTF0 R V_NTF R V_ V_ V_ V_ L V_ L V 0VRUN V_XM T V_XM T V_XM K V_XM K V_XM K V_XM J V_XM J ate: Wednesday, July, 00 heet of

ize ocument Number Rev ate: heet of HON HI PRIION IN. O., LT. FOXONN P - R& ivision M0/M0 restline (V) of Wednesday, July, 00 ize ocument Number Rev ate: heet of HON HI PRIION IN. O., LT. FOXONN P - R& ivision M0/M0 restline (V) of Wednesday, July, 00 ize ocument Number Rev ate: heet of HON HI PRIION IN. O., LT. FOXONN P - R& ivision M0/M0 restline (V) of Wednesday, July, 00 V UJ LPM(LU) V UJ LPM(LU) V V00 0 V0 V0 V0 V0 V0 V0 V0 V0 V0 0 V0 V V V V V F V F V F V F0 V F0 V0 V V V V V V V V V V0 V V H V H V H V H V J V J V J V J V0 J V J V J V J V K V K V K V L V L V0 L0 V L V L V L V L V L V M V M V M V M V0 M V M0 V M V N V N V N V N V N V N V N V0 N V N V N V P V P V P V P V P0 V R V T V0 T V T V U V U V U0 V W V W V W V0 W V W V W V Y V Y V Y V V V V V Y V Y V Y V Y0 V00 Y V0 P V0 T V0 T V0 T V0 R V0 V0 V0 V0 F V0 F V T V V V H0 V UI LPM(LU) V UI LPM(LU) V V V V V V V V V 0 V V0 V V V 0 V V V V V V0 V V V V V V V V 0 V V0 0 V V V F0 V F V F V F V V V V0 V 0 V H V H0 V H V H V H V J V J V J V0 J V J V J V J V J V J V K0 V K V K V K V0 K V K V L V M V M V M V M V M V M V N V0 N V N V N V N V N V P V P V P0 V R V R V0 R V R V R V R V T0 V T V T V T V W V00 W V0 W V0 W V0 W V0 W V0 Y0 V0 Y V0 Y V0 Y V0 Y V0 Y V Y V Y0 V 0 V 0 V V V 0 V V V0 V V V V V V V V V V0 V 0 V V V V V V V V 0 V0 V V V V V V V V V V0 0 V V V V F V F V F V V V V0 V V V V V H V H0 V H V H V H V0 J V J V J V J V J V J V K V K V K V K V U V U V0 U V U V U V U V U V V V V V W V W V0 K V K V K V L V L V V V V V V K0 V K V L V L V L V0 L V V V

R_VRF _V U N R_VRF VRF V M Q0 V Q.U_0V_M M Q Q0 Q 0.U_V_M Q V 00_XR M Q#0 V M0 00 M Q0 Q#0 V Q0 Q PVT / change to XR M Q V Q M Q Q V 0. F and. F placed Q Q close to VRF pins M Q V Q M Q Q V Q M M Q# V V M Q Q# K0 Q K0# M Q0 V V M Q Q0 Q Q Q V0 V M Q M Q M Q# M Q M Q M Q M Q M Q M M M Q M Q, M_K0 0, M M M M M M M 0 0 M 0 0 0, M 0 0 0, M W# 0 0, M #, M_#, M_OT M Q M Q M Q# M Q M Q M Q M Q0 M Q M M M Q M Q M Q M Q M Q# M Q M Q0 M Q M Q M Q M M M Q M Q,,0,, M_T_,,0,, M_LK_ VRUN 0 0 0 R O-IMM_x00P N_.U_0V_Y_Y N_0.U_V_M_ FOX_0_NRN_F 00 00 V V0 Q Q0 Q Q V V Q# N Q M V V Q Q Q Q V V Q Q Q Q V V M Q# N Q V V0 Q Q0 Q Q V V K0 K V V N _ V V V V 0 V0 V 0/P.mm 0 R# W# 0# V V # OT0 # V V OT N V V Q Q Q Q V V Q# M Q V V Q Q Q Q V V Q Q0 Q Q V V Q# M Q V V Q Q Q Q V0 V Q Q Q Q V V NTT K V0 K# Q# V Q M V V Q0 Q Q Q V V Q Q0 Q Q V V M Q# V Q Q V Q Q V Q V L 0 V(P) N N NPTH NPTH P00 R RM O-IMM (00P) IMM_0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 _V U M Q M Q M M0 M Q M Q M Q M Q M M M Q M Q M Q0 M Q R R_XTT#0 M M N_ 00 M Q M Q M Q M Q M Q# M Q M Q0 M Q M M M M M M M 0.V per IMM=.0 M M Q M Q M M M Q M Q M Q M Q M Q# M Q M Q M Q M Q M Q M M M Q M Q M Q0 M Q M Q# M Q M Q M Q 0_IM0 _IM0 R 0K_J 00 R 00 0K_J M_LK_R0 M_LK_R#0 M_K, M, M 0, M R# 0, M_#0, M_OT0, M_LK_R M_LK_R# PM_XTT#0 Mus ddress: 0(W)/(R) M M[0..] 0 M Q[0..] 0 M Q[0..] 0 M Q#[0..] 0 M [0..] 0, R_VRF R_VRF (0 mil) 0.U_V_M 00 _V U RIMM_VRF R 00 lose to IMM Place these aps near o-imm0. R N_0K_F 00 _V U.U_0V_Y_Y.U_0V_Y_Y.U_0V_Y_Y.U_0V_Y_Y.U_0V_Y_Y 00 00 00 00 00 _V U Place these aps near o-imm0. 0 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 00 00 00 00 R N_0K_F 00 HON HI PRIION IN. O., LT. FOXONN P - R& ivision R(II)O-IMM_0 ize ocument Number Rev M0/M0 ate: Wednesday, July, 00 heet of

R_VRF 0.U_V_M 00.U_0V_M 00_XR PVT / change to XR 0. F and. F placed close to VRF pins M Q0 M Q M Q#0 M Q0 M Q M Q M Q M Q M Q# M Q M Q0 M Q _V U N VRF V Q0 Q V Q#0 Q0 V Q Q V Q Q V Q# Q V Q0 Q V0 V Q Q V M0 V Q Q V Q Q V M V K0 K0# V Q Q V 0 0 0 0 _V U.V per IMM=.0 M Q M Q M M0 M Q M Q M Q M Q M M M Q M Q M_LK_R M_LK_R# M M[0..] 0 M Q[0..] 0 M Q[0..] 0 M Q#[0..] 0 M [0..] 0, VRUN, 0, M 0, M 0 0, M W# 0, M #, M_#, M_K M_OT,,0,, M_T_,,0,, M_LK_ M Q M Q M Q# M Q M Q M Q M Q M Q M M M Q M Q M M M M M M M 0 M Q M Q M Q# M Q M Q M Q M Q0 M Q M M M Q M Q M Q M Q M Q# M Q M Q0 M Q M Q M Q M M M Q M Q N_.U_0V_Y_Y N_0.U_V_M_ 00 00 V V0 Q Q0 Q Q V V Q# N Q M V V Q Q Q Q V V Q Q Q Q V V M Q# N Q V V0 Q Q0 Q Q V V K0 K V V N _ V V V V 0 0 0 V0 V 0 0/P 0 0 R# 0 W# 0# V.mm V # OT0 # V V OT N V V Q Q Q Q V V Q# M Q V V Q Q Q Q V V Q Q0 Q Q V V Q# M Q V V Q Q Q Q V0 V Q Q Q Q V V NTT K V0 K# Q# V Q M V V Q0 Q Q Q V V Q Q0 Q Q V V M Q# V Q Q V Q Q V Q V L 0 V(P) 0 N N 0 NPTH NPTH IMM_ P00 R RM O-IMM (00P) R O-IMM_x00P FOX_0_NRN_F 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 M Q0 M Q R_XTT# M M M Q M Q M Q M Q M Q# M Q M Q0 M Q M M M M M M M 0 M M Q M Q M M M Q M Q M Q M Q M Q# M Q M Q M Q M Q M Q M M M Q M Q M Q0 M Q M Q# M Q M Q M Q 0_IM _IM R0 N_ 00 R0 0K_J 00 00 R0 0K_J M_K, M, M 0, M R# 0, M_#, M_OT, M_LK_R M_LK_R# VRUN PM_XTT# Mus ddress: (W)/(R) Place these aps near o-imm. Place these aps near o-imm. _V U.U_0V_Y_Y.U_0V_Y_Y.U_0V_Y_Y.U_0V_Y_Y.U_0V_Y_Y 00 00 00 00 00 _V U 0 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 0.U_V_Y_Y 00 00 00 00 HON HI PRIION IN. O., LT. FOXONN P - R& ivision R(II)O-IMM_ ize ocument Number Rev M0/M0 ate: Wednesday, July, 00 heet of

0_V U M R0 00 _J, M_OT R 00 _J, M_K R 00 _J 0, M [0..],, 0, M M M M M R R R 00 _J 00 _J 00 _J 0, M [0..] 0, M # 0, M W#, M_#, M_OT RP 0_V U M M M M R 00_PR RP 0 0.U_.V_K 00_XR 0 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 00_XR 00_XR 00_XR 00_XR 0 0 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 0, M R#, M_#, M_OT M R 00_PR RP Layout note: Place cap close to every R-pack terminated to 0 VU 0, M M M M 0 R 00_PR RP, M_K M M M R 00_PR RP 0_V U 0 0 0 0 00 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 00_XR 0.U_.V_K 00_XR 0.U_.V_K 0.U_.V_K 0.U_.V_K 0.U_.V_K 00_XR 00_XR 00_XR 00_XR 0.U_.V_K 00_XR 0, M 0, M_OT0, M_#0 0, M R# M 0 M M M R 00_PR RP R RP 00_PR Layout note: Place cap close to every R-pack terminated to 0_V U 0, M M 0 M M R 00_PR RP0 0, M W# 0, M 0, M_# 0, M # R 00_PR RP, 0,, M_K0 M M_K M M M M M R 00_PR RP R RP 00_PR M M M M 0 R 00_PR RP R 00_PR HON HI PRIION IN. O., LT. FOXONN P - R& ivision R(II)Termination ize ocument Number Rev M0/M0 ate: Wednesday, July, 00 heet of

NV_O_LKIN- NV_O_LKIN O_LKIN- O_LKIN NV_VN_RXIN- NV_VN_RXIN NV_VN_RXIN- NV_VN_RXIN NV_VN_LKIN- NV_VN_LKIN NV_VN_RXIN0- NV_VN_RXIN0 NV_VN_RXIN- NV_VN_RXIN RN RN O_RXIN0- NV_O_RXIN0- M_O_RXIN0- O_RXIN0 NV_O_RXIN0 M_O_RXIN0 NV_O_RXIN- O_RXIN- M_O_RXIN- O_RXIN NV_O_RXIN M_O_RXIN RN RN O_RXIN- NV_O_RXIN- M_O_RXIN- O_RXIN NV_O_RXIN M_O_RXIN O_RXIN- NV_O_RXIN- M_O_RXIN- O_RXIN NV_O_RXIN M_O_RXIN NV_LV_N# M_LV_N RP NV_0 0_PR NV_0 0_PR RP RN NV_0 00_PR NV_0 00_PR NV_0 0_PR RN NV_0 0_PR VN_LKIN- VN_LKIN VN_RXIN0- VN_RXIN0 VN_RXIN- VN_RXIN NV_INV_N M_INV_N L_ON_ R NV_K_J 00 RN VN_RXIN- VN_RXIN VN_RXIN- VN_RXIN VRUN Q NV_TU L_ON_ LV_N M_O_LKIN- M_O_LKIN M_VN_LKIN- M_VN_LKIN M_VN_RXIN0- M_VN_RXIN0 M_VN_RXIN- M_VN_RXIN M_VN_RXIN- M_VN_RXIN M_VN_RXIN- M_VN_RXIN NVII F UT TO PULL OWN RITOR R NV_0K_J 00 RP R_0 00_PR R_0 0_PR RP R_0 00_PR RN R_0 0_PR R_0 0_PR NV_ R R R_ Reserved For ctive High nable ignal R0 N_NV_ R R_ 00 R_0 0_PR R K_J 00 PVT / : dd R0 to prevent L unexpect turn on.u_.v_k 00_XR VRUN Vin=.~.V, Vth=.0V Vin=.~.V, Vth=.V U LV0W R0 K_J 00 VRUN N_0P_0V_J_N 00 O_LKIN- N_0P_0V_J_N O_LKIN LV_LV LV_LV 00 N_0P_0V_J_N 00 VN_LKIN- N_0P_0V_J_N VN_LKIN 0 0 00 For MI 0 PNL_I PNL_I0 0 O_LKIN 0 VN_LKIN O_LKIN- 0 VN_LKIN- M0, " O_RXIN0 VN_RXIN0 Type Type Type Type O_RXIN0- VN_RXIN0-0 UO M0PW0 V. V O_RXIN 0 VN_RXIN 00 O_RXIN- VN_RXIN- V O_RXIN VN_RXIN 0 O_RXIN- 0 VN_RXIN- 0 V O_RXIN VN_RXIN 0 O_RXIN- VN_RXIN- 00 INV_NL 0.U_V_Y_Y U IN IN OUT IN N IN N IN THRML P RU_V0. 0 00 0.U_V_Y_Y R K_J 00 LV PVT / change 0.uF N TO _0P FOX_QT000-0-F VT : change to N, NPTH pin has build-in discharge ciucuit.u_.v_k 00_XR LV ONNTOR LV_LV P 0.U_V_Y_Y 0U_.V_M 00 MFIX MFIX NPTH NPTH NV_RJ 0U_V_M 0_XR 0.U_V_M 00_XR R N_ 00 M0, " Type Type Type Type 00 0 0 TOUT M_RJ 00 NV_ UO M0W0 V. HOKURIKU NKO, NM0JJ-PF, INV_TMP_NP INV_TMP_NN R INV_NL NV_0.U_V_Y_Y 00 00P_0V_K_N 00 RJPWM_LPF R R_ 00 R NV_0K_J 00 VRUN 00 N_ V T T 0MIL 0MIL U R INV_RJ 00P_0V_K_N 00 NV_H0W R 0K_J 00 INVRTR ONNTOR V T T T0 T T0 0MIL 0MIL 0MIL 0MIL 0MIL T T T 0MIL 0MIL 0MIL V FL Lamps 0 N0 MFIX MFIX PVUT 0 HR ONN_0P FOX_H0 PVT / for R 00K_J 00 L POWR VT:added for LV power ripple (too large,spec is 00mv) The R will consume about 0.0 Watt (x/0 = 0.0W). We changed resistor to 00 size (/0 Watt) HON HI PRIION IN. O., LT. FOXONN P - R& ivision LV ize ocument Number Rev M0/M0 ate: Wednesday, July, 00 heet of

VRUN VRUN VRUN PI_FRM# PI_TOP# PI_RR# PI_TRY# INT_PIRQ# INT_PIRQ# INT_PIRQ# INT_PIRQ# 0 RP.K 00_PR 0 RP 0_0PR.K RP.K 0_0PR PI_RQ#0 PI_RQ# PI_RQ# PI_RQ# PI Pullups VRUN PI_VL# PI_LOK# PI_PRR# PI_IRY# VRUN INT_PIRQ# INT_PIRQF# INT_PIRQ# INT_PIRQH# 0 PI_[..0] PVT / dd TP for FT test TP TP tpct_0 tpct_0 0 INT_PIRQ# 0 INT_PIRQ# 0 INT_PIRQ# 0 INT_PIRQ# U PI_0 0 PI_ 0 PI_ PI_ 0 PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ 0 PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ 0 0 PI_ PI_ F PI_ PI_ PI_ PI_ PI_ PI_ PI_0 PI_ 0 PI Interrupt I/F F PIRQ# PIRQ# PIRQ# 0 PIRQ# IHM-QN null RQ0# NT0# RQ#/PIO0 NT#/PIO RQ#/PIO NT#/PIO RQ#/PIO NT#/PIO /0# /# /# /# IRY# PR PIRT# VL# PRR# PLOK# RR# TOP# TRY# FRM# PLTRT# PILK PM# PIRQ#/PIO PIRQF#/PIO PIRQ#/PIO PIRQH#/PIO F 0 F PI_RQ# PI_NT# PI_LOK# F0 0 F INT_PIRQ# INT_PIRQF# F INT_PIRQ# INT_PIRQH# PI_RQ# 0 PI_NT# 0 PI_RQ# 0 PI_NT# 0 R N_K_J 00 0MIL TP PI_/#0 0 PI_/# 0 PI_/# 0 PI_/# 0 PI_IRY# 0 PI_PR 0 PI_RT#,0, PI_VL# 0 PI_PRR# 0 PI_RR# 0 PI_TOP# 0 PI_TRY# 0 PI_FRM# 0 PLT_RT#,,0,,,,,,,, LK_IHPI PI_PM# 0 INT_PIRQ# 0 PI_RQ#0 0 PI_NT#0 0 For PI oot IO election. (Need to tune the resistor value) trap for oot-io LP(efault) PI NT0# Hi Hi PI_# Hi LOW PI LOW Hi VLW U_O# U_O# U_O# U_O# LN_RXN LN_RXP LN_TXN LN_TXP XPR_RXN XPR_RXP XPR_TXN XPR_TXP MINI_RXN MINI_RXP MINI_TXN MINI_TXP ROON_RXN ROON_RXP ROON_TXN ROON_TXP RP 0K RP 0 U_O# U_O# 00_PR 0K 0_0PR U_O#0 U_O# U_O# U_O# 0.U_V_M 00 LN_TXN_ 0.U_V_M 00 LN_TXP_ 0.U_V_M 00 0.U_V_M 00 0.U_V_M 00 0.U_V_M 00 0 0.U_V_M 00 0.U_V_M 00 U_O#0 U_O# U_O# U_O# U_O# XPR_TXN_ XPR_TXP_ MINI_TXN_ MINI_TXP_ ROON_TXN_ ROON_TXP_ U_O#0 U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# U_O# U P PRN P PRP N PTN N PTP M PRN M PRP L PTN L PTP K PRN K PRP J PTN J PTP H PRN H PRP PTN PTP F PRN F PRP PTN PTP IHM-QN null PI-xpress PRN/LN_RXN PRP/LN_RXP PTN/LN_TXN PTP/LN_TXP PI_LK PI_0# PI_# PI_MOI F PI_MIO J O0# O#/PIO0 O#/PIO O#/PIO F O#/PIO O#/PIO O#/PIO0 J O#/PIO O# H O# PI irect Media Interface U MI0RXN V MI0RXP V MI0TXN U MI0TXP U MIRXN Y MIRXP Y MITXN W MITXP W MIRXN MIRXP MITXN MITXP MIRXN MIRXP MITXN MITXP MI_LKN T MI_LKP T MI_ZOMP Y MI_IROMP Y MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_PI_IH# LK_PI_IH MI_OMP MI_RXN0 MI_RXP0 MI_TXN0 MI_TXP0 MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP MI_RXN MI_RXP MI_TXN MI_TXP LK_PI_IH# LK_PI_IH R._F 00 U_PN0 UP0N U_PN0 U_PP0 UP0P U_PP0 U_PN UPN H U_PN U_PP UPP H U_PP U_PN UPN H U_PN U_PP UPP H U_PP U_PN UPN J U_PN U_PP UPP J U_PP U_PN UPN K U_PN U_PP UPP K U_PP U_PN UPN K U_PN U_PP UPP K U_PP U_PN UPN L U_PN U_PP UPP L U_PP U_PN UPN M U_PN U_PP UPP M U_PP U_PN UPN M U_PN U_PP UPP M U_PP UPN N UPP N 0MIL TP 0MIL TP URI# F R0 URI URI F._F 00 Place within 00 mils of IH and don't routing next to high speed signals Place within 00 mils of IH _V_PI U PORT PORT-0 PORT- PORT- PORT- PORT- PORT- PORT- PORT- PORT- PORT- HON HI PRIION IN. O., LT. FOXONN P - R& ivision IH-M( PI/MI/U/PI ) / ize ocument Number Rev M0/M0 Function RR- RR- RR- I- I- XPR R MR IR RF K N ate: Wednesday, July, 00 heet of

IH_ITLK P_0V_K 00_NPO IH_TO V 0 VT :add for MI R 0_F 00 RTRT# VccRT R _J 00 R _J 00 R _J 00 R0 0_F 00 TPT attery Holder - T TTRY_P FOX_00-0-F R _J 00 P_0V_K 00_NPO T_L# Min :ms 0 P_0V_K 00_NPO H_M_TOUT H_O_TO VRT R0 M_J 00 U_.V_Y 00_YV R 0K_J 00 00_NPO U_.V_Y 00_YV VRUN R0 0K_J 00 T_RXN0 T_RXP0 T_TXN0 T_TXP0 T_RXN T_RXP T_TXN T_TXP _V_PI H_M_ITLK H_O_ITLK IH_RT# The traces inside this block should be wider. No digital signals routed under XTL VT : vendor test suggestion P_0V_J 00_NPO P_0V_J LK_KX LK_KX RTRT# M_INTRUR# INTVRMN LN00_LP IH_ITLK IH_YN IH_RT# H_O_TIN0 H_O_TIN0 H_M_TIN H_M_TIN TP_H_IN TP 0MIL TP_H_IN TP 0MIL _PROM_WR# M_FLH_N LK_PI_T# LK_PI_T mils lose to door opening Within 00 mils of the IHM,and avoid routing next to clock pins. VT : M flash fail because of PIO can't used as PIO,hange to PIO MP / OPN_JUMP_OPN PJ Y.KHZ_.P_0PPM QM00000 R._F 00 00P_V_K_ 00 00P_V_K_ 00 00P_V_K_ 00 00P_V_K_ 00 00P_V_K_ 00 00P_V_K_ 00 00P_V_K_ 00 00P_V_K_ 00 R0 _J 00 R _J 00 R 0M_J 00 IH_TO T_RXN0_ T_RXP0_ T_TXN0_ T_TXP0_ T_RXN_ T_RXP_ T_TXN_ T_TXP_ R._F 00 Place close to IH H_M_RT# H_O_RT#, U RTX F RTX F INTRUR# F INTVRMN LN00_LP LN_LK LN_RTYN LN_RX0 LN_RX LN_RX LN_TX0 0 LN_TX 0 LN_TX H J H_IT_LK J H_YN H_RT# J H_IN0 H H_IN H H_IN H_IN F0 RTRT# LN_OK#/PIO LN_OMPI LN_OMPO H_OUT TL# F T0RXN F T0RXP H T0TXN H T0TXP TRXN TRXP J TTXN J TTXP T_LKN T_LKP TRI# TRI IHM-QN null IH-M Internal VR nable trap (Internal VR for Vccus_0, Vccus_, VccL_) INTVRMN _PROM_WR# 0 H_OK_N#/PIO H_OK_RT#/PIO F TRXN F TRXP TTXN TTXP PVT / Q sample P/N -HM0N-0000 Q H_M_YN H_O_YN IH LN / LN RT I PU LP T Low= Internal VR isabled High= nternal VR nabled(efault) FWH0/L0 FWH/L F FWH/L FWH/L F FWH/LFRM# LRQ0# LRQ#/PIO 0T F 0M# PRTP# F PLP# FRR# PUPWR/PIO INN# F INIT# INTR 0 RIN# H NMI MI# TPLK# 0 # Y # Y INTVRMN R _J00 R _J00 H_0T H_RIN# VRT IH_YN PM_THRMTRIP_R THRMTRIP# VRUN R K_F 00 R N_ 00 LP_0, LP_, LP_, LP_, LP_FRM#, LP_RQ#0 H_0M# H_PWR H_INN# H_INIT# H_INTR H_NMI H_MI# H_TPLK# TP 0MIL TP I_P[0..] I_P0 0 V I_P U I_P V I_P T I_P V I_P T I_P I_P T I_P T I_P R I_P0 0 T I_P V I_P V I_P U I_P V I_P U IOR# W IOW# W K# Y IIRQ Y IORY Y RQ W I_P0 I_P I_P I_P# I_P# I_PIOR# I_PIOW# I_PK# INT_IRQ I_PIORY I_PRQ R N_K_J 00 IH-M LN00_LP trap (Internal VR for VccLN_0 and VccL_0) LN00_LP _0VRUN I_P[0..] _RIN# _0T Low= Internal VR isabled High= Internal VR nabled(efault) _0VRUN R _J 00 R N J 00 _0VRUN IH_ITLK _0T 0 LN00_LP 0 N_P_0V_K_N 00 H_PRTP#,,0 H_PLP# H_FRR# VRUN VRT H_RIN# R 0K_J 00 H_0T R R 0K_J 00 N J 00 VT:Reserved for disable Thrmtrip R _F 00 PM_THRMTRIP#, N00W--F VRUN H_RIN# H_0T HON HI PRIION IN. O., LT. FOXONN P - R& ivision IH-M( LP/I/T ) / ize ocument Number Rev M0/M0 R N_ 00 R N_ 00 ate: Wednesday, July, 00 heet of _RIN# Q N00W--F R N J 00 R0 N J 00 R0 N_ 00 R K_F 00 Q

VLW VLW M_LINK_LRT# MLINK MLINK0 PM_RI# IMVP_PWR R 0K_J 00 PIO0 R 0K_J 00 _RT# R 0K_J 00 VRUN RP0 0K 00_PR _THRM# R.K_J 00 RUNTIM_I# R0.K_J 00 INT_RIRQ R 0K_J 00 PM_LKRUN# R.K_J 00 I_LP_PI# R00 0K_J 00 YTM_I YTM_I,,,, M_LK_,,,, M_T_ M_LINK_LRT# _PKR PM_TPPI# TP_PU#,,0 PM_LKRUN#,, PI_WK#,,0 INT_RIRQ tuff for No-reboot Low=efault High=No-reboot PM_U_TT# PM_M_UY# MH_IH_YN# YTM_I YTM_I VRUN R N_K_J 00 M_LINK_LRT# MLINK0 MLINK PM_RI# PM_U_TT# PM_YRT# M_LRT# PM_TPPI# TP_PU# INT_RIRQ _THRM# VRMPWR LN_RT# U J MLK MT LINKLRT# MLINK0 MLINK F U_TT#/LPP# Y_RT# MUY#/PIO0 MLRT#/PIO PM_YRT# J R 0K_J 00 TP 0 Port I/F: J TLOW# R H: LP bus TH/PIO I_LP_PI# J R0.K_J 00 N_ L: PI bus TH/PIO RUNTIM_I# H 00 TH/PIO XTMI# PI_WK# R N_PIO PIO,,,0 OVT_# R K_J 00 IO_RII# PIO TH0/PIO _YP H PIO VT : reset,used when program TP_PIO0 PIO TP 0MIL R 0K_J 00 PIO: flash PROM PIO0 0 IMVP_PH 0 TP0 0MIL TP_PIO LOK/PIO H M_LRT# QRT_TT0/PIO MP / M_PWRN R 0K_J 00 QRT_TT/PIO TLKRQ# YTM_I TLKRQ#/PIO F XTMI# VT : reset,used when program YTM_I LO/PIO J R 0K_J 00 TOUT0/PIO YTM_I 0 WK_I# TOUT/PIO R 0K_J 00 0 _PKR PKR F 0 TP_PI#/PIO TP_PU#/PIO PM_LKRUN# H LKRUN#/PIO WK# F RIRQ THRM# J0 J J RI# VRMPWR MH_YN# TP IHM-QN R null N_K_F 00 R N_ 00 R 0K_J 00 M Y PIO PIO VRUN R0 00 0K_J P IO_RII# PLT_RT#,,,,,,,,,, VT : change to Pull Low 0K,check OPN_JUMP_0X LK_IH LK_U U_LK LP_# LP_# LP_# L_LK L_T PIO0 LK_IH LK_U PNL_I0 PNL_I 0MIL TP00 PNL_I0 YTM_I PNL_I 0MIL TP R0 0 00 R 0 00 R 00 0MIL TP L_LK0 L_LK L_T0 L_T PVT / N W W VRUN R R 0K_J 0K_J 00 00 YTM_I YTM_I YTM_I YTM_I N_H0-_W-LI YTM_I YTM_I YTM_I YTM_I PM_LP_#, PM_LP_#, PM_LP_#,, R0 0K_J 00 VRUN R 00 N_0K_J R 00 N_0K_J PVT / etting for L Output "000" V U R L_RT#0.K_F 00 _PWRN# VT : power down,,used when power down WK_I# _RT# 0.U_V_Y 00_YV R 00 N_0K_J L_VRF ~=0.0V R 0K_J 00 R 0K_J 00 R 0K_J 00 R N_0K_J 00 VRUN VLW R N_.K_F 00 R _F 00 R N_.K_F 00 M_LK_ R00.K_J 00 M_T_ R.K_J 00 VRUN VRUN PVT / MI T PIO locks Power MT ontroller Link T0P/PIO J TP/PIO J0 TP/PIO F TP/PIO LK LK ULK LP_# LP_# F LP_# PT LW_PWR _TT#/PIO H 0MIL TP0 IH_PWROK PWROK IMVP_PWR,, R K_J00 0 R _F 00 PRLPVR/PIO J VT : change to K for resume shutdown PRLPVR,0 TLOW# TLOW# R N_00K_J PWRTN# IH_PWRTN_# VT : change to K for resume shutdown 00 LN_RT# PT LN_RT# H0 LW_PWR, 0 RMRT# PM_RMRT#, R0 K_J 00 LK_PWR_IH LK_PWR K_PWR LK_PWR R 00 MPWROK IMVP_PWR LPWROK MPWROK TP_LP_M# LP_M# J L_LK0 F L_LK L_T0 F L_T F L_VRF0 L_VRF H L_RT# J LPIO0/PIO J LRT#/PIO0 J NTTT/PIO F WOL_N/PIO R 00 LK_U I YTM I ON(0) OFF() R N_0.U_V_Y N F 00_YV 00 M_LK_ M_T_ dds.h U V WP L 0 V PROM_OP-_x HTL0 0 0.U_V_Y 00_YV 0 LK_N# R K_J 00 U V N N HW 0 0.U_V_Y 00_YV VRMPWR R 00K_J 00 R N_ 00 N_0P_0V_J_N 00 I I I RT L HON HI PRIION IN. O., LT. FOXONN P - R& ivision IH-M( PIO) / ize ocument Number Rev M0/M0 ate: Wednesday, July, 00 heet 0 of

VLW R 00 VRUN VRUN VLW R0 0 00 0 H00H-0PT 0 U_.V_Y 00_YV R 00 R N_ 00 VRUN _VRUN _VRUN _VRUN 0.U_V_Y 00_YV 0 VRF U_.V_Y 00_YV H00H-0PT L _V_PI VRT 0R-00M_0 HKF-T0 P 0U_.V_M VT : changed by R L 0UH_00 L0-00K. for all V_ R _F 00 L VLNPLL_L UH_00 FI0F-R0K.U_0V_Y 00_YV 0 U_0V_Y 0_YV V._PLL_IH 0U_.V_Y 00_YV VRUN U_.V_Y 00_YV U_.V_Y 00_YV _V_PI VLNPLL 0U_.V_Y 00_YV VRF_U 0 U_0V_Y 0_YV U_.V_Y 00_YV U_.V_Y 00_YV U_.V_Y 00_YV 0.U_V_Y_Y 00 0.U_V_Y_Y 00 V._LN_IH R 00 u m m m 0 U_0V_Y 0_YV m 0m TP 0MIL 0m m.u_v_z 00_YV 0m UF VRT VRF[] T VRF[] VRF_U V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [0] V [] F V [] F V [] V [] H V [] H V [] J V [] J V [] K V [] K V [0] L V [] L V [] L V [] M V [] M V [] N V [] N V [] N V [] P V [] P V [0] R V [] R V [] R V [] R V [] T V [] T V [] T V [] T V [] T V [] U V [0] U V [] V V [] V V [] V V [] W V [] Y V [] J VTPLL V [0] F V [0] V [0] H V [0] J V [0] V [0] V [0] V [0] V [0] V [0] null 0 V [] V [] V [] V [] V [] V [] H V [] V [] V [] VUPLL F V [0] L V [] L V [] M V [] M V [] W V [] F VLN_0[] VLN_0[] F VLN_[] 0 VLN_[] VLN_[] VLN_[] VLN_[] VLN_[] VLN_[] VLNPLL VLN_ m IHM-QN OR VP RX TX VP_OR I PI VPU U OR VPU LN POWR V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[0] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[0] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] V_0[] VMIPLL V_MI[] V_MI[] V_PU_IO[] V_PU_IO[] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[0] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[] V_[0] V_[] V_[] V_[] V_[] VH VUH VU_0[] VU_0[] VU_[] VU_[] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[0] VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] VU_[] VL_0 VL_ VL_[] VL_[] F L L L L L L M M P P T T U U V V V V V V R F F U V W W W Y 0 F J F0 J 0 H TP_VU_0 TP_VU_ P P N.U_0V_Y P 00_YV P P P P R R R R TP0 0MIL TP_VccL_0 TP_VccL_ F0 m. m 0m VRUN _VRUN m m VMIPLL_IH VRUN 0 0.U_V_Y 00_YV VRUN m for all VU_ m 0.U_V_Y 00_YV 0.0U_V_M 00_XR 0.U_V_Y 00_YV 0.U_V_Y 00_YV 0.U_V_Y 00_YV 0.U_V_Y 00_YV 0.U_V_Y 00_YV 0.U_V_Y 00_YV 0.0U_V_Y 00_YV 0 U_0V_Y 0_YV 0.U_V_Y 00_YV 0.U_V_Y 00_YV 00 U_.V_Y 00_YV 0.0U_0V_Y 00_YV 0.U_V_Y 00_YV VLW _0VRUN _0VRUN 0.U_V_Y 00_YV m for all V_ 0MIL TP 0MIL TP P N_0U_.V_M N_0.0U_V_K_ 00 0.U_V_Y 00_YV L0 _VRUN 0UH_00 L0-00K VMIPLL_IH_R R _F 00 0U_.V_Y 00_YV 0.U_V_Y 00_YV VLW 0.U_V_Y 00_YV In non Intel MT systems, these rails should be powered at a minimun in 0-state since PI functionality is power from these wells. 0.U_V_Y 00_YV HON HI PRIION IN. O., LT. FOXONN P - R& ivision IH-M( POWR) / ize ocument Number Rev M0/M0 ate: Wednesday, July, 00 heet of